Digital Design and Programming B38DB

Component Based Logic Design Class Exercises 2 Partial Solutions for you to complete

Problem #1
Develop a minimized Boolean implementation of a ones count circuit that works as follows. The subsystem has four binary inputs A, B, C, D, and generates a 3-bit output, XYZ. XYZ is 000 if none of the inputs are 1, 001 if one input is 1, 010 if two are one, 011 if three inputs are 1, and 100 if all four inputs are 1. (a) Draw the truth tables for XYZ (A, B, C, D). (b) Minimize the functions X, Y, Z using 4-variable K-maps. Write down the Boolean expressions for the minimized Sum of Products form of each function. Repeat the minimization process, this time deriving Product of Sums form.

(c)

Problem #1 Solution (1/6)

(a) Draw the truth tables for XYZ (A, B, C, D).

Problem #1 Solution (2/6)

(b) Minimize the functions X, Y, Z using 4-variable K-maps. Write down the Boolean expressions for the minimized Sum of Products form of each function.

Problem #1 Solution (3/6)

Problem #1 Solution (4/6)

(c) Repeat the minimization process, this time deriving Product of Sums form.

Problem #1 Solution (5/6)

Problem #1 Solution (6/6)

Problem #2
Consider a combinational logic subsystem that performs a two-bit addition function. It has two 2-bit inputs A B and C D, and forms the 3-bit sum X Y Z. (a) Draw the truth tables for XYZ(A,B,C,D). (b) Minimize the functions using 4-variable K-maps to derive minimized Sum of Products forms.

(c) The Full Adder circuit should be familiar. What is the relative performance to compute the resulting sum bits of the 2-bit adder compared to two full adders connected together? (Hint: which has the worst delay in terms of gates to pass through between the inputs and the final outputs, and how many gates is this?).

Problem #2 Solution (1/3)

(a) Draw the truth tables for XYZ(A,B,C,D).

0 1 2 3

00 01 10 11

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Problem #2 Solution (2/3)

(b) Minimize the functions using 4-variable K-maps to derive minimized Sum of Products forms.

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Problem #2 Solution (3/3)

(c) We have previously introduced the Full Adder circuit. What is the relative performance to compute the resulting sum bits of the 2-bit adder compared to two full adders connected together? (Hint: which has the worst delay in terms of gates to pass through between the inputs and the final outputs, and how many gates is this?).

The above circuit is better because there are only two gate levels. But the adder circuit can be used to build adder circuit of more bits. I cant imagine doing a K-map to construct a adder circuit of 64 bits using the method above.

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Problem #3
Show how to implement the full adder Sum(A, B, Cin) and Carry(A, B, Cin) in terms of:

(a) Two 8:1 multiplexers;

(b) Two 4:1 multiplexers; (c) If you are limited to 2:1 multiplexers (and inverters) only, how would you use them to implement the full adder and how many 2:1 multiplexers would you need?

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Problem #3 Solution (1/8)

Ai 0 0 0 0 1 1 1 1

Bi 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

Sum 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

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Problem #3 Solution (2/8)

(a) Two 8:1 multiplexers (Sum);
Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1

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Problem #3 You Complete Carry (3/8)

(a) Two 8:1 multiplexers (Carry);
Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1

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Problem #3 You Complete Sum (4/8)

(b) Two 4:1 multiplexers (Sum);
Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1

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Problem #3 Solution (5/8)

(b) Two 4:1 multiplexers (Carry);
Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1

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Problem #3 Solution (6/8)

(c) 2:1 multiplexers (sum)
Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1

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Problem #3 You Complete Carry (7/8)

(c) 2:1 multiplexers (Carry)
Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1

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Problem #3 Solution (8/8)

(c) 2:1 multiplexers (Sum) Ver 2 - USE the same carry

Ai 0 0 0 0 1 1 1 1

Bi 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1
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Sum 0 1 1 0 1 0 0 1

Problem #4
Design a combinational logic subsystem with three inputs, I3, I2, I1, and two outputs, O1, O0, that behaves as follows. The outputs indicate the highest index of the inputs that is driven high. For example, if I3 is 0, I2 is 1, I1 is 1, then O1, O0 would be 10 (i.e., I2 is the highest input set to 1). (a) Specify the function by filling out a complete truth table. (b) Develop the minimized gate-level implementation using the K-map method. Compare your implementation for (b) and (c). Which is better and under what criterion?

(c) Develop an implementation using two 4:1 multiplexers. (d)

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Problem #4 Solution (1/5)

(a) Specify the function by filling out a complete truth table. I3 I2 0 0 0 0 0 1 1 x I1 0 1 x x O1 0 0 1 1 O0 0 1 0 1

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Problem #4 You Complete (2/5)

(b) Develop the minimized gate-level implementation using the K-map method.

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Problem #4 Solution (3/5)

(c) Develop an implementation using two 4:1 multiplexers. I3 I2 0 0 0 0 0 1 1 x I1 0 1 x x O1 0 0 1 1 O0 0 1 0 1

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Problem #4 You Complete (4/5)

(c) Develop an implementation using two 4:1 multiplexers. I3 I2 0 0 0 0 0 1 1 x I1 0 1 x x O1 0 0 1 1 O0 0 1 0 1

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Problem #4 You Complete (5/5)

(d) Compare your implementation for (b) and (c). Which is better and under what criterion?

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Problem #5
You are to design a simple combinational subsystem to the following specification. The system has the ability to pass its inputs directly to its outputs when a control input, S, is not asserted. It interchanges its inputs when the control input S is asserted. For example, given four inputs A, B, C, D and four outputs W, X, Y, Z, when S=0, WXYZ=ABCD and when S=1, WXYZ=BCDA. Show how to implement this functionality using building blocks that are restricted to be 2:1 multiplexers and 2:1 demultiplexers. Draw your solution below, using black boxes for the mux/demux blocks.

A B C D S

W X Y Z
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Problem #5 Solution
Each output is tied to the output of a 2:1 Multiplexer. S is the select signal.

W X Y Z

C
D

S
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Problem #19
Consider the Equation: Z= A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D Use Shannons decomposition to implement this using 2-1 multiplexers.

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Problem #19 Solution (1/3)

Z= A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D Z = A [B (C D + C D) + B (C D + C D)] + A [B (C D + C D) + B (C D + C D)] = A [B (C xor D) + B (C xor D)] + A [B (C xor D) + B (C xor D)]

= A [( B xor C xor D)] + A [( B xor C xor D)]

= A xor B xor C xor D

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Problem #19 You Complete (2/3)

Z= A xor B xor C xor D Decompose around A: Z = A (B xor C xor D) + A (B xor C xor D)
( B xor C xor D)

Now Decompose (B xor C xor D) around B:

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Problem #19 You Complete (3/3)

Now Decompose (C xor D) around C: C xor D = C D + B D

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