XDR 2

TM

MEMORY ARCHITECTURE

Applications

Benefits
Highest memory performance with reduced power Memory controller compatibility with GDDR5 and DDR3 Scalable system architecture with increased memory transfer efficiency Improved system yield and reduced system level costs

Graphics Gaming Multi-core Computing

DQ [0:7] DQ [8:15] DQ [16:23] DQ [24:31]

RQ [0:3]

Key Innovations

FDMA FlexLinkTM C/A FlexMode Interface

Micro-threading 32X Data Rate Enhanced FlexPhase Circuits

XDR TM2 is the Worlds Fastest DRAM Technology Multi-core processors, graphics cards and game consoles continue to be the marquee performance products for consumers. The insatiable demand for photorealistic game play, 3D images, and a richer end-user experience is constantly pushing system and memory requirements higher. Today's high-end graphics processors support as much as 128 gigabytes per second (GB/s) of memory bandwidth, and future generations will push memory bandwidth to upwards of 500GB/s. Due to the physical limitations of thermals and manufacturing, this increase in performance must also be achieved without significantly increasing the power consumption or pin count over current solutions. Rambus XDR 2 memory architecture, the worlds fastest DRAM technology, is designed to address these enormous bandwidth needs by delivering data rates of up to 20 gigabits per second (Gbps) with best-in-class power-efficiency. This translates to an astounding 80GB/s of bandwidth from a single 4-byte wide XDR 2 DRAM device, dramatically exceeding the bandwidth capabilities of GDDR5 or DDR3 devices. Further, these data rates enable smaller memory controller interfaces and lower pin-counts while minimizing the total memory system bill-of-materials.

Innovative Features The XDR 2 memory architecture incorporates innovations developed through Rambus Terabyte Bandwidth Initiative as well as other key innovations including, Fully Differential Memory Architecture (FDMA), 32X Data Rate, FlexLink Command/Address (C/A), Enhanced FlexPhase circuits, Micro-threading, and FlexMode interface technology. These innovations combine to deliver record-breaking performance, best-in-class power efficiency, improved throughput and scalability in a flexible memory interface that enables a seamless transition from todays single-ended solutions. Total System Solution The XDR 2 controller interface cell is backward compatible with XDR DRAM devices as well as industry standard memories such as GDDR5 and DDR3. This provides system and chip designers the flexibility to develop controllers that meet the broadest range of system requirements. The XDR 2 architecture provides a total system solution addressing many of the complex issues faced by engineers designing cost-effective, power-efficient, highperformance memory subsystems.

Solution Brief

Copyright 2011 Rambus Inc.

Features
Highest pin bandwidth
Up to 20Gbps data rate Enhanced FlexPhase circuis Asymmetric equalization

Highest sustained device bandwidth

Up to 80GB/s total bandwidth per device Micro-threaded 8-bank DRAM core 32-byte access granularity

Low power
FDMA FlexLink C/A 1.5V Vdd

XDR 2 Memory Controller PHY with FlexMode Interface

XDR 2 Memory Interface

Processor
Controller PHY

DQ
x16

C/A C/A

DQ
x16

Multi-modal pins operate as DQ or C/A to maintain PHY footprint

DRAM

DQ
x16

DQ
x16

GDDR5/DDR3 Single-Ended Interface

Fully Differential Memory Architecture Differential signaling improves data rates and power efficiency when compared with single-ended signaling techniques. Rambus pioneered high-speed differential signaling the first implementing this technology in the XDR memory architecture. The XDR 2 architecture employs differential signaling on all key signal connections between the memory controller and the DRAM: data, clock and command/address. Differential signaling inherently reduces noise, such as simultaneous switching output (SSO), crosstalk, and electromagnetic interference (EMI). FlexLink Command and Address FlexLink C/A interface is a full-speed, differential, point-topoint C/A interface technology that provides flexible access granularity and scalable capacity. Using this innovation, the C/A channel can be implemented with as a little as two wires per DRAM device, reducing area, power, pin count, and overall system costs. Operating at up to 20Gbps in the XDR 2 architecture, FlexLink C/A reduces the required number of signal pins on both the DRAM and the memory controller. Given the robust signaling characteristics of differential signaling, FlexLink C/A increases system reliability and provides designers great flexibility through a straightforward means to scale memory system capacity and access granularity. Micro-threading Technology Micro-threading improves transfer efficiency and effective use of DRAM architecture resources by reducing row and column access granularity. It allows minimum transfer sizes to be one fourth the size of typical DRAM devices by using independent

row and column circuitry for each quadrant of physical memory space. Independent addressability of each quadrant also complements the threaded memory workloads of modern graphics and multi-core processors. This unique architecture enables microthreading to maintain the total data bandwidth of the device while reducing power consumption per transaction. 32X Data Rate Technology Rambus' 32X Data Rate technology transfers 32-bits of data per I/O on every clock cycle versus conventional double data rate memory systems which transfer only two bits of data per clock cycle. For example, the XDR 2 architecture can operate at 20Gbps with only a 625 megahertz system clock. This enables a scalable migration path to faster memory with higher resulting device bandwidth while maintaining a more manageable lower-frequency system clock. Use of low-speed system clocks lowers power consumption and reduces complexity and cost in board and system design. FlexMode Interface Technology Rambus' FlexMode interface technology enables multi-modal functionality across differential and single-ended signaling memory types with no additional pin overhead and in a single SoC package design. By using a programmable assignment of signaling pins as either data, or C/A, FlexMode interface technology enables compatibility with industry standard memories including GDDR5 and DDR3 while minimizing signal pin count. By advancing data rates to up to 20Gbps in an extremely power-efficient way with XDR 2 memory, and enabling multi-modal functionality, FlexMode interface technology removes the technical and business barriers for customers to achieve unprecedented capabilities in their products.
Copyright 2011 Rambus Inc.

www.rambus.com