Microelectronic Engineering 113 (2014) 7073

Contents lists available at ScienceDirect

Microelectronic Engineering
journal homepage: www.elsevier.com/locate/mee

Short Note

Deep single step vertical ICPRIE etching of ion beam sputter deposited SiO2/Si multilayer stacks
Ferdinand Messow a,, Colin Welch b, Alexander Eifert a, Wei Chung Ang a, Nee Shiuan Hoe a, Thomas Kusserow a, Hartmut Hillmer a
a b

Institute of Nanostructure Technologies and Analytics Technological Electronics, Heinrich-Plett-Str. 40, 34132 Kassel, Germany Oxford Instruments Plasma Technology, Yatton, Bristol BS49 4AP, United Kingdom

a r t i c l e

i n f o

a b s t r a c t
Deep vertical etching of a 10 lm thick SiO2/Si multilayer stack is presented. The stack was deposited by ion beam sputtering. To etch the stack, an octauorocyclobutane (C4F8)oxygen (O2) based inductively coupled plasma - reactive ion etching (ICPRIE) process was developed. The recipe shows very similar etching rates for silicon dioxide (SiO2) and silicon (Si); thus it can be implemented as a simple one step etching process. In order to protect the stack properly during the etching, a durable hard mask is required. Investigations of the deposition of such a mask, using chromium (Cr) deposited by electron beam physical vapour deposition (EBPVD), are also presented. 2013 Elsevier B.V. All rights reserved.

Article history: Received 25 January 2013 Received in revised form 12 June 2013 Accepted 23 July 2013 Available online 31 July 2013 Keywords: ICPRIE etching SiO2/Si multilayer stack Thin lm Ion beam sputter deposition

1. Introduction Vertical structuring of silicon is commonly used in microelectromechanical systems (MEMS) technology [1,2]. Usually structuring of silicon and its compounds is done by uorinated gas-based ICPRIE. Most studies performed in this eld aim for a high selectivity between silicon and its oxide, so that a single layer of one material may act as hard mask for the corresponding other material, thus allowing deep etching [3,4]. Since silicon and silicon dioxide show different chemical behaviour, the parameters of the etching recipe are then normally adjusted in a way that only one material is etched signicantly. However, if it is required to etch both materials simultaneously, a different approach has to be used. Such simultaneous etching is required for instance in vertical structuring of periodic SiO2/Si thin lm multilayer stacks, commonly used as distributed Bragg reectors (DBR) in infrared optics [57]. Furthermore, SiO2/Si multilayer stacks can be used to create dielectric/air gap DBRs by removing the sacricial Si layers. Such DBRs are promising candidates for broad band high reectivity mirrors for the visible and ultraviolet range [8]. High aspect ratio vertical structuring [9] is essential to obtain high quality factors of these optical devices [10].

Corresponding author. Tel.: +49 561 804 4147; fax: +49 561 804 4488.
E-mail address: messow@ina.uni-kassel.de (F. Messow). 0167-9317/$ - see front matter 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.07.018

The vertical structuring of SiO2/Si multilayer stacks requires two tailored etching recipes due to the individual chemical behaviour of SiO2 and Si [11]. In order to achieve an optimum result, switching between these two recipes has to be accurately timed. This needs precise knowledge of the individual layer thicknesses as well as their etching rates and thus requires pre-investigation of single lm behaviour. Additionally, if the selectivity is not adjustable, the layers of one material in particular may be undercut, leading to rippled sidewalls of the multilayer stack and therefore to poor quality factors. In this paper we present a different approach to vertical multilayer stack etching - using only one recipe for both layer materials. This provides two benets: rstly time-consuming pre-investigation of the etching rates becomes unnecessary and secondly, as both layers are etched with similar rates the tendency for signicant undercutting of either layer is reduced, resulting in smooth sidewalls. As stated above the SiO2/Si stack was deposited by ion beam sputtering. This technique provides several advantages for deposited lms, including high density and quality with excellent uniformity and reproducibility as well as low optical absorption in a broad spectral range. However, due to the high material density of the layers, etching rates will be low, resulting in long process times. Furthermore, since both materials are etched simultaneously, a different etch-resistant mask material is required. The deposition technique of a suitable hard mask (Cr) will be also presented in this paper.

F. Messow et al. / Microelectronic Engineering 113 (2014) 7073

71

2. Materials and methods Samples were prepared as follows. The SiO2/Si multilayer stack was deposited on a silicon wafer substrate by a dual ion beam sputtering technique. Both layer materials were sputtered with an argon ion beam from a 99.999% pure polycrystalline boron doped low resistivity silicon target. The SiO2 layers were obtained by reactive dual ion beam sputtering using an additional oxygen ion beam from an assist source, while the Si layers were deposited directly from the target without further treatment. This created amorphous SiO2 and Si layers. By depositing 29.5 periods of SiO2 and Si with a thickness of 198 nm and 163 nm, respectively, a multilayer stack with thickness of approximately 10 lm was created. After the deposition, the sample was structured by photolithography. Photoresist residue was removed by a two minute descum step in an oxygen incinerator at 40 W. Next Cr was deposited by EBPVD from 99.99% pure Cr pellets. Optimised deposition parameters are given in Section 3.1. Redundant Cr was removed by a liftoff process to leave the patterned Cr hard mask. Next, in order to reduce mechanical stress in the hard mask, the sample was tempered by a rapid thermal annealing (RTA) process, conducted in three steps. Firstly the sample was heated to 290 C for 40 s, secondly further heated to 390 C for 20 s and thirdly allowed to cool down again to room temperature. Samples thus prepared, were then etched by a C4F8 and O2 based ICPRIE recipe. The optimised values of the vertical etching process are given in Section 3.2. Finally the etched samples were treated with a four second dip in buffered ammonium uoride to remove the uorocarbon passivation layer on the etched sidewalls. Evaluation of each process step was performed by means of a scanning electron microscope.

3. Results 3.1. Hard mask deposition Prior to the etching of the SiO2/Si multilayer stack, it was required to choose a suitable hard mask. SiO2 and Si cannot be used, as both materials are etched within the stack. Cr on the other hand is a good candidate as it shows strong resistance to sputtering and chemical reactions, good adhesion to most materials as well as high selectivity in SiO2 and Si etching processes [12]. Therefore Cr was chosen as a hard mask for our experiments. Ion beam sputtered Cr would meet the requirement of high material density and thus being durable during the etching process. This approach was rejected since the sidewalls of the structured photoresist were covered as well, due to the broader angular distribution of the sputtered particles. This would inhibit the subsequent lift-off process. Better results were obtained by electron beam physical vapour deposition (EBPVD), which only coats the top surfaces of the photoresist. Since the density of an evaporated Cr layer is lower than that of a sputtered layer, it needs to be thicker. However, with increasing thickness mechanical stress increases, which might cause lm rupture and delamination, thus making the mask unusable. Therefore, a major aim of this study was to deposit a sustainable Cr hard mask with good adhesion properties. With an established EBPVD process such Cr hard masks were attainable. However, after the lift-off process, the edges of the hard mask were very sloped (Fig. 1(a)). The ICPRIE process will abrade the thin sloped edge of the hard mask, exposing the top SiO2/Si layers. The now unprotected layers will be then etched as well, causing roughened and sloped sidewalls at the top of the stack (Fig. 1(b)). Therefore, in order to provide optimal pattern transfer, a hard mask with perpendicular edges to the stack surface was sought.

Cr hard mask layers with steep sidewalls were obtained by using the established EBPVD process but without substrate holder rotation. However, Cr layers, deposited in this way, were deformed and showed lifted mask edges. This delamination of the steep Cr lms in contrast to the sloped ones can be explained by the differing shape of the edges. For the sloped Cr, the layer is very thin at the edge and the stress is low, resulting in good adhesion, while as the thickness increases from the edge the increasing stress is spread out evenly. When the layer ends abruptly, as is the case for the steep Cr, the stress is not compensated and can only be released by layer deformation (Fig. 1(c)). To decrease the mechanical stress, the effect of different deposition rates was investigated rst. Low deposition rates should give the evaporated atoms more time to arrange in an energetically optimal position, which might lead to lower stress within the layers. However, no signicant difference in bending behaviour of the edges was observed between low (1 /s) and high (3 /s) deposition rates. Further investigations have been performed regarding the inuence of the layers thickness on the mechanical stress. Thin layers should show lower stress values. In order to still obtain the required thickness, the hard mask was deposited in multiple short steps. It was expected this would also enable potential imperfections within one partially deposited layer to be lled up by the subsequent layer. To test the multiple short step deposition technique, two hard mask samples with total thickness of 300 nm were deposited at a rate of 3 /s. One layer was deposited in six steps with a single step thickness of 50 nm. The second layer was deposited in three steps of 100 nm. Each single deposition was interrupted by a 1 h break, giving the deposited Cr atoms sufcient time to arrange in an optimal position. Both layers showed optimal adhesion properties and steep sidewalls, as depicted in Fig. 2 for a Cr hard mask with a three step deposition. Also no fractures or defects within the layer were observed in scanning electron microscope images after a 6 h vertical etching experiment. With this hard mask, vertical etching of the multilayer stack was performed, as will be explained in the following section and is shown schematically in Fig. 1(d). 3.2. Vertical etching The main aim of our investigations was to obtain vertical etched multilayer stacks with smooth sidewalls and a perpendicular prole. To full these requirements, a single step etching process was optimized, which was initially designed for SiO2 etching only [13,14]. During the investigations the parameters of RIE-bias power and oxygen ow were varied. The initial RIE power value was 32 W and yielded etched stacks with nearly perpendicular sidewalls. However, microrods were formed in the vicinity of the etched multilayer stack due to micromasking. This may occur when there is too little ion bombardment energy to eject redeposited Cr particles from the eld which then act as a hard mask. Increased RIE power of 75 W provided enough ion energy to remove the particles and micromasking vanished. However, the higher power reduced selectivity over Cr and the prole was no longer 90 due to Cr erosion. As etching experiments showed better sidewall proles with RIE power of 32 W, we decided to continue our investigations with this lower value and used a different approach to avoid micromasking: with a decreased oxygen ow micromasking was eliminated. We assume that the micromasking was caused by desorbed brittle chromium oxide formed by the previously higher oxygen content. Additionally, the Cr hard mask is less degraded by oxidation, which will increase its lifetime. The decreased oxygen ow also showed a second advantage: by decreasing the oxygen ow from 25 sccm of the initial recipe to

72

F. Messow et al. / Microelectronic Engineering 113 (2014) 7073

Fig. 1. Optimization of the Cr mask deposition. (a) An EBPVD Cr mask deposited with substrate rotation is sloped after lift-off and does not suffer delamination because the stress is spread, (b) but thin edges of the sloped Cr mask are etched back in direction of the arrows by ICPRIE, leading to sloped and roughened sidewalls of the SiO2/Si stack. (c) Conversely an EBPVD Cr mask deposited without rotation is steep after lift-off but suffers delamination due to high stress at the edge. (d) Finally a steep mask deposited as in (c) but with reduced stress by using stepwise deposition avoids delamination as well as damage due to back etching of the mask.

Fig. 2. Scanning electron micrograph of an EBPVD deposited Cr hard mask after optimisation.

Fig. 3. Scanning electron micrograph of a vertically etched SiO2/Si multilayer stack after treatment with buffered ammonium uoride etching solution. The Cr hard mask has not been removed.

10 sccm we were able to minimise the undercut of the Si layers respective to the SiO2 layers. This may be explained by a combination of greater uorocarbon-based passivation due to less oxidation and lower uorine radical concentration at the lower oxygen ow [14,15]. Silicon is well known to be spontaneously and isotropically etched by uorine radicals, whilst uorocarbon passivation can protect the sidewall [16,17]. Lateral etching of SiO2 is much less of a concern because the strong siliconoxygen bond is not spontaneously etched requiring a high degree of perpendicular ion bombardment. We were able to retain very similar etch rates for both Si and SiO2 with the modied process, which is given below. Although literature indicates that etch rates are controlled by the uorocarbon layer thicknesses and that this layer is thicker on Si than SiO2 [17,18], we have struck a balance with the current process. This could be due to equalising passivation lm thicknesses, but it is more likely to be a combination of factors including partial oxidation of Si to retard its etching relative to SiO2. Thus, the lateral Si etch rate can be tailored by varying the partial amount of O2 gas. Concluding, we obtained an optimised single step vertical etching recipe with the following parameters. A mixture of 28 sccm C4F8 and 10 sccm O2 gas gave a good compromise between the protective layer thickness and process cleanliness, whilst maintaining very similar etching rates of SiO2 and Si. All experiments were conducted at 10 mTorr process pressure and with an ICP power of 1500 W. The RIE-power was optimised at 32 W. The helium backside pressure was 10 Torr and the set electrode temperature 20 C.

Vertical etching rates of SiO2 and Si were 41.1 nm/min and 44.3 nm/min respectively, resulting in a total process time of about 6 h. By increasing the ICP power, the process could be made faster. The selectivity between the multilayer stack and Cr was 77:1 meaning less than half of the 300 nm Cr hard mask was consumed by the 10 lm etch. After each hour of etching, the sample was transported to the load lock. Concurrently the chamber was cleaned by a 10 min O2 (50 sccm) and SF6 (6 sccm) plasma before reloading the sample for the next hour of etching. Fig. 3 shows a scanning electron microscope image of a smooth and vertical SiO2/Si multilayer stack etched with the optimised parameters (the uorocarbon passivation layer on the etched sidewalls has been removed with buffered ammonium uoride).

4. Conclusion The development of a single-step recipe for a 10 lm deep vertical etching of ion beam sputtered SiO2/Si multilayer stacks has been presented. The recipe etches SiO2 and Si with nearly equal rates. Furthermore a deposition method for a durable and defect free, steep Cr hard mask has been given. The selectivity between the multilayer stack and Cr was 77:1. The combination of the steep Cr hard mask and the single-step etching recipe has enabled multilayer stacks to be etched with a sidewall prole of 90 and low sidewall roughness.

F. Messow et al. / Microelectronic Engineering 113 (2014) 7073

73

Acknowledgment The research, performed at the Institute for Nanostructure Technologies and Analytics, was funded by the Deutsche Forschungsgemeinschaft (DFG German Research Foundation) in the research project HI 763/14-1.

References
[1] F. Marty, L. Rousseau, B. Mercier, O. Franais, Y. Mita, T. Bourounia, Microelectron. J. 36 (7) (2005) 637. [2] M.-C.M. Lee, D. Hah, E.K. Lau, H. Toshiyoshi, M. Wu, IEEE Photon. Tech. Lett. 18 (2) (2006) 358. [3] R.A. Heinecke, Solid-State Electron. 18 (1975) 1146. [4] F. Gaboriau, G. Cartry, M.-C. Peignon, Ch. Cardinaud, J. Phys. D: Appl. Phys. 39 (2006) 1830. [5] M.K. Emsley, O. Dosunmu, M.S. nl, IEEE J. Sel. Top. Quant. Electron. 8 (4) (2002) 948. [6] D. Hohlfeld, M. Epmeier, H. Zappe, Sensors Actuator A 103 (2003) 93.

[7] L. Yang, M.C. Wu, K. Tai, T. Tanbun-Ek, R.A. Logan, Appl. Phys. Lett. 56 (10) (1990) 889. [8] S. Irmer, K. Alex, J. Daleiden, I. Kommallein, M. Oliveira, F. Rmer, A. Tarraf, H. Hillmer, J. Micromech. Microeng. 15 (2005) 867. [9] C.C. Welch, A.L. Goodyear, T. Wahlbrink, M.C. Lemme, T. Mollenhauer, Microelectron. Eng. 83 (2006) 1170. [10] K.J. Vahala, Nature 424 (2003) 839. [11] A.P. Milenin, C. Jamois, T. Geppert, U. Gsele, R.B. Wehrspohn, Microelectron. Eng. 81 (2005) 15. [12] A.B. Kaul (Ed.), Microelectronics to Nanoelectronics: Materials, Devices & Manufacturability, CRC Press, Boca Raton, USA, 2012. [13] G. Hassall, M.J. Cooke, Temperature and DC bias effects in ICP etching of silicon dioxide, in: Proceeding AVS 47th International Symposium on Vacuum, Thin Films, Surfaces/Interfaces and Processing, Boston, 2000. [14] X. Li, L. Ling, X. Hua, M. Fukasawa, G.S. Oehrlein, M. Barela, H.M. Anderson, J. Vac. Sci. Technol. A 21 (1) (2003) 284. [15] C.J. Mogab, A.C. Adams, D.L. Flamm, J. Appl. Phys. 49 (7) (1978) 3796. [16] M.J. de Boer, J.G.E. Gardeniers, H.V. Jansen, E. Smulders, M.-J. Gilde, G. Roelofs, J.N. Sasserath, M. Elwenspoek, J. Microelectromech. Syst. 11 (4) (2002) 385. [17] T.E.F.M. Standaert, C. Hedlund, E.A. Joseph, G.S. Oehrlein, T.J. Dalton, J. Vac. Sci. Technol. A 22 (1) (2004) 53. [18] M. Matsui, T. Tatsumi, M. Sekine, J. Vac. Sci. Technol. A 19 (5) (2001) 2089.