Project Report

1 Lessons learnt
Follow the installation guidelines properly (read the document before installing the tool) Vl2mv not working properly in cygwin. Beyond some size of the code, it seems to be breaking. As a part of this project, Solaris was used to generate the blif file and then the verification was done using vis in cygwin. Vl2mv doesnt handle the non-blocking assignments and therefore the code needs to be edited properly. Care has to be taken to make sure that the functionality is not changed while using the blocking assignments. A simple example is given below. module fflop(clk, dout,din, lenable); input din; input lenable; input clk; output dout; reg out1; assign dout = out1 & 1'b1; initial out1 = 0; always @(posedge clk) begin if (lenable) out1 = din; // Works out1 <= din; // Doesn't work end Endmodule Read the section on Verilog for VL2MV : Hints and Traps in Ref[1] Be aware of the fact that the combinational outputs can be in any state before settling into the final state. This may lead to many failures of the rules. If required one has to clock them before using. A typical problem faced when checking clock based circuits. module simple(clk, in); input clk; input in; reg latch; initial latch = 0; always @(posedge clk) latch = in; endmodule

If the CTL formula to be checked is,

AG(in = 1 -> AX latch = 1); then it will fail with the following error message :
** mc error: error in parsing Atomic Formula: Node S found in the support of node S. Node S is not driven only by latches and constants. things will not work because in is an input. We need to change the verilog and the formula as follows.

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The problem is that signal in is an input and is not allowed by VIS. To bypass this restriction, create an extra latch that latches the input, and then that latch is used in the formula. This changes the input-output relation, as we would have shifted the time by one timestep. Solution for solving this problem is :
module simple2(clk, in); input clk; input in; reg latch; reg inlatched; initial begin latch = 0; inlatched = 0; end always @(posedge clk) inlatched = in; always @(posedge clk) latch = inlatched; endmodule After this modification, the rule AG(inlatched = 1 -> AX latch = 1) passes. Send questions to the vl2mv SIGs alias id to get inputs from the experts. The following examples talks about the problem with an enable type flipflop. module simple2(clk, in); input clk; input in; input en; reg latch; reg inlatched; reg enlatched; reg din; initial begin latch = 0; inlatched = 0; enlatched=0; end always @(posedge clk) begin inlatched = in; enlatched=en; end always @(inlatched or enlatched) if (enlatched) din=inlatched; else din=1b0; always @(posedge clk) latch = din;

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endmodule AG ((inlatched=1)*(enlatched=1) -> AX (latch=1)) is failing. The above example and the rule are passing when the muxing logic is put with in the second always block. If one wants to use include directive, it has to appear at the end of the file !

1.1

Issues with the tool:

Hardware model has to be given to VIS in an internal format called MV. Vl2MV really caused lot of problems. Here are few of those and how we mitigated those problems a) Vl2mv doesnt support functions. So, all the design has to be rewritten using modules. b) Vl2mv supports module instantiation of only one kind. E.g., even though it supports type module (.in (in), .out (out)), it doesnt support module instantiation in this type Module (.in (in), .out [2] ({x2, x1})); -------------doesnt work Using other kind of instantiation technique can mitigate this problem. Module (in, {x1, x2}) -------------------works. c) Reset signal has to be taken care while writing properties. In each property we have to mention the reset value. d) We need to register all input ports in order to write properties consisting of input signals. e) Unused input and output ports flag error whereas unused signals flag as warnings. f) Delay operators are not allowed. g) Registered variables should be initialized. h) Vis doesnt work in SUSE Linux it works in redhat Linux. i) All the antecedants (variables which are in the left hand side of ->) in CTL formula are to be latched which may are primary inputs or wires, otherwise it result in a mc-error in model checking. j) Care should be taken while invoking another file, i.e. instead of include usr/tmp/filex.h we need to declare as include file usr/tmp/filex.h.