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Novel Three-Phase Three-Level-Stacked Neutral Point Clamped Grid-Tied Solar Inverter With a Split Phase Controller
Yong Wang, Member, IEEE, and Fei Wang
AbstractCharacterized by the low leakage current and high efciency, a three-level neutral point clamped (3L-NPC) inverter becomes more popular for a transformerless photovoltaic grid connected system. The three-level-stacked neutral point clamped (3L-SNPC) structure is a derivative of 3L-NPC providing more advantages such as a double apparent switching frequency and parallel load current paths. In this paper, the power loss distribution and features of 3L-SNPC are analyzed rst when applied to solar inverters. Based on the analysis, a novel 3L-SNPC leg structure is proposed for solar applications in order to reduce the power loss particularly for the low power range, given the fact that solar inverters generally operate in the low power range during most of the daytime. Then, a two-stage solar inverter topology, applying the proposed structure to the phase leg, is described. Further, a split phase controller is applied for the two-stage solar inverter, consisting of the maximum power point tracking control, optimized dc-link voltage control, and grid current control. Finally, a new dead-time elimination pulsewidth modulation strategy is proposed and conveniently implemented to each phase based on the split phase controller. Experimental results are illustrated to demonstrate the applicability of the proposed topology and controller. Index TermsGrid connected, split phase control, three-levelstacked neutral point clamped (3L-SNPC), topology.

I. INTRODUCTION

HOTOVOLTAIC (PV) energy has become a convenient and promising renewable energy source since last decade and current PV systems are capable of generating electricity in a very clean, quiet, and reliable way. In order to achieve low cost, compact size, high reliability and efciency, transformerless topologies have been proposed and increasingly analyzed in the literature. The efciency and the leakage current are two main factors that should be considered during the development of transformerless solar inverters. The study in [1][4] proposed different topologies and modulation techniques to suppress the ground leakage current in transformerless solar inverters. The study in [5] and [6] proposed several novel topologies

Manuscript received May 10, 2012; revised July 27, 2012 and September 11, 2012; accepted October 18, 2012. Date of current version December 7, 2012. This work was supported by the National Nature Science Foundation of China under Project 51177100. Recommended for publication by Associate Editor S. Choi. The authors are with the Key Laboratory of Control of Power Transmission and Conversion, Ministry of Education, Department of Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China (e-mail: wangyong75@sjtu.edu.cn; wy_ywy2@126.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2226475

for single-phase transformerless inverters to achieve higher efciencies. Thereafter, among different transformerless topologies, three-level neutral point clamped (3L-NPC) inverter, as shown in Fig. 1(a), is becoming more attractive for its higher efciency and lower leakage current [7][14]. Derived from 3L-NPC topologies, Floricau et al. [15] proposed the threelevel-stacked neutral point clamped (3L-SNPC) structure, as shown in Fig. 1(b). A 3L-SNPC is made of six switches (i.e., S1 , S1c , S2 , S2c , S3 , and S3c ) disposed on three sides and two clamp diodes (i.e., Dnp c1 and Dnp c2 ). Its exterior sides are made of two switches which are connected serially to support the VDC voltage. The middle side is made of two switches, connected in an opposite way in order to form a bidirectional current path. The clamp diodes are connected similar to the 3L-NPC topology. Floricau et al. [16] proposed an active stacked neutral point clamped converter (3L-ASNPC) as shown in Fig. 1(c). The topology of a 3L-ASNPC is a derivative of the 3L-SNPC structure, having two additional active switches connected antiparallel with the clamp diodes. Various pulsewidth modulation (PWM) strategies have been proposed for the topologies of a 3L-SNPC and 3L-ASNPC. Those topologies together with their PWM strategies are believed to have better performance over a traditional 3L-NPC, in terms of increased apparent switching frequencies, the parallel load current paths, etc. Meanwhile, the study in [15] also provided a PWM-1 strategy for 3L-SNPC as shown in Fig. 2 and Table I. In Fig. 2, V is the reference voltage. With the aforementioned PWM-1 strategy, the simulation results of the 3L-SNPC total power loss distribution, including the switching and conduction losses, are shown in Fig. 3, where fsw , Vdc , and Irm s , load are the switching frequency, dc voltage, and load current, respectively. Apart from the aforementioned 3L-SNPCs advantages, compared with a 3L-NPC, it could also be found from Fig. 3 that a 3L-SNPC also have disadvantages, such as, S1 and S1c and S3 and S3c are highly stressed in the switching power loss, especially for the cases with high switching frequencies. However, the most prominent disadvantage is the relatively high insulated-gate bipolar transistor (IGBT) conduction loss in the low power range due to IGBTs high saturation voltage. This issue becomes a key problem in solar inverters due to the fact that the three-phase PV inverter operates in a relatively low power range during most of the daytime. In this paper, based on the analysis and comparison for power loss distributions in all PV power ranges, a novel 3L-SNPC

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Fig. 1.

Topologies of a 3L-NPC, 3L-SNPC, and 3L-ASNPC. (a) 3L-NPC. (b) 3L-SNPC. (c) 3L-ASNPC.

Fig. 3. Total power loss distribution simulation of PWM-1, courtesy of [15] (modulation index = 0.95, fsw = 1 kHz, V d c = 3000 V, Irm s , lo a d = 130 A).

congured to alleviate the power losses. Moreover, a two-stage solar inverter system with the split phase controller is proposed and tested.
Fig. 2. PWM-1 strategy proposed in [15]. TABLE I OUTPUT VOLTAGE AND SWITCHING SEQUENCE OF PWM-1

II. PROPOSED TWO-STAGE PV INVERTER AND ANALYSIS OF POWER LOSS The structure of the proposed two-stage transformerless PV inverter is shown in Fig. 4. In Fig. 4, two independent solar strings feed energy to the dc link via two conventional boost converters. Energy from the dc link is inverted to the grid through the proposed 3L-SNPC inverter. This design is mainly focused on the efciency improvement in both low and medium power ranges. In each boost converter, two IGBTs are connected in parallel to reduce the conduction loss. However, the main improvement lies in the proposed 3L-SNPC phase leg structure, as called out in Fig. 5. In Fig. 5, two CoolMosfets are paralleled with the outer IGBTs. Moreover, the CoolMosfet and diode structure replaces the IGBTs S1c -Lx and S3 -Lx in 3L-SNPC. It is shown later in this section that the switching loss and the conduction loss, especially in the low power range, are reduced due to those modications. Additionally, two diodes Dp1 -Lx and Dn1 -Lx are added to replace the body diodes in the load current path to alleviate the diodes loss. Fig. 6 shows the proposed 3L-SNPC topological stages in one grid cycle when PWM-1 as illustrated in Fig. 2 is applied.

Output Voltage (VAO) -VDC/2 0 VDC/2

Switch State N O1O2+ P

Switch Sequence S1 0 0 0 1 S1c 1 1 1 0 S2 0 0 1 1 S2c 1 1 0 0 S3 0 1 1 1 S3c 1 0 0 0

leg together with its PWM strategy is proposed to develop a novel three-phase 3L-SNPC inverter for solar applications in order to improve the efciency. However, different from stateof-the-art technologies where the efciency at low power ranges is not emphasized, this paper mainly focuses on the efciency at the low power range, considering the solar inverter operating below 80% power almost all the daytime. A new IGBT + CoolMosfet hybrid power device together with its switching strategy is applied to reduce the outer power devices power loss. IGBT + CoolMosfet hybrid parallel current paths are also

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Fig. 4.

Proposed two-stage PV inverter topology using the proposed 3L-SNPC phase leg.

Fig. 5.

Improved 3L-SNPC phase leg circuit.

Table II shows the power device selection of the proposed phase leg topology with the design consideration aforementioned. The power loss distribution with Table II and PWM-1 is calculated as follows. For simplicity, the ripple current is supposed to be zero. Therefore, Dp1 -Lx and Dn1 -Lx do not conduct any current during the cycle. Since S1c -Lx does not actually conduct, it has no switching loss during the positive half-cycle and the same to S3 -Lx in the negative half-cycle. Therefore, in the positive half-cycle, power losses only happen on S1 -Lx , S2 -Lx , S3 -Lx , and Dnp c1 -Lx . The conduction losses of the outer devices S1 -Lx can be given as 1 PS 1 -Lx -cond = T
T 2

Vce (Pout )

Pout

2 sin(t) ULx

d(t)dt

In Fig. 6, in the positive half-cycle, the P state commutates with the O2+ state as shown in Fig. 6(a) and (b). It indicates that S2 -Lx and S3 -Lx keep ON while S1 -Lx and S1c -Lx are switching with fsw . Different from the conventional 3L-SNPC or 3L-NPC, the outer IGBT S1 -Lx is paralleled with CoolMosfet to reduce the conduction loss in the P state, especially in the low power range, because CoolMosfet has less ON-state voltage especially in the low current case. Moreover, S3 -Lx is replaced by CoolMosfet compared with the conventional 3L-SNPC. Therefore, in the O2+ state, IGBT of S2 -Lx and CoolMosfet of S3 -Lx form a parallel load current path to reduce the conduction loss, particularly in the low power range. The same analysis can be extended to the negative half-cycle as shown in Fig. 6(c) and (d). The previous analysis shows that CoolMosfet with the low conduction resistance can alleviate the conduction loss of the hybrid switch S1 -Lx and S3c -Lx . However, on the other hand, they themselves are still highly stressed with the switching loss because of the modulation mode as shown in Fig. 6, particularly when the switching frequency increases. Therefore, this paper proposes to switch ON earlier and switch OFF later CoolMosfet than its parallel IGBT. With this switching scheme, CoolMosfet dominates most of the dynamic switching process. For example, the power loss caused by the IGBT tail current can be avoided. The aforementioned features lead to a better power losses distribution in all devices. Therefore, the switching frequency could be pushed to a higher level.

(1) where Pout , Vce (Pout ), d(t), UL x , Lx L1 , L2 , L3 are the one phase output ac power, IGBT, and CoolMosfet hybrid structure on state voltage at the certain phase power output, the duty cycle, and the phase voltage, respectively. The switching loss of S1 -Lx is shown in Fig. 7, where E is the function between the IGBT and CoolMosfet hybrid structure switching loss per pulse and the inverter current, f is the grid frequency, and k is the total switching time during one grid period. It should be noted that the switching loss is mostly shared by CoolMosfet because it is designed to turn ON earlier and turn OFF later than the parallel IGBT. More importantly, in this paper, Vce and E for the IGBT and CoolMosfet hybrid structure are not directly from the devices datasheet but derived from the actual test circuit as shown in Fig. 8. Since the ripple current is supposed to be zero, the inner IGBT S2 -Lx and CoolMosfet S3 -Lx only have the conduction loss in the positive half-cycle, given as PS 2 -Lx -cond 1 = T
T 2

Vce (Pout )

Pout

2 sin(t) ULx

dt (2)

PS 3 -Lx -cond =

1 Ts

T 2

Rs (Pout )

Pout

2 sin(t) ULx

(1 d(t))dt.

(3)

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Fig. 6.

Topological stages of PWM-1. (a) P state. (b) O2+ state. (c) N state. (d) O1 state. TABLE II POWER DEVICE SELECTION WITH fsw = 34 kHZ

Dnpc1-Lx=Dnpc2-Lx=Dp2-Lx=Dn2-Lx Dp1-Lx =Dn1-Lx S1-Lx =S3c-Lx S2-Lx =S2c-Lx =S1c-Lx =S3-Lx

FFP30S60S SIDC23D120F6 IPW60R045CP HGTG40N60

Fig. 8.

CoolMosfet and IGBT structure test circuit.

The clamping diodes losses are given as T 1 2 Pout 2 sin(t) PD np c1 -Lx = VFW T 0 ULx
Fig. 7. Flowchart for the switching loss iteration calculation algorithm.

(1 d(t))dt

In (3), Rs (Pout ) is the CoolMosfet on state resistance at the certain phase output power.

(4) where VFW is the diode forward voltage. Equations (1)(4) can be extended to S1c -Lx , S2c -Lx , S3c -Lx , and Dnp c2 -Lx in the negative half-cycle easily. Therefore, based on those equations, the power loss distribution is plotted in Fig. 9(a). The power loss distributions of a 3L-SNPC and 3L-NPC as shown in Fig. 1(b) and (c) are also simulated for comparison.

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Fig. 9.

Power devices losses distribution analysis (fsw = 34 kHz, V d c = 700 V). (a) Proposed 3L-SNPC. (b) 3L-SNPC. (c) 3L-NPC.

Fig. 10.

Two-stage PV inverter with the proposed topology and its split phase controller.

As shown in Fig. 9(b) and (c), a 3L-SNPC improves the 3L-NPCs inner IGBT conduction loss by the parallel load current path. However, the power loss of the outer IGBTs, S1 -Lx , S3c -Lx in a 3L-SNPC, are the same with a 3L-NPC. Therefore, as shown in Fig. 9(a), the proposed 3L-SNPC reduces S1 -Lx , S3c -Lx power losses by the IGBT and CoolMosfet hybrid structure. At the same time, power losses of the inner four power devices in the proposed 3L-SNPC, S2 -Lx , S3 -Lx , S1c -Lx , and S2c -Lx , are also reduced due to the IGBT and CoolMosfet hybrid current parallel path. It can be seen from Fig. 9 that the total power loss reduced by using the proposed 3L-SNPC, compared to a 3L-SNPC, is about 510 w, which is about 0.2% of the rated power.

proposed and applied to the two-stage PV inverter as shown in Fig. 10. In Fig. 10, the PV input voltage range is 2001000 V and the desired dc-link voltage is 700 V, slightly changed according to the instantaneous grid voltage. Therefore, when the PV voltage is lower than 700 V, it will be boosted to 700 V. However, when the input PV voltage is larger than 700 V, the boost converter will be bypassed by the diodes. The string voltages are controlled at Upv1Ref and Upv2Ref by the boost converters in order to achieve MPPT control. The PV voltages are boosted to the dc-link voltage UdcRef which is the lowest possible dc-link voltage to feed power into the grid as shown in (5). It is veried that the lower UdcRef , the higher the boost efciency [17] UdcRef = [2 2 max(UL 1 , UL 2 , UL 3 )/mm ax LX + margin] (5)

III. SPLIT PHASE CONTROLLER DESIGN A split phase controller, including the maximum power point tracking (MPPT), the optimized dc-link voltage control, etc., is

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where UL 1 , UL 2 , UL 3 , mm ax LX , margin are the three-phase grid voltages, the maximum phase modulation index, and a 30 50 V voltage margin considering the grid voltage uctuation and analog-digital (AD) sampling error, respectively. When the PV voltage Upv1Ref and Upv2Ref are larger than the dc-link reference voltage UdcRef calculated by (5), e.g., 700 V, the controller chooses the larger one between Upv1Ref and Upv2Ref as the dc-link voltage reference. The boost converter is now bypassed. Therefore, the MPPT is controlled by the inverter dc-link voltage control loop. Moreover, if Upv1Ref and Upv2Ref are signicantly different from each other (e.g., there is shadow or snow), a tradeoff PV reference voltage will be calculated to optimize the total yielding which can be an interesting future research topic. Therefore, a maximum selection or tradeoff calculation block (as shown in Fig. 10) is designed to determine the input reference voltage for two dc-link voltage P controllers. Meanwhile, the positive and negative half dc-link voltages are both sampled and fed back to two independent P controllers. Two P controllers are commutated at 150 Hz, considering that the dc-link voltage referred to the neutral point has 150 Hz ripple. In this way, the positive and negative half dc voltages are kept balanced. Iam p , as given in (6) and (7), is the dc voltage P controllers output variable added with PV power feedforward component responding to the PV panel power uctuation to improve the dc-link dynamic response Iam p = kp (1/2 UdcRef Udc , Pos ) + k (Ppv1 + Ppv2 )/UdcBus or Iam p = kp (1/2 UdcRef |Udc , Neg |) + k (Ppv1 + Ppv2 )/UdcBus (7) (6)

Fig. 11.

Grid current PR controller.

The harmonic compensators Gh (s) are dened as Gh (s) =

h =3 , 5 , 7

kih

s . s2 + (LX h)2

(10)

Gd -Lx (s) and Gf -Lx (s) in Fig. 11 are the inverter and LCL lter transfer function, respectively. Again in Fig. 10, Ucom m and -Lx , as the output of the PR controller, is taken as the inverter voltage reference. With Ucom m and -Lx , the modulation function mLx can be dened as m m a n d L 1 mL 1 = U c o U sin L 1 t dcB us m m a n d L 2 sin L 2 t mL 2 = U c o U dcB us m = U c o m m a n d L 3 sin t. L3 L3 Ud cB u s

(11)

where UdcBus = Udc , Pos + Udc , Neg and k is the input power feedforward coefcient. The product of Iam p and the digital phase lock loop output variable sin LX (as shown in (8)) is the current reference for the proportional resonance (PR) controller which is proved to have better performance in canceling the steady-state ac current error and in rejecting grid disturbances I = Iam p sin L 1 ref ,L 1 (8) Iref ,L 2 = Iam p sin L 2 Iref ,L 3 = Iam p sin L 3 . The grid currents Igrid ,L 1 , Igrid ,L 2 , and Igrid ,L 3 are other input variables for PR controllers as shown in Fig. 11. It composes of fundamental current controller Gc (s) and the harmonic current compensators Gh (s) = G3 (s) + G5 (s) + G7 (s), acting as notch lters to the third, fth, and seventh harmonics. The fundamental current controller Gc (s) is dened as s Gc (s) = kp 1 + ki 1 2 (9) 2 s + LX where LX is the grid phase frequency in radian per second.

In the grid-tied inverter, the modulation function mLx is obtained from and in phase with the output current Igrid ,L x given the utility power factor. That is, even though S1c -Lx is switching complementarily with S1 -Lx in the positive half-cycle, it actually does not conduct the current. Therefore, the switching signal for S1c -Lx could be disabled if mLx is positive. However, the switching signal for S1c -Lx should be enabled around the zero-crossing point to conduct a high-frequency ripple current which could both have positive and negative current polarities within one switching period. Based on the analysis earlier, this paper proposes a new split phase PWM control strategy for the improved 3L-SNPC as shown in Fig. 12. Phase L1 is used to explain the switch states. Table III shows the switching states with the improved PWM strategy as shown in Fig. 12. Compared to Fig. 2 and Table I, in this case, O1+ and O2 are the added states specic to the new PWM strategy, in which switching signals of S1c -Lx or S3 -Lx are disabled. The P state commutates with O1+ during [1 , 2 ], and the N state commutates with O2 during [3 , 4 ] as shown in Fig. 12. Only around zero-crossing region [2 , 3 ], switching signals of S1c -Lx or S3 -Lx are enabled. The P state commutates with O2+ during [2 , 0] and the N state commutates with O1 during [0, 3 ] as shown in Fig. 12. Therefore, in Fig. 12, S2 -Lx and S2c -Lx work completely with the line frequency while S1c -Lx and S3 -Lx only work with the switching frequency in the short period [2 , 3 ] conducting very low current. Therefore, the dead-time is only necessary in the region of [2 , 3 ] where 2 and 3 are

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Fig. 13.

Flowchart for working region and states judging.

Fig. 12.

Improved PWM strategy for a novel three-phase 3L-SNPC. TABLE III SWITCHING STATES OF THE NEW PWM STRATEGY

Switch states

Switch sequence

S1-Lx P O1+ O2+ O1O2N 1 0 0 0 0 0

S2- Lx 1 1 1 0 0 0

S2c- Lx 0 0 0 1 1 1

S3c- Lx 0 0 0 0 0 1

S1c- Lx 0 0 1 1 1 1

S3- Lx 1 1 1 1 0 0

In the positive half-cycle as shown in Fig. 14(a), (b), and (c), the P state commutates with O2+ only in the narrow region of [2 , 0], the same as the situation shown in Fig. 6. In [2 , 0], both S1 -Lx and S1c -Lx are switching with fs ; therefore, the dead-time must be inserted between those two states. However, in the most region of the positive half-cycle apart from [2 , 0], the P state commutates with the O1+ state as in Fig. 14(b). Therefore, only S1 -Lx is switching ON and OFF and no dead-time is necessary. The same analysis can be extended to the negative half-cycle as shown in Fig. 14(d), (e), and (f). With the new dead-time elimination PWM strategy, the maximum modulation ratio as shown in (14) can be improved because Td , the dead-time, is almost zero mm ax -Lx = 1 Td Ts (14)

determined by |(udcBus uLx ) mLx | |Igrid , Lx | = ILx sin 2 = 2 2Li Lx fsw |(udcBus uLx ) mLx | |Igrid , Lx | = 2 2Li Lx fsw (12)

where Td and Ts are the dead-time and control period, respectively. Moreover, with enhanced mm ax Lx , the dc-link reference voltage UdcRef as shown in (5) can be reduced to improve the system efciency. IV. SYSTEM PARAMETERS DESIGN A 17-kW two-stage PV inverter prototype with the proposed phase leg and its split phase controller is designed and built up in this paper, in which the switching frequency is improved to 34k to reduce the lter size. Therefore, the inverter-side inductance Li Lx is designed as 1 mH to suppress the inverter peak ripple current Ipk Lx to be within 20% Igrid , rated , as shown |(udcBus /2 uLx ) mLx | < 20% Igrid , Lx , rated Li -Lx fsw (15) where Igrid , Lx , rated is the rated inverter current. Next, in order to further attenuate the current ripple to a desired level, an LC second-order lter is used as a part of the LCL lter. The attenuation at the switching frequency can be determined by plotting the bode plot of the transfer function [i.e., (16)], as shown in Fig. 15 Ipk -Lx = 1 Igrid , Lx (s) = . Ii , Lx (s) 1 + Cf Lx Lg Lx s2 (16)

ILx sin 3 =

(13)

where ILx , Igrid , Lx , udcBus , uLx , Li Lx , fsw are the grid phase current amplitude, the grid current ripple, the dc-link voltage, the grid voltage, the inverter-side inductance, and the switching frequency, respectively. The owchart of judging the region is shown in Fig. 13. As shown in Fig. 13, when the ripple current amplitude is larger than the grid current, the modulation function is within the zero-crossing region [2 , 3 ]. The switching signals for S1c -Lx or S3 -Lx should be enabled to provide the load current path. With the proposed PWM strategy based on the split phase controller, the topological stages in one grid cycle for the proposed inverter is shown in Fig. 14.

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Fig. 14. [0, 3 ].

Topological stages corresponding to the switching states. (a) P state. (b) O1+ state. (c) O2+ state in [2 , 0]. (d) N state. (e) O2 state. (f) O1 state in

Fig. 15.

Bode plot of the L g L x C f L x lter transfer function. TABLE IV MAIN EXPERIMENTAL PARAMETERS
Open circuit voltage range PV operating voltage range MPPT range AC output voltage

The Lg Lx Cf Lx is designed as Lg Lx = 150 uH and Cf Lx = 4.7 uF to get around 30 dB attenuation at the switching frequency as it can be seen in Fig. 15. Thus, the grid-side current is highly attenuated. Main system parameters are listed in Table IV. V. EXPERIMENTAL RESULTS The prototype is build up and tested to verify the proposed topology and controller. The experimental waveforms are shown from Figs. 16 to 23. For comparison and simplicity, the open circuit and MPPT voltage UOC /UPV are xed at 800 and 640 V, respectively. In Figs. 16 and 17, the drive signals of S1 -L1 and S1c -L1 are used to demonstrate the new PWM strategy, where S1 -L1 is

U OC U PV

200V-1000V 0.8* U OC 260V-800V 230V 1mH/4.7uF/150uH 2.7mH 34kHz 17kHz Chr oma 62030k1000/30kW-1000V

U grid

Li Lx @0A/ C f Lx / Lg Lx @0A

LBoost @0A
Inverter switching frequency Boost switching frequency Sol ar panel

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Fig. 16. Drive signals and grid current with a new PWM strategy at 8-kW output (green: grid current, 20 A/div, blue: S 1 -L 1 , 10 V/div, yellow: S 1 c -L 1 , 10 V/div, time: 10 ms/div).

Fig. 19. Drive signals for S 1 -L 1 -C o o lM o sfe t (yellow, 5 V/div) and S 1 -L 1 -IG B T (blue, 5 V/div) time: 1 us/div.

Fig. 17. Drive signals and grid current with a new PWM strategy at 12-kW output (green: grid current, 30 A/div blue: S 1 -L 1 , 10 V/div, yellow: S 1 c -L 1 , 10 V/div, time: 10 ms/div).

Fig. 20. Positive dc-link voltage (yellow, 100 V/div), negative dc-link voltage (blue, 100 V/div), U L 1 (green, 250 V/div), U L 2 (250 V/div, purple), time: 10 ms/div.

Fig. 18. Drive signals for S 1 -L 1 -C o o lM o sfe t (yellow, 5 V/div) and S1 -L 1 -IG B T (blue, 5 V/div), time: 400 ns/div.

Fig. 21. Positive dc-link voltage (yellow, 100 V/div), negative dc-link voltage (blue, 100 V/div) U L 1 (purple, 250 V/div), U L 2 (green, 250 V/div), time: 10 ms/div.

working with fsw . However, S1c -L1 is working with fsw only in the narrow region across the zero crossing point. The region width is determined by the load current as shown in Fig. 13. Therefore, in Fig. 17, the region width of S1c -L1 switching is reduced soundly compared to Fig. 16, because the power has been increased from 8 to 12 kW. Figs. 16 and 17 also show that in the negative half-cycle, S1c -L1 is ON state to conduct the current parallel to S2c -L1 . Figs. 18 and 19 show the drive signals for S1 -L1 -IGBT and S1 -L1 -Co olM osfet where CoolMosfet is switching ON earlier and

switching OFF later than IGBT to share most of turn ON/OFF power losses. Figs. 20 and 21 show the dc-link voltage control results, where the dc-link voltage is not xed but slightly changed according to the grid voltage uctuation. Moreover, the positive and negative dc-link voltages can reach very good balance not only with balanced grid voltage as shown in Fig. 20, but also with unbalanced grid voltage as shown in Fig. 21. Fig. 22 shows three-phase current waveforms with full power. It shows relatively large total harmonic distortion, particularly around the zero crossing point because the proposed PWM

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an improved 3L-SNPC phase leg topology together with a new PWM strategy. With the novel construction and PWM strategy, the power losses are reduced especially in the low power range. A 17-kW two-stage solar inverter topology is described and a split phase controller is designed. The novel PWM strategy is also proposed and easily applied to each phase leg with the split phase control scheme. The experimental results from the prototype are shown to verify the applicability of the proposed schemes. REFERENCES
Fig. 22. Three phase currents (50 A/div for all, time: 10 ms/div). [1] B. Yang, W. Li, Y. Gu, W. Cui, and X. He, Improved transformerless inverter with common-mode leakage current elimination for a photovoltaic grid-connected power system, IEEE Trans. Power Electron., vol. 27, no. 2, pp. 752762, Feb. 2012. [2] R. Gonzalez, J. Lopez, P. Sanchis, and L. Marroyo, Transformerless inverter for single-phase photovoltaic systems, IEEE Trans. Power Electron., vol. 22, no. 2, pp. 693697, Mar. 2007. [3] M. C. Cavalcanti, K. C. de Oliveria, A. M. de Farias, F. A. S. Neves, G. M. S. Azevedo, and F. C. Camboim, Modulation techniques to eliminate leakage currents in transformerless three-phase photovoltaic systems, IEEE Trans. Ind. Electron., vol. 57, no. 4, pp. 13601368, Apr. 2010. [4] T. Kerekes, M. Liserre, R. Teodorescu, C. Klumpner, and M. Sumner, Evaluation of three-phase transformerless photovoltaic inverter topologies, IEEE Trans. Power Electron., vol. 24, no. 9, pp. 22022211, Sep. 2009. [5] W. Yu, J.-S. Lai, H. Qian, and C. Hutchens, High-efciency MOSFET inverter with H6-type conguration for photovoltaic nonisolated ac-module applications, IEEE Trans. Power Electron., vol. 26, no. 4, pp. 12531260, Apr. 2011. [6] S. V. Araujo, P. Zacharias, and R. Mallwitz, Highly efcient single-phase transformerless inverters for grid-connected photovoltaic systems, IEEE Trans. Ind. Electron., vol. 57, no. 9, pp. 31183128, Sep. 2010. [7] R. Gonzalez, E. Gubia, J. Lopez, and L. Marroyo, Transformerless singlephase multilevel-based photovoltaic inverter, IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 26942702, Jul. 2008. [8] J. Li, J. Liu, D. Boroyevich, P. Mattavelli, and Y. Xue, Three-level active neutral-point-clamped zero-current-transition converter for sustainable energy systems, IEEE Trans. Power Electron., vol. 26, no. 12, pp. 36803693, Dec. 2011. [9] V. G. Agelidis, D. M. Baker, W. B. Lawrance, and C. V. Nayar, A multilevel PWM inverter topology for photovoltaic applications, in Proc. IEEE Int. Symp. Ind. Electron., Jul. 1997, vol. 2, pp. 589594. [10] P. G. Barbosa, H. A. C. Braga, Md. C. B. Rodrigues, and E. C. Teixeira, Boost current multilevel inverter and its application on single-phase gridconnected photovoltaic systems, IEEE Trans. Power Electron., vol. 21, no. 4, pp. 11161124, Jul. 2006. [11] S. Busquets-Monge, J. Rocabert, P. Rodriguez, S. Alepuz, and J. Bordonau, Multilevel diode-clamped converter for photovoltaic generators with independent voltage control of each solar array, IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 27132723, Jul. 2008. [12] H. Xiao and S. Xie, Transformerless split-inductor neutral point clamped three-level PV grid-connected inverter, IEEE Trans. Power Electron., vol. 27, no. 4, pp. 17991808, Apr. 2012. [13] F.-S. Kang, S.-J. Park, S. E. Cho, C.-U. Kim, and T. Ise, Multilevel PWM inverters suitable for the use of stand-alone photovoltaic power systems, IEEE Trans. Energy Convers., vol. 20, no. 4, pp. 906915, Dec. 2005. [14] A. A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, Voltagesharing converter to supply single-phase asymmetrical four-level diodeclamped inverter with high power factor loads, IEEE Trans. Power Electron., vol. 25, no. 10, pp. 25072520, Oct. 2010. [15] D. Floricau, G. Gateau, M. Dumitrescu, and R. Teodorescu, A new stacked NPC converter: 3l-topology and control, in Proc. Eur. Conf. Power Electron. Appl., 2007, pp. 110. [16] D. Floricau, G. Gateau, and A. Leredde, New active stacked NPC multilevel converter: Operation and features, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 22722278, Jul. 2010. [17] Y. Wang and X. Cai, Dc link voltage optimized control for efcient residential fuel cell converter, Int. J. Electr. Power Energy Syst., vol. 32, no. 9, pp. 10311036, 2010.

Fig. 23. Efciency versus output power: (a) efciency of the proposed prototype for different open-circuit voltage of the PV generator (V o c ), (b) efciency comparison between the conventional 3L-NPC and the proposed 3L-SNPC topology for V o c = 1000 V.

strategy cannot compensate the dead-time effect around the zero crossing point. Moreover, the uncompensated region will become larger if the inverter is generating reactive power. Fig. 23 shows the efciency plot in all power range and the comparison with the conventional 3L-NPC solar inverter. It shows that the efciency, especially in low power range, is soundly improved. VI. CONCLUSION This paper has investigated the power loss distribution in the conventional 3L-NPC and 3L-SNPC structures for solar inverters. Much attention has been paid on power losses in the low power range. To overcome the drawbacks, the authors proposed

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Yong Wang (M12) received the Ph.D. degree in power electronics from Zhejiang University, Hangzhou, China, in 2005. From 2005 to 2008, he was a Senior Researcher in Samsung Advanced Institute of Technology, Korea, researching on the fuel cell grid-tied inverter. From 2008 to 2010, he was a Power Electronics Hardware Engineer in Danfoss, Denmark. In 2010, he joined Shanghai Jiao Tong University, Shanghai, China, where he is currently an Associate Professor in the Department of Electrical Engineering. His research interest includes the power electronics applications in renewable energy, especially the grid-tied inverter.

Fei Wang received the B.E. degree in electrical engineering from Shanghai Jiao Tong University, Shanghai, China, in June 2012, where she is currently working toward the Masters degree in electrical engineering, majoring in power electronics and power drives. Her current research interests include photovoltaic inverter and wind-power converter.