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VLSI Combinational Circuit Design

Dr. Le Dung
Hanoi University of Science and Technology

A large digital logic circuit can be implemented by

SSI, MSI and LSI off-the-shelf parts VLSI Application-specific integrated circuit (ASIC)

Mul:ple ICs
Dr. Le Dung

Single IC
Hanoi University of Science and Technology

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An example of the off-the-shelf parts design

Dr. Le Dung

Hanoi University of Science and Technology

Designing with off-the-shelf parts

The o-the-shelf parts = Commercial SSI, MSI and LSI modular logic integrated circuits (74xxx, 4xxx ) Quickly assembling a circuit board The number of parts and the cost per gate can become unacceptably large

Dr. Le Dung

Hanoi University of Science and Technology

9/25/13

VLSI ASIC design

Using single VLSI IC + Reduce PCB space and power requirements + Reduce total cost Designing approaches :

+ Full-custom design + Semi-custom design

Using hardware descrip:on language and

CAD tools for designing

Dr. Le Dung

Hanoi University of Science and Technology

Full-custom design (1)

Gate by gate designing with the physical layout of each individual transistor and the interconnec:ons between them. Each transistor and each connec:on is designed individually as a set of rectangles

Dr. Le Dung

Hanoi University of Science and Technology

9/25/13

Full-custom design (2)

+ Both the circuit performance and the silicon area can be op:mized (using ECAD tools) - Extremely labor-intensive to implement - Increasing manufacturing and design :me Time-to-market compe::on - High cost of mask sets

Dr. Le Dung

Hanoi University of Science and Technology

Semi-custom design
Semi-custom device

+ has predesigned parts

Semi-custom design approaches Standard cell based design Gate array based design Programmable devices based design

Dr. Le Dung

Hanoi University of Science and Technology

9/25/13

Standard cell based design (1)

Library of standard cells
+ Each cell is a gate + Same height, variable width, interleaved by rou:ng channels + All inputs at the top, all outputs at the bo]om

A designer selects cells from a design libarary, specifying where they should be placed on the IC and then dicta:ng how they should be interconnected. Faster design of more complex building blocks Silicon foundries design and sell such op:mized libraries for their processing technology

Dr. Le Dung

Hanoi University of Science and Technology

Basic process standard cell based design

Technology mapping

Dr. Le Dung

Hanoi University of Science and Technology

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Hardware Descrip:on Language Synthesis

Translate HDL descriptions into logic gate networks in a particular library

Dr. Le Dung

Hanoi University of Science and Technology

Logic Synthesis Phases

Logic optimization transforms current gate-level network into an equivalent gate-level network more suitable for technology mapping. Technology mapping transforms the gate-level network into a netlist of gates (from library) which minimizes total cost.

Dr. Le Dung

Hanoi University of Science and Technology

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Library of standard cell

CELLS COST DELAY SYMBOL PATTERN
2 3 1 1.4

INVERTER NAND2

NAND3

1.8

NAND4

2.2

AOI21

1.8

CMOS AND-OR-Invert Gate Dr. Le Dung Hanoi University of Science and Technology

An example of standard cell technology mapping (1)

Dr. Le Dung

Hanoi University of Science and Technology

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An example of standard cell technology mapping (2)

Synthesis
Netlist of gates (from library) which minimizes total cost.

Dr. Le Dung

Hanoi University of Science and Technology

Phases of synthesis (1/3)

1. Independent transformaNons (opNmizaNon):

Dr. Le Dung

Hanoi University of Science and Technology

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Phases of synthesis (1/3)

1. Independent transformaNons (opNmizaNon):

Dr. Le Dung

Hanoi University of Science and Technology

Phases of synthesis (1/3)

1. Independent transformaNons (opNmizaNon):

Dr. Le Dung

Hanoi University of Science and Technology

9/25/13

Phases of synthesis (1/3)

1. Independent transformaNons (opNmizaNon):

Dr. Le Dung

Hanoi University of Science and Technology

Phases of synthesis (1/3)

1. Independent transformaNons (opNmizaNon):

Dr. Le Dung

Hanoi University of Science and Technology

10

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Phases of synthesis (1/3)

1. Independent transformaNons (opNmizaNon):

Original netlist d a b c e f g h

Dr. Le Dung

Hanoi University of Science and Technology

Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

Original netlist d a b c e f g h
Dr. Le Dung Hanoi University of Science and Technology

11

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Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

d a b c e f g h
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

d a b c e f g h
Dr. Le Dung Hanoi University of Science and Technology

12

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Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

d a b c e f g h
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

d a b c e f g h
Dr. Le Dung Hanoi University of Science and Technology

13

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Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

14

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Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

15

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Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

16

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Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (2/3)

DecomposiNon using base funcNons:

Decompose to a network NAND2/NOT

Subject Graph
a b c d e f g h
Dr. Le Dung Hanoi University of Science and Technology

17

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What is technology mapping ?

Technology mapping is the problem of opNmising a network for area or delay, using only library cells.

library

Original netlist Mapping

Netlist of gates (from library) which minimizes total cost.

rule

Dr. Le Dung

Hanoi University of Science and Technology

Phases of synthesis (3/3)

Technology mapping:
Greedy algorithm Greedy search

a b c d e f g h

Subject Graph
Dr. Le Dung Hanoi University of Science and Technology

18

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Phases of synthesis (3/3)

Technology mapping:
Greedy search

a b c d e f g h

Subject Graph
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (3/3)

Technology mapping:
- Greedy search

a b c d e f g h

Subject Graph
Dr. Le Dung Hanoi University of Science and Technology

19

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Phases of synthesis (3/3)

Technology mapping:
Using principle of op:mality

15

a b c d e f g h

Subject Graph
Dr. Le Dung Hanoi University of Science and Technology

Phases of synthesis (3/3)

Technology mapping:
Using principle of op:mality

15

a b c d e f g h

Subject Graph
Dr. Le Dung Hanoi University of Science and Technology

20

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Phases of synthesis (3/3)

Technology mapping:
Using principle of op:mality

a b c d e f g h

Subject Graph
Dr. Le Dung Hanoi University of Science and Technology

Gate array based design

+ A gate array or uncommitted logic array (ULA) circuit is prefabricated
with a number of unconnected logic gates (cells). + CMOS transistors with fixed length and width are placed at regular predefined positions and manufactured on a wafer, usually called a master slice ( sea of gates). + Creation of a circuit with a specified function is accomplished by adding a final surface layer or layers of metal interconnects to the chips on the master slice late in the manufacturing process, joining these elements to allow the function of the chip to be customized as desired reducing the designing time Cell I/O buffer reducing the mask costs Customized metal layer for + Disadvantages connecting gate - slow clock speed - wasted chip area Sea of gates
Fixed transistor layer

Dr. Le Dung

Hanoi University of Science and Technology

21

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Gate array based design ow

Design entry Simula:on

Technology mapping

Library of cells

Placement

Rou:ng

Timing simula:on

Fabrica:on (metal 1 mask)

Dr. Le Dung

Tes:ng
Hanoi University of Science and Technology

Programmable Device Based Design

Based on programmable devices:
The interconnection layers are personalized by electronic means for a specific application. This work usually can be done by end-users.

F0 = AB+ AC F1 = B + AC F2 = AB+ BC F3 = AC + B
Dr. Le Dung Hanoi University of Science and Technology

22

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Programmable Elements
+ + + + + + + Fuse Antifuse Switch Volatile Non-volatile One Time Programmable Reprogrammable (Memory-based)

Dr. Le Dung

Hanoi University of Science and Technology

Programmable Devices
Simple Programmable Logic Device: + Programmable read only memory (PROM) + Field Programmable logic array (FPLA or PLA) + Programmable array logic (PAL) + Generic array logic (GAL) Complex programmable logic device (CPLD) Field programmable gate array (FPGA) Field programmable interconnect (FPIC)
Dr. Le Dung Hanoi University of Science and Technology

23

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Basic SPLD organiza:on

Feedback terms

AND array

OR array

Output options

Inputs

Product terms

Sum terms

Outputs

Dr. Le Dung

Hanoi University of Science and Technology

Fuse-based programmable AND OR Array

Dr. Le Dung

Hanoi University of Science and Technology

24

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Output Polarity Op:ons

Dr. Le Dung

Hanoi University of Science and Technology

Bidirec:onal Pins and Feedback line

Dr. Le Dung

Hanoi University of Science and Technology

25

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PLD Design Process

Dr. Le Dung

Hanoi University of Science and Technology

Combina:onal Circuit is implemented on SPLD

Dr. Le Dung

Hanoi University of Science and Technology

26

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PROM = Read-Only-Memory

Dr. Le Dung

Hanoi University of Science and Technology

PROM = PLD with xed AND array

Dr. Le Dung

Hanoi University of Science and Technology

27

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Full-adder on PROM

Dr. Le Dung

Hanoi University of Science and Technology

PAL

Dr. Le Dung

Hanoi University of Science and Technology

28

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Combina:onal Circuit is implemented PAL

Dr. Le Dung

Hanoi University of Science and Technology

FPLA

Programmable AND array

Programmable OR array

Dr. Le Dung

Hanoi University of Science and Technology

29

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Combina:onal Circuit is implemented on FPLA (1)

Minimize each func:on separately 8 product terms F1 = bd + bc + ab F2 = c + abd F3 = bc + abc+ abd

Dr. Le Dung

Mul:ple-Output Op:miza:on 5 product terms F1 = abd + abd + abc+ bc F2 = abd + bc + bc F3 = abd + abc+ bc
Hanoi University of Science and Technology

Combina:onal Circuit is implemented on FPLA (2)

F1 = abd + abd + abc+ bc F2 = abd + bc + bc F3 = abd + abc+ bc

Dr. Le Dung

Hanoi University of Science and Technology

30

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Exercise
PLA

Implement the two functions with PLA

Dr. Le Dung

Hanoi University of Science and Technology

Generic Array Logic architecture

Output logic macrocell (OLMC)

Dr. Le Dung

Hanoi University of Science and Technology

31

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CPLD architecture
O AND-OR Plane I/O I/O AND-OR Plane O

Switch matrix

AND-OR Plane O I/O

AND-OR Plane I/O O

Dr. Le Dung

Hanoi University of Science and Technology

FPGA architecture (1)

Dr. Le Dung

Hanoi University of Science and Technology

32

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FPGA architecture (2)

Dr. Le Dung

Hanoi University of Science and Technology

FPGA architecture (3)

Switch Matrix and interconnection

Long lines : - Across whole chip - High fan-out, low skew - Suitable for global signals (CLK) and buses - 2 tri-states per CLB for busses
Dr. Le Dung Hanoi University of Science and Technology

33

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FPGA architecture (4)

Configurable Logic Block (CLB) 5 logic inputs Data input (DI) Clock (K) Clock enable (EC) Direct reset (RD) 2 outputs (X,Y)

Dr. Le Dung

Hanoi University of Science and Technology

FPGA architecture (5)

I/O Block (IOB)

Dr. Le Dung

Hanoi University of Science and Technology

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FPGA development toolkit

Dr. Le Dung

Hanoi University of Science and Technology

35