ALDEC 16450 IP Core Data Sheet

April 11, 2006 (version 1.0)

Overview
The 16450 core is the HDL synthesizable model of industry standard 16450 Universal Asynchronous Receiver/Transmitter.

Features

Functionally based on the 16450 device Transmission of programmable word length (5, 6, 7, 8) and stop bits (1,1.5, or 2) Even, odd, force, or no parity generation and detection Possibility to remove selected parts of the core, e.g. receiver or transmitter (one of them is required), baud generator, modem controller, interrupt controller, scratch patch register

Pinout
Table 1: Core Signal Pinout Name CLK RD WR CE MR CS0 Direction Input Input Input Input Input Input Polarity Low/High Low/High Low/High Low/High Low/High Low/High Description Transmitter and receiver clock input Read signal Write signal Clock Enable signal for the CLK input Reset. The active state on this pin resets the internal registers and all outputs. Chip select 0. The active state on all chip select inputs causes UART to respond to RD and WR signals. Chip select 1. The active state on all chip select inputs causes UART to respond to RD and WR signals. Chip select 2. The active state on all chip select inputs causes UART to respond to RD and WR signals. Chip select out. The active state on this output indicates that the UART has been enabled by the chip select inputs. Clear to send. Logic 0 on the CTS pin indicates that the modem or data set is ready to accept data from the UART. Status can be tested by reading MSR bit 4. This pin has no effect on the UARTs transmit or receive operations. Carrier Detect. Logic 0 on this pin indicates that a carrier has been detected by the modem. This pin has no effect on the UARTs transmit or receive operation.

CS1

Input

Low/High

CS2

Input

Low/High

CSOUT

Output

Low/High

CTS

Input

Low

DCD

Input

Low

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Aldec 16450 Core Data Sheet Data Set Ready. A logic 0 on this pin indicates that the modem or data set is powered-on and ready for data exchange with the UART. This pin has no effect on the UARTs transmit or receive operation. Ring Indicator. Logic 0 on this pin indicates that the modem has received a ring signal from the telephone line. Logic 1 transition on this input pin will generate interrupt. This pin has no effect on the UARTs transmit or receive operation. Address bus. Selects internal registers address. Data in bus. Drive Disable. This pin goes to the active state when external CPU is reading data from the UART. Interrupt Request. Interrupt requests are indicated by the active state of this output pin. Serial input. This pin provides the serial input channel to the UART. During the local loop-back mode the SIN pin is disconnected and SOUT data is internally connected to the UART SIN input. Serial output. This pin provides the serial output channel from UART. During the local loop-back mode, the SOUT pin is disconnected, and SOUT data is internally connected to the UART SIN input. Data Terminal Ready. Logic 0 on this pin indicates that the UART is powered-on and ready. This pin can be controlled via the MCR register. Writing a logic 1 to MCR bit -0 will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit -0. This pin has no effect on the UARTs transmit or receive operation. Output 1. The function of this pin is user defined. Writing to MCR bit 2 will set this pin to 0. This pin has no effect on the UARTs transmit or receive operation. Output 2. The function of this pin is user defined. Writing to MCR bit 3 will set this pin to 0. This pin has no effect on the UARTs transmit or receive operation. Ready To Send. Logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the MCR bit 1 will set this pin to a logic 0 indicating data is available. This pin has no effect on the UARTs transmit or receive operation. Data out bus.

DSR

Input

Low

RI

Input

Low

A [2:0] DATA_IN [7:0] DDIS INT

Input Input

Low -

Output Output

Low/High Low/High

SIN

Input

SOUT

Output

DTR

Output

Low

OUT1

Output

Low

OUT2

Output

Low

RTS

Output

Low

DATA_OUT [7:0]

Output

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Aldec 16450 Core Data Sheet Notes: 1) Bi directional DATA bus is defined in the core interface as two separated ports DATA_IN and DATA_OUT. 2) The additional CE (Clock Enable) port has been added for the CLK input. This port allows to divide the frequency of the clock input (CLK). 3) The external clock port of the receiver and external clock output from the baud generator has been removed. The receiver uses the same clock signal as the transmitter. 4) The latches in the address port A and the ADS port used to drive the latches have been removed. 5) The doubled write (WR) and read (RD) input has been removed.

Block Diagram

CS0 CS1 CS2 MD RD

Receiver

SIN CLK CE

Registers

WR DDIS CSOUT A [2:0] D [7:0]

Transmitter

SOUT CLK CE

CE OUT Baud Generator CLK

OUT1 OUT2 RTS Modem DTR Controller CTS DSR DCD RI

Interrupt Controller
INTR

Figure 1: Core Structure

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2006 Aldec, Inc. All rights reserved

Aldec 16450 Core Data Sheet

Deliverables
Available at No Cost: Verilog and/or VHDL Simulation Model (Encrypted for Aldec simulator only) Data Sheet Application Notes Available Upon ordering: VHDL/Verilog source code Technology-dependent EDIF and VHDL/Verilog netlists Verification Test Bench source code RTL Source compilation and simulation scripts Synthesis scripts User-Guide

Ordering Information
Aldec, Inc. 2260 Corporate Circle Henderson, NV 89074 Tel: 702-990-4400 Fax: 702-990-4414 Email: ipcores@aldec.com http://www.aldec.com

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2006 Aldec, Inc. All rights reserved