HS-2420RH

Data Sheet February 2003 FN3554.3

Radiation Hardened Fast Sample and Hold

The HS-2420RH is a radiation hardened monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultra-low leakage analog switch and MOSFET input unity gain amplifier. With an external hold capacitor connected to the switch output, a versatile, high performance sample-and-hold or track-andhold circuit is formed. When the switch is closed, the device behaves as an operation amplifier, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened the output will remain at its last level. Performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. Accuracy to better than 0.01% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than 1 frequently eliminates the need for external scaling amplifiers. The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95669. A hot-link is provided on our website for downloading.

Features
Electrically Screened to SMD # 5962-95669 QML Qualified per MIL-PRF-38535 Requirements Maximum Acquisition Time - 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . . . . . . 4s - 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . . . . . . 6s Maximum Drift Current . . . . . . . . . . . . . . . . . . . . . . . 10nA (Maximum Over Temperature) TTL Compatible Control Input Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . 80dB Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) No Latch-Up

Applications
Data Acquisition Systems D to A Deglitcher Auto Zero Systems Peak Detector Gated Op Amp

Ordering Information
ORDERING NUMBER 5962R9566901VCC INTERNAL MKT. NUMBER HS1B-2420RH-Q TEMP. RANGE (oC) -55 to 125

Functional Diagram
OFFSET ADJUST 3 1 + 2 4 V+ 5

Pinout
14 LEAD METAL-SEALED SIDE-BRAZED CERAMIC DIP MIL-STD-1835, CDIP2-T14 TOP VIEW
14 SAMPLE/HOLD CONTROL 13 GND 12 NC 11 HOLD CAPACITOR 10 NC 9 V+ 8 NC SAMPLE/ HOLD CONTROL

- INPUT
+ INPUT

7 OUTPUT

IN- 1 IN+ 2 OFFSET ADJUST 3 OFFSET ADJUST 4 V- 5 NC 6 OUTPUT 7

14

HS-2420RH

13 5 11 GND VHOLD CAPACITOR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

HS-2420RH Test Circuits

VDC ALL RESISTORS = 1% ALL CAPACITORS = 10% 100k 10k +VCC -VCC S2 2 S/H

S7

1 S4 GND S5 1 OPEN 3 2 100k + NULL AMP X1 X-1 BUFFER

DUT

50 2 1 S1 2 S6

1 2

S7

1 50

CH = 1000pF

S3 3

1 50pF

2k

+VCC 1M VAC 50 + ILOAD

AOUT 4 3 EOUT S8 1 2

FIGURE 1. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S1 - S8 DETERMINE CONFIGURATION)

+5V SINEWAVE INPUT IN2 IN1 IN3 IN4 IN5 IN6 IN7 IN8 A2 A1 EN +15V -15V +15V -15V

OUT VIN

+ DUT 2k CH = 1000pF

VOUT 50pF 50

DUT + 2k S/H CH = 1000pF

VOUT 50pF

A0

SAMPLE/HOLD CONTROL INPUT

NOTE: Compute Hold Mode Feedthrough Attenuation from the Formula: V OUT HOLD FeedthroughAttenuation = 20 log ------------------------------- V IN HOLD Where VOUT HOLD = Peak-Peak Value of Output Sinewave during the Hold Mode. FIGURE 2. HOLD MODE FEEDTHROUGH ATTENUATION

NOTE: GBWP is the Frequency of VINPUT at which: V OUT 20 log -------------------- = 3dB V INPUT

FIGURE 3. GAIN BANDWIDTH PRODUCT

HS-2420RH Test Circuits

(Continued)

SEND SAMPLE COMMAND

SET t2 TO 7s INITIALLY

COURSE tACQ MEASUREMENT LOOP

FINE tACQ MEASUREMENT LOOP

DIGITIZE V1 AT t1 (10s)

INCREMENT t2 BY 50ns (50ns LONGER DELAY)

DIGITIZE V2 AT t2

DECREMENT t2 BY 50ns

DIGITIZE V1 AT t1 (10s) CALCULATE V1 - V2 IS V 0.01%? YES DIGITIZE V2 AT t2

NO DECREMENT t2 BY 50ns RECORD tACQ

YES CALCULATE V1 - V2 IS V 0.01%?

NO

NOTE: See Test Diagram, Timing Diagram FIGURE 4. ACQUISITION TIME (tACQ TO 0.01% IS SHOWN, tACQ TO 0.1% IS DONE IN THE SAME MANNER)

t1

HS-2420RH

V1 V1 DIGITIZER

+ +10V 0V OR 0V -10V S/H CONTROL

+ 50pF 2k 1000pF t1 V2 V2 DIGITIZER

COMPUTER CONTROLLER

10s
DELAY t2 VARIABLE DELAY

t2 DELAY CONTROL

FIGURE 5.

HS-2420RH Timing Waveforms

10V

VIN (POS tACQ CASE) S/H CONTROL

0V 2V 0V 0.01% OR 0.1% ENVELOPE 10V

DUT OUTPUT (POS tACQ CASE) t1

0V (t1 DIGITIZER COMMAND)

t1 10s

t2

(t2 DIGITIZER COMMAND)

t2

FIGURE 6. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE tACQ CASE)

+V

0V

VPEAK 90%

VFINAL 10%

INPUT 10% 0V +OS, tR -OS, tF -V tR tF 90% VFINAL VPEAK

FIGURE 7A.

FIGURE 7B.

FIGURE 7. OVERSHOOT, RISE AND FALL TIME WAVEFORMS

+V

+V

+V 75%

+V 25%

INPUT 25% -V +SL -SL -V -V t t 75% -V

FIGURE 8A. FIGURE 8. SLEW RATE WAVEFORMS

FIGURE 8B.

HS-2420RH Typical Performance Curves

1000 DRIFT DURING HOLD AT 25oC mV/s

VSUPPLY = 15VDC , TA = 25oC, CH = 1000pF, Unless Otherwise Specified

1000 LOWER 3dB FREQUENCY = 10Hz OUTPUT NOISE HOLD MODE HOLD STEP OFFSET ERROR (mV) 100 mVRMS EQUIV. INPUT NOISE SAMPLE MODE - 100K SOURCE RESISTANCE 10 EQUIV. INPUT NOISE SAMPLE MODE - 0K SOURCE RESISTANCE 1.0mF 1 10 100 1K 10K 100K 1M

100 UNITY GAIN PHASE MARGIN (DEG) 10

1.0

0.1

UNITY GAIN BANDWIDTH (MHz) MIN SAMPLE TIME SLEW RATE/ FOR 0.1% ACCURACY CHARGE RATE 10V SWINGS (ms) V/(ms) 100pF 1000pF 0.01mF 0.1mF

0.01 10pF

CH VALUE

BANDWIDTH

FIGURE 9. TYPICAL SAMPLE AND HOLD PERFORMANCE vs HOLDING CAPACITOR

1000 OPEN LOOP VOLTAGE GAIN (dB)

FIGURE 10. BROADBAND NOISE CHARACTERISTICS

100 80 60 40 20 0 -20 10 100 1K 10K 100K 1M 10M 100M CH = 1.0F CH = 0.1F CH = 0.01F CH = 100pF CH = 1000pF

100 ID (pA) 10 1 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 125

FREQUENCY (Hz)

FIGURE 11. DRIFT CURRENT vs TEMPERATURE

FIGURE 12. OPEN LOOP FREQUENCY RESPONSE

-30 -40 ATTENUATION (dB) -50 -60 -70 -80 -90

OPEN LOOP PHASE ANGLE (DEGREES)

0 20 40 60 80 100 120 140 160 180 200 220 240 10 100

CH = 0.01F CH =1000pF

CH = 1.0F CH = 0.1F

CH 100pF

100

1K

10K

100K

1M

10M

1K

10K

100K

1M

10M

100M

10V SINUSOIDAL INPUT FREQUENCY (Hz)

FREQUENCY (Hz)

FIGURE 13. HOLD MODE FEEDTHROUGH ATTENUATION CH = 1000pF

FIGURE 14. OPEN LOOP PHASE RESPONSE

HS-2420RH Burn-In Circuit

HS-2420RH CERDIP
-IN +IN OFF ADJ OFF ADJ -V NC OUT S/H CTL 14 GND 13 NC 12 HOLD CAP 11 NC 10 +V NC +15V 9 8 D1 C1 6 7 9 8 V1 V2 GND

Irradiation Circuit

1 2 R1 3 4 -15V 5 C2 D2 6 7

1 R 2 3 4 5

14 13 12 GND 11 10

NOTES: R1 = 100k 5% (per socket) C1 = C2 = 0.1F (one per row) or 0.01F (one per socket) D1 = D2 = 1N4002 or equivalent (per board)

NOTES: V1 = +15V V2 = -15V R = 100k

HOLD STEP VOLTAGE (V) +10

S/H CONTROL V+

+5 -10 -5 +5 +10

CH

-5 -10

DC INPUT VOLTAGE (V) CH = 0.1F CH = 10,000pF

+ HS-2420RH

-15 -20 -25 -30 -35

CH = 1000pF

-IN CH = 100pF

+IN

V-

OUT

100k OFFSET TRIM (25mV RANGE)

FIGURE 15. HOLD STEP vs INPUT VOLTAGE

FIGURE 16. BASIC SAMPLE-AND-HOLD (TOP VIEW)

0.002RF RF

INPUT +IN HS-2420RH OUT OUTPUT

INPUT RI -IN HS-2420RH OUT +IN S/H CONTROL RI OUTPUT

-IN RF

S/H CONTROL

S/H CONTROL INPUT

0.002RI S/H CONTROL INPUT -RF GAIN ~ RI GAIN ~ I +

-RF RI

FIGURE 17. INVERTING CONFIGURATION

FIGURE 18. NONINVERTING CONFIGURATION

HS-2420RH Offset and Gain Adjustment

Offset Adjustment
The offset voltage of the HS-2420RH may be adjusted using a 100k trim pot, as shown in Figure 15. The recommended adjustment procedure is: 1. Apply 0V to the sample-and-hold input, and a square wave to the S/H control. 2. Adjust the trim pot for 0V output in the hold mode.

Gain Adjustment
The linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. The two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input voltage that should produce a +10V output. 3. Adjust the trim pot for +10V output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. 5. Measure the output hold voltage (V-10 NOMINAL). Adjust the trim pot for an output hold voltage of:
( V-10 NOMINAL ) + ( 10V ) ----------------------------------------------------------------------2

HS-2420RH Die Characteristics

DIE DIMENSIONS: 97 mils x 61 mils x 19 mils METALLIZATION: Type: Al Thickness: 16k 2k GLASSIVATION: Type: Silox Thickness: 14k 2k WORST CASE CURRENT DENSITY: 2.0 x 105A/cm2 TRANSISTOR COUNT: 78 PROCESS: Bipolar-Di

Metallization Mask Layout

HS-2420RH

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