EE-430: Embedded Systems Design

Combinational Logic Design

Awais M. Kamboh

Slide 1

Single-purpose processors
A custom single-purpose processor is
Fast Low power Small size

But,
Large Design Time, time-to-market High NRE Cost, No Flexibility

Awais M. Kamboh

Slide 2

CMOS transistor on silicon

Transistor
The basic electrical component in digital systems Acts as an on/off switch Voltage at gate controls whether current flows from source to drain Dont confuse this gate with a logic gate gate
1
IC package IC source gate oxide channel drain Silicon substrate

source Conducts if gate=1 drain

Awais M. Kamboh

Slide 3

CMOS transistor implementations

Complementary Metal Oxide Semiconductor We refer to logic levels
Typically 0 is 0V, 1 is 5V
drain gate Conducts if gate=1 source

nMOS

Two basic CMOS types

nMOS conducts if gate=1 pMOS conducts if gate=0 Hence complementary
gate

source
Conducts if gate=0 drain

pMOS

Awais M. Kamboh

Slide 4

CMOS transistor implementations

Basic gates

Inverter
1

F = x'

Awais M. Kamboh

Slide 5

CMOS transistor implementations

Basic gates NAND NOR
1 x y F = (xy)' 1

x y

x y
F = (x+y)' x y 0 NOR gate

0 NAND gate

Awais M. Kamboh

Slide 6

CMOS transistor implementations

Activity
CMOS Implementation of AND gate

Awais M. Kamboh

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CMOS transistor implementations

Solution to Activity
CMOS Implementation of AND gate

Awais M. Kamboh

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Basic logic gates

Awais M. Kamboh

Slide 9

Combinational Logic Design

A) Problem description y is 1 if a is 1, or b and c are 1. z is 1 if b or c is 1, but not both, or if all are 1.
Inputs B) Truth table Outputs

a
0 0 0 0 1

b
0 0 1 1 0 0 1 1

c
0 1 0 1 0 1 0 1

y
0 0 0 1 1 1 1 1

z
0 1 1 0 0 1 1 1

C) Output equations y = a'bc + ab'c' + ab'c + abc' + abc

z = a'b'c + a'bc' + ab'c + abc' + abc

1 1 1

Awais M. Kamboh

Slide 10

Combinational Logic Design

D) Minimized output equations

y a 0 1 bc 00 0 1 01 0 1 11 1 1 10 0 1 a b c

E) Logic Gates

y = a + bc z a 0 1 bc 00 0 0 01 1 1 11 0 1 10 1 1 z

z = ab + bc + bc

Awais M. Kamboh

Slide 11

Combinational Components
I(m-1) I1 I0 n n-bit, m x 1 Multiplexor S(log m) n O S0 I(log n -1) I0 log n x n Decoder O(n-1) O1 O0 A n n-bit Adder n carry sum less equal greater B A B A n n B

n-bit Comparator

n bit, m function S0 ALU S(log m) n O

O= I0 if S=0..00 I1 if S=0..01 I(m-1) if S=1..11

O0 =1 if I=0..00 O1 =1 if I=0..01 O(n-1) =1 if I=1..11

sum = A+B (first n bits) carry = (n+1)th bit of A+B

less = 1 if A<B equal =1 if A=B greater=1 if A>B

O = A op B op determined by S.

MUX

Decoder
With enable input e all Os are 0 if e=0

Adder
With carry-in input Ci sum = A + B + Ci

Comparator

ALU
May have status outputs carry, zero, etc. Commonly, Add, Sub, Mul, AND, XOR etc

Awais M. Kamboh

Slide 12

EE-430: Embedded Systems Design

Sequential Logic Design

Awais M. Kamboh

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Sequential Components

Awais M. Kamboh

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Sequential logic design

Example
Design a 3-bit counter that counts the following sequence: 1, 2, 4, 5, 7, 1, 2, etc. This counter has an output odd whose value is 1 when current count value is odd. Start from a state diagram, draw the state table, minimize the logic, and draw the final circuit.

Awais M. Kamboh

Slide 15

Sequential logic design

State Diagram

Awais M. Kamboh

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Sequential logic design

State Table

Awais M. Kamboh

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Sequential logic design

Given this implementation model
Sequential logic design quickly reduces to combinational logic design

Awais M. Kamboh

Slide 18

Sequential logic design

Logic Circuit

Awais M. Kamboh

Slide 19

Sequential logic design

Block Diagram

Awais M. Kamboh

Slide 20