CHAPTER-1

1. Explain the functions of microprocess 8 2. Explain the block diagram of microprocessor (general block diagram of mp not internal or block diagram 8085 mp) 3. Define microprocessor 4. Define bus and Explain the bus organization in 8085 mp 5. Explain the functions of the different pins or pin configuration of 8085 6. Explain the internal architecture of 8085 or block diagram of 8085 mp 7. Expain the programming model of 8085 mp 8. With a neat diagram explain demultiplexing of Address/Data bus of 8085 9. Write a note on stack pointer(SP) and program counter(PC) 10. What is the function of ALE and how does it function? 11. Write a note on general purpose registers of 8085 mp. 12. How does 8085 based single board microcomputer works?

Ans.

We have studied the architecture of a 8085 microprocessor. 8085 microprocessor when connected with the input device, output device and memory forms a microcomputer system. The input device like keyboard is used to enter the data and instructions. The memory is used to store the data and the output device like seven segment display or CRT is used to display the results. Fig. shows the block diagram of a 8085 based micro computer system. It consists of two types of memory, (EPROM and R/W memory) an input device, an output device and address bus, data bus and a few control signals connected to the peripherals (memory and I/O devices) and the microprocessor.

The address lines A8-A15 of the microprocessor are used to carry the addresses of the memory, input device and output devices.

These lines are connected to the EPROM memory, R/W memory, input device and output device. The data lines of 8085 microprocessor are used to carry the data. These are bidirectional lines. The data can flow- from the microprocessor to the peripherals (memory and input/output devices) and also from peripherals to the microprocessor. These bidirectional data lines are also connected to the EPROM memory, R/W memory, input and, output device. The four control signals generated by the microprocessor (Memory Read), (Memory Write), (I/O Read) and (I/O write) are also connected to different peripherals. First control signal, Memory Read is connected to the EPROM memory and R/W memory to read the data from these memories. The second control signal, memory write is connected to the R/W memory so that the data may be written in the R/W memory. The third control signal input/output read signal is connected to the input device. When this signal is active, the 8085 microprocessor can read data from the input device. The fourth control signal input/output write is connected to the output device and when this signal is active, the microprocessor can send data to the output device. The 8085 microprocessor communicates with only one peripheral (memory or I/O device) at a time by enabling the peripheral through its control signal. To read the data from the R/W memory, the 8085 microprocessor sends a low signal. When is low the memory section is enabled, the microprocessor places the address of memory on the address bus, data from the memory (whose address is placed) is read by the microprocessor through the data bus. To send the data to the output device, the microprocessor places the address of the output device on the address bus, data on the data bus and enables the output device by generating a control signal low. The data from the microprocessor is transferred to the output device. Similarly to read data, from the input device, the 8085 microprocessor generates a low control signal so that input device is enabled. Then the microprocessor place the address of the input device on the address bus and the data from the input device is placed on the data bus and it is read by the microprocessor through its data bus. Explain the flag register of 8085 mp With a diagram explain the generation of control signals Explian the block diagram of a computer showing all the essential components Explain briefly machine language, assembly language and high level language

13. 14. 15. 16.

CHAPTER-2

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.

What is an instruction? In how many categories the instructions of 8085 be classified and explain ? What are the different types of data transfer operations possible? What an instruction essentially consists of and explain? Classify the instruction according to word size and explain What is meant by addressing mode and Explain the different addressing modes of 8085 Explain all the instructions with example(refer gonkar Appendix F) Write an alp program to add two 8-bit nos. Write an alp program to multiply two 8-bit nos. Write an alp program to subract two 8-bit nos. Write an alp program to check whether a one byte no is palindrome or not Write an alp program to add two 8-bit nos. Write an alp program to find largest and smallest of two nos, to find twos complement, sorting, to add N one byte nos, to add two 16 bit nos , to perform division, BCD addition and subtraction . 14. All the programs which has been done in class 15. All code conversion programs with explanation

CHAPTER-3
1. Define timing diagram, instruction cycle, machine cycle,T-state. 2. Explain the bus timings in fetching an instruction from the memory(opcode fetch machine cycle using timing diagram) 3. Explain memory read machine cycle using timing diagram 4. Explain memory write machine cycle using timing diagram 5. Explain I/O read machine cycle using timing diagram 6. Explain I/O write machine cycle using timing diagram 7. Explain Interrupt acknowledge machine cycle using timing diagram 8. Explain the execution of the instruction ADI,data with the help of timing diagram. 9. Illustrate the 8085 bus contents and control signals when an OUT instruction is executed. 10. Write the timing diagram for execution of IN instruction. 11. Read the timing diagram of the instructions which has been done in class

CHAPTER-4

1. 2. 3. 4. 5.

Write a note on stack and subroutines What is a stack? How stack is initialized Explain CALL and RET instruction. Explain PUSH and pop instruction What the SP register does in a program

CHAPTER-5
INTERRUPTS

1. Mention the interrupt pins of 8085. Ans. There are five (5) interrupt pins of 8085from pin 6 to pin 10. They represent TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR interrupts respectively. These five interrupts are hardware interrupts. 2. Explain maskable and non-maskable interrupts. Ans. An interrupt which can be disabled by software means, is called a maskable interrupt. Thus an interrupt which cannot be masked is an unmaskable interrupt. 3. Which is the non-maskable interrupt for 8085? Ans. TRAP interrupt is the non-maskable interrupt for 8085. It means that if an interrupt comes via TRAP, 8085 will have to recognise the interrupt. 4. Do the interrupts of 8085 have priority? Ans. Yes, the interrupts of 8085 have their priorities fixedTRAP interrupt has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and lastly INTR. 5. What is meant by priority of interrupts? Ans. It means that if 8085 is interrupted by more than one interrupt at the same time, the one which is having highest priority will be serviced first, followed by the one(s) which is (are) having just next priority and so on. For example, if 8085 is interrupted by RST 7.5, INTR and RST 5.5 at the same time, then the sequence in which the interrupts are going to be serviced are as follows: RST 7.5, RST 5.5 and INTR respectively. 6. Mention the types of interrupts that 8085 supports Ans. 8085 supports two types of interrupts hardware and software interrupts. 7. What are the software interrupts of 8085? Mention the instructions, their hex codes and the corresponding vector addresses. Ans. 8085 has eight (8) software interrupts from RST 0 to RST 7. The instructions, hex codes and the vector locations are tabulated in Table 4.1:

8. How the vector address for a software interrupt is determined? Ans. The vector address for a software interrupt is calculated as follows: Vector address = interrupt number 8 For example, the vector address for RST 5 is calculated as 5 8 = 40)10 = 28)H Vector address for RST 5 is 0028H. 9. In what way INTR is different from the other four hardware interrupts? Ans. There are two differences, which are discussed below: 1. While INTR is not a vectored interrupt, the other four, viz., TRAP, RST 7.5, RST 6.5 and RST 5.5 are all vectored interrupts. Thus whenever an interrupt comes via any one of these four interrupts, the internal control circuit of 8085 produces a CALL to a predetermined vector location. At these vector locations the subroutines are written. On the other hand, INTR receives the address of the subroutine from the external device itself. 2. Whenever an interrupt occurs via TRAP, RST 7.5, RST 6.5 or RST 5.5, the corresponding returns address (existing in program counter) is auto-saved in STACK, but this is not so in case of INTR interrupt. 10. Indicate the nature of signals that will trigger TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. Ans. TRAP interrupt is both positive edge and level triggered, RST 7.5 is positive edge triggered while RST 6.5, RST 5.5 and INTR are all level triggered. 11. Why the TRAP input is edge and level sensitive? Ans. TRAP input is edge and level sensitive to avoid false triggering caused by noise and transients. 12. Discuss the INTR interrupt of 8085. Ans. The following are the characteristics of INTR interrupt of 8085: It is a maskable interrupt It has lowest priority It is a non-vectored interrupt. Sequentially, the following occurs when INTR signal goes high: 1. 8085 checks the status of INTR signal during execution of each instruction. 2. If INTR signal remains high till the completion of an instruction, then 8085 sends out an active low interrupt acknowledge (INTA) signal. 3. When INTA signal goes low, external logic places an instruction OPCODE on the data bus. 4. On receiving the instruction, 8085 saves the address of next instruction (which would have otherwise been executed) in the STACK and starts executing the ISS (interrupt service subroutine).

13. What is to be done if a particular part of a program is not to be interrupted by RST 7.5, RST 6.5, RST 5.5 and INTR? Ans. Two software instructionsEI and DI are used at the beginning and end of the particular portion of the program respectively. The scheme is shown schematically as follows:

14. Explain the software instructions EI and DI. Ans. The EI instruction sets the interrupt enable flip-flop, thereby enabling RST 7.5, RST 6.5, RST 5.5 and INTR interrupts. The DI instruction resets the interrupt enable flip-flop, thereby disabling RST 7.5, RST 6.5, RST 5.5 and INTR interrupts. 15. When returning back to the main program from Interrupt Service Subroutine (ISS), the software instruction EI is inserted at the end of the ISS. Why? Ans. When an interrupt (either via RST 7.5, RST 6.5, RST 5.5, INTR) is acknowledged by the microprocessor, any interrupt acknowledge signal resets the interrupt enable F/F. It thus disables RST 7.5, RST 6.5, RST 5.5 and INTR interrupts. Thus any future interrupt coming via RST 7.5, RST 6.5, RST 5.5 or INTR will not be acknowledged unless the software instruction EI is inserted which thereby sets the interrupt enable F/F. 16. Mention the ways in which the three interrupts RST 7.5, RST 6.5 and RST 5.5 are disabled? Ans. The three interrupts can be disabled in the following manner: Software instruction DI RESET IN signal Any interrupt acknowledge signal. 17. Draw the SIM instruction format and discuss. Ans. The SIM instruction format is shown below:

D7 and D6 bits are utilised for serial outputting of data from accumulator. D5 bit is a dont care bit, while bits D4D0 are used for interrupt control. D4 bit can clear the D F/F associated with RST 7.5. D3 bit is mask set enable (MSE) bit, while bits D2D0 are the masking bits corresponding to RST 7.5, RST 6.5 and RST 5.5 respectively. None of the flags are affected by SIM instruction. By employing SIM instruction, the three interrupts RST 7.5, RST 6.5 and RST 5.5 can be masked or unmasked. For masking any one of these three interrupts, MSE (i.e., bit D3) bit must be 1. For example let RST 7.5 is to be masked (disabled), while RST 6.5 and RST 5.5 are to be unmasked (enabled), then the content of the bits of the SIM instruction will be like 0000 1100 = 0CH For this to be effective the following two instructions are written, MVI A, 0CH SIM Execution of SIM instruction allows copying of the contents of the accumulator into the interrupt masks. 18. Show the RIM instruction format and discuss the same. Ans. RIM stands for Read interrupt mask and its format is as follows:

When RIM instruction is executed in software, the status of SID, pending interrupts and interrupt masks are loaded into the accumulator. Thus their status can be monitored. It may so happen that when one interrupt is being serviced, other interrupt(s) may occur. The status of these pending interrupts can be monitored by the RIM instruction. None of the flags are affected by RIM instruction.

19. Write a program which will call the interrupt service subroutine (at 3C00H) corresponding to RST 7.5 if it is pending. Let the ACC content is 20 H on executing the RIM instruction. Ans. The program for the above will be as hereunder:

20. Write a program which will call the subroutine (say named SR) if RST 6.5 is masked. Let content of ACC is 20 H on executing the RIM instruction. Ans. RST 6.5 is masked if bit M6.5 (D1 bit of RIM) is a 1 and also D3 bit (i.e., IE) is 1 The program for the above will be as hereunder:

21. For what purpose TRAP interrupt is normally used? Ans. TRAP interrupt is a non-maskable one i.e., if an interrupt comes via the TRAP input, the system will have to acknowledge that. That is why it is used for vital purposes which require immediate attention like power failure. If the microprocessor based system loses power, the filter capacitors hold the supply voltage for several mili seconds. During this time, data in the RAM can be written in a disk or E2PROM for future usage. 22. Draw the interrupt circuit diagram for 8085 and explain. Ans. Figure 4.6 is the interrupt circuit diagram of 8085. It shows the five hardware interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR along with the software interrupts RST n: n = 0 to 7. Trap is both edge and level sensitive interrupt. A short pulse should be applied at the trap input, but the pulse width must be greater than a normal noise pulse width and also long enough for the P to complete its current instruction. The trap input must come down to low level for it to be recognised for the second time by the system. It is having highest priority. Next highest priority interrupt is RST 7.5 which responds to the positive edge (low to high transition) of a pulse. Like trap, it also has a D F/F whose output becomes 1 on accepting the RST 7.5 input, but final call to vector location 3C00H is reached only if RST 7.5 remains unmasked and the program has an EI instruction inserted already. These are evident from the circuit. If R 7.5 (bit D4 of SIM instruction) is 1, then RST 7.5 instruction will be overlooked i.e., it can override any RST 7.5 interrupt. Like RST 7.5, final call locations 3400H and 2C00H corresponding to interrupts at RST 6.5 and RST 5.5 are reached only if the two interrupts remain unmasked and the software instruction EI is inserted.

The three interrupts RST 7.5, RST 6.5 and RST 5.5 are disabled once the system accepts an interrupt input via any one of these pinsthis is because of the generation of any interrupt acknowledge signal which disables them. Any of the software RST instructions (RST n : n = 0 to 7) can be utilised by using INTR instruction and hardware logic. RST instructions are utilised in breakpoint service routine to check register(s) or memory contents at any point in the program.

23. The process of interrupt is asynchronous in nature. Why?

Ans. Interrupts may come and be acknowledged (provided masking of any interrupt is not done) by the microprocessor without any reference to the system clock. That is why interrupts are asynchronous in nature. 24. In how many categories can interrupt requests be classified? Ans. The interrupt requests can be classified into two categoriesmaskable interrupt and non-maskable interrupt. A maskable interrupt can either be ignored or delayed as per the needs of the system while a nonmaskable interrupt has to be acknowledged. 25. When the interrupt pins of 8085 are checked by the system? Ans. Microprocessor checks (samples) interrupt pins one cycle before the completion of an instruction cycle, on the falling edge of the clock pulse. 26. Can the microprocessor be interrupted before completion of existing Interrupt Service Subroutine (ISS)? Ans. Yes, the microprocessor can be interrupted before the completion of the existing ISS. Let after acknowledging the INTR, the microprocessor is in the ISS executing instructions one by one. Now, for a given situation, if the interrupt system is enabled (by inserting an EI instruction) just after entering the ISS, the system can be interrupted again while it is in the first ISS. If an interrupt service subroutine be interrupted again then this is called nested interrupt. 27. Bring out one basic difference between SIM and DI instructions. Ans. While by using SIM instruction any combinations or all of RST 7.5, RST 6.5 and RST 5.5 can be disabled, on the other hand DI disables RST 7.5, RST 6.5, RST 5.5 and in addition INTR interrupt also. 28. What is RIM instruction and what does it do? Ans. The instruction RIM stands for Read Interrupt Mask. By executing this instruction in software, it is possible to know the status of interrupt mask, pending interrupt(s), and serial input. 29. In an interrupt driven system, EI instruction should be incorporated at the beginning of the program. Why? Ans. A program, written by a programmer in the RAM location, is started first by system reset and loading the PC with the starting address of the program. Now, with a system reset, all maskable interrupts are disabled. Hence, an EI instruction must be put in at the beginning of the program so that the maskable interrupts, which should remain unmasked in a program, remain so. 30. How the system can handle multiple interrupts? Ans. Multiple interrupts can be handled if a separate interrupt is allocated to each peripheral. The programmable interrupt controller IC 8259 can also be used to handle multiple interrupts when they are interfaced through INTR serial input. 31. When an interrupt is acknowledged, maskable interrupts are automatically disabled. Why? Ans. This is done so that the interrupt service subroutine (ISS) to which the program has entered on receiving the interrupt, has a chance to complete its own task.

32. What is meant by nested interrupts? What care must be taken while handling nested interrupts? Ans. Interrupts occurring within interrupts are called nested interrupts. While handling nested interrupts, care must be taken to see that the stack does not grow to such an extent as to foul the main programin that case the system program fails. 33. A RIM instruction should be performed immediately after TRAP occursWhy? Ans. This is so as to enable the pre-TRAP interrupt status to be restored with the implementation of a SIM instruction. 34. What does the D4 bit of SIM do? Ans. Bit D4 of SIM is R 7.5 which is connected to RST 7.5 F/F via a OR gate. If D4 of SIM is made a 1, then it resets RST 7.5 F/F. This thus can be used to override RST 7.5 without servicing it. 35. Comment on the TRAP input of 8085. Ans. Trap input is both edge and level sensitive. It is a narrow pulse, but the pulse width should be more than normal noise pulse width. This is done so that noise cannot affect the TRAP input with a false triggering. Again the pulse width should be such that the TRAP input which is directly connected to the gate stays high till the completion of current instruction by the mP. In that case, only the program gets diverted to vector call location 2400 H. TRAP cannot respond for a second time until the first TRAP goes through a high to low transition. TRAP interrupt, once acknowledged, goes to 2400 H vector location without any external hardware or EI instruction, as is the case for other interrupt signals to be acknowledged. 36. explain the operation of a DMA controller.(refer text) 37. write a note on stack memory 38. explain the interrupts of 8085

CHAPTER-6
Counters
A loop counter is set up by loading a register with a certain value Then using the DCR (to decrement) and INR (to increment) the contents of the register are updated. A loop is set up with a conditional jump instruction that loops back or not depending on whether the count has reached the termination count. The operation of a loop counter can be described using the following flowchart.

Delays It was shown in Chapter 2 that each instruction passes through different combinations of Fetch, Memory Read, and Memory Write cycles. Knowing the combinations of cycles, one can calculate how long such an instruction would require to complete. The table in Appendix F of the book contains a column with the title B/M/T. B for Number of Bytes M for Number of Machine Cycles T for Number of T-State.

Knowing how many T-States an instruction requires, and keeping in mind that a T-State is one clock cycle long, we can calculate the time using the following formula: Delay = No. of T-States / Frequency

For example a MVI instruction uses 7 T-States. Therefore, if the Microprocessor is running at 2 MHz, the instruction would require 3.5 mSeconds to complete.

Delay loops
We can use a loop to produce a certain amount of time delay in a program. The following is an example of a delay loop: MVI C, FFH LOOP DCR C JNZ LOOP 7 T-States 4 T-States 10 T-States

The first instruction initializes the loop counter and is executed only once requiring only 7 TStates. The following two instructions form a loop that requires 14 T-States to execute and is repeated 255 times until C becomes 0. We need to keep in mind though that in the last iteration of the loop, the JNZ instruction will fail and require only 7 T-States rather than the 10. Therefore, we must deduct 3 T-States from the total delay to get an accurate delay calculation. To calculate the delay, we use the following formula: Tdelay = TO + TL Tdelay = total delay TO = delay outside the loop TL = delay of the loop TO is the sum of all delays outside the loop. TL is calculated using the formula TL = T X Loop T-States X N10 Using these formulas, we can calculate the time delay for the previous example: TO = 7 T-States Delay of the MVI instruction TL = (14 X 255) - 3 = 3567 T-States 14 T-States for the 2 instructions repeated 255 times (FF16 = 25510) reduced by the 3 T-States for the final JNZ. TDelay = (7 + 3567) X 0.5 mSec = 1.787 mSec Assuming f = 2 MHz

Using a Register Pair as a Loop Counter

Using a single register, one can repeat a loop for a maximum count of 255 times. It is possible to increase this count by using a register pair for the loop counter instead of the single register.

A minor problem arises in how to test for the final count since DCX and INX do not modify the flags. However, if the loop is looking for when the count becomes zero, we can use a small trick by ORing the two registers in the pair and then checking the zero flag.

The following is an example of a delay loop set up with a register pair as the loop counter. LXI B, 1000H LOOP DCX B MOV A, C ORA B JNZ LOOP 10 T-States 6 T-States 4 T-States 4 T-States 10 T-States

Using the same formula from before, we can calculate: TO = 10 T-States The delay for the LXI instruction

TL = (24 X 4096) - 3 = 98301 T- States 24 T-States for the 4 instructions in the loop repeated 4096 times (100016 = 409610) reduced by the 3 T-States for the JNZ in the last iteration.

TDelay = (10 + 98301) X 0.5 mSec = 49.155 mSec Nested Loops Nested loops can be easily setup in Assembly language by using two registers for the two loop counters and updating the right register in the right loop. In the figure, the body of loop2 can be before or after loop1.

Nested Loops for Delay

Instead (or in conjunction with) Register Pairs, a nested loop structure can be used to increase the total delay produced. MVI B, 10H LOOP2 LOOP1 MVI C, FFH DCR C JNZ LOOP1 DCR B JNZ LOOP2 7 T-States 7 T-States 4 T-States 10 T-States 4 T-States 10 T-States

Delay Calculation of Nested Loops

The calculation remains the same except that it the formula must be applied recursively to each loop. Start with the inner loop, then plug that delay in the calculation of the outer loop.

Delay of inner loop TO1 = 7 T-States

MVI C, FFH instruction

TL1 = (255 X 14) - 3 = 3567 T-States 14 T-States for the DCR C and JNZ instructions repeated 255 times (FF16 = 25510) minus 3 for the final JNZ.

TLOOP1 = 7 + 3567 = 3574 T-States Delay of outer loop TO2 = 7 T-States MVI B, 10H instruction

TL1 = (16 X (14 + 3574)) - 3 = 57405 T-States 14 T-States for the DCR B and JNZ instructions and 3574 T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for the final JNZ.

TDelay = 7 + 57405 = 57412 T-States

Total Delay TDelay = 57412 X 0.5 mSec = 28.706 mSec

Increasing the delay

The delay can be further increased by using register pairs for each of the loop counters in the nested loops setup. It can also be increased by adding dummy instructions (like NOP) in the body of the loop.

1. 2. 3. 4. 5. 6.

. write a note on counters and time delays. Explain time delay using one register Explain time delay using a register pair Explain time delay using loop within a loop Explain hexadecimal counter with program(refer text )

CHAPTER-7
1. 2. 3. 4.
5.

Explain the basic cocept of memory interfacing Explain the memory interfacing with SDK 85 memeory chip. Define memory and explain the classification of memory. Discuss the folling: cache memory,main memory, read only memory
Mention the memory capacities corresponding to the number of address lines 10, 11, 12 .... 16.

Ans. The memory capacities corresponding to the number of address lines 10, 11, ... 15, 16

are 1 K, 2 K, 4 K, 8 K, 16 K, 32 K and 64 K, respectively. 6. refer text book for interfacing of some circuit and to find its memory map like interfacing circuit using 3-8 decoder to interface the 2732 EPROM memory chip ect.

CHAPTER-8
1. 2. 3. 4. 5. Write a note on peripheral mapped I/O and memory mapped I/O. Brinf out the difference b/w peripheral mapped I/O and memory mapped I/O. Explain the I/O interfacing with block diagram Explain the interfacing of input devices Explain the interfacing of output displays