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EEET2366
Two-Stage OPAMP Design Project
9/18/2013
Contents
Contents ............................................................................................................................... 1
Table of illustrations ............................................................................................................ 3
1
Introduction ................................................................................................................. 1
Typology ................................................................................................................ 1
2.2
Specifications ......................................................................................................... 2
2.3
Calculations ............................................................................................................ 2
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.2
5.3
5.4
5.4.1
5.4.2
5.5
6
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.5
6.6
Power ................................................................................................................... 35
Summary.................................................................................................................... 36
Discussion .................................................................................................................. 36
Conclusion ................................................................................................................. 37
Table of illustrations
Figure 1: OPAMP typology................................................................................................. 1
Figure 2: Specifications ....................................................................................................... 2
Figure 3: Technology information ....................................................................................... 2
Figure 4: First calculation results ........................................................................................ 5
Figure 5: First simulation schematic ................................................................................... 5
Figure 6: Test bench ............................................................................................................ 6
Figure 7: First run (gain = 55.64dB) ................................................................................... 6
Figure 8: Channel Modulation ............................................................................................. 6
Figure 9: Characterization PMOS (up) and NMOS (down)................................................ 7
Figure 10: Test bench for simulation and optimization ...................................................... 8
Figure 11: Simulation setup (test bench 1) .......................................................................... 9
Figure 12: ADE setup .......................................................................................................... 9
Figure 13: Calculate the phase margin (up) and unity gain frequency (down) ................. 10
Figure 14: Output results of the phase margin (left) and the output voltage in kV (right) 10
Figure 15: First simulation optimization ........................................................................... 11
Figure 16: Simulation setup with optimized variables ...................................................... 11
Figure 17: Simulation result (with optimized sizes).......................................................... 12
Figure 18: Characteristic of the optimized circuit (using calculator without testing on
specific test bench) ............................................................................................................ 12
Figure 19: Test bench (schematic) .................................................................................... 13
Figure 20: Transient simulation setup ............................................................................... 13
Figure 21: Output waveform ............................................................................................. 14
Figure 22: Output waveforms (zoom in) ........................................................................... 14
Figure 23: ICMR ADE setup ............................................................................................. 15
Figure 24: Plot Vout/Vin ................................................................................................... 15
Figure 25: ICMR simulation result .................................................................................... 16
Figure 26: Open loop gain test bench ................................................................................ 16
Figure 27: Simulation profile ............................................................................................ 17
Figure 28: Output waveform ............................................................................................. 17
Figure 29: Simulation profile setup ................................................................................... 18
Figure 30: Input offset ....................................................................................................... 18
Figure 31: Values on the linear region of the opamp ........................................................ 19
Figure 32: Schematic view (test bench) ............................................................................ 19
Figure 33: Simulation profile (testing Vout = 0 when Vin = 0) ........................................ 20
Figure 34: Check for Vout when Vin dc is zero (result) ................................................... 20
Figure 35: Transfer function and phase margin test bench ............................................... 21
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1 Introduction
The purpose of this paper is to report the procedure and results when designing a twostage Operational Amplifier (OPAMP) using Cadence EDA tools and the process design
kit (PDK) AMI 0.6u library. The design must meet a set of specifications (See section
2.2)
Based on the provided OPAMP typology, the OPAMPs transistor sizes, base current,
miller capacitor will be calculated by hand. Then those results will be placed into the
schematic for the very first simulation. Any changes in the provided typology are
welcomed. If the calculated transistor sizes and values (bias current and miller capacitor)
cannot produce the required specifications (as they are most likely cannot), students are
required to optimize the schematic to produce the final OPAMP which satisfies all
specifications.
During the design process, there are some design choices which have been made:
1. Change the length of the design from minimum 600nm to 1.8um
2. Using simulation tool and parametric sweeping to optimize the OPAMP instead of
doing by hand
The final design has the maximum transistor size of 150um (M6), the capacitor Cc of
2.5pF and the bias current Ib of 30uA and meets all the design specifications.
2 Hand calculation
2.1 Typology
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2.2 Specifications
Figure 2: Specifications
2.3 Calculations
Compensation capacitance CC
CC 0.22CL = 0.22*10pF = 2.2pF
Choose CC = 3pF.
Current I5
I5 = SR*CC = 10*106*3*10-12 = 30*10-6 = 30uA
W3/L3 (Size of transistor M3)
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Trans-conductance gm1
VDS5
0.475V
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Trans-conductance gm6
gm6 10*gm1 = 10*94.25uS = 942.5uS
Tran-conductance gm4
47.12uS
S6 = (942.5*2)/40.8 = 32.66
Choose S6 = 33
Current through M6 (I6)
< 1V
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First calculation
M1, M2
M3,M4
M5,M8
M6
M7
Cc
IB
Av
3
2
3
35
35
3pF
30uA
58.39dB
Hand
optimization
3
23.45
3
137
8.76
3pF
30uA
72dB
Width
5.4u
42.15u
5.4u
246.6u
15.75u
3p
30uA
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PMOS
2.3
Figure 8: Channel Modulation
This number is too big and therefore will decrease the gain significantly. To solve this,
we need to find a way to decrease the channel length modulation.
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this lab, instead of using the minimum length 0.6um we will use the length of 1.8um.
4 Simulation Optimization
To optimize the design, we will create the following test bench and use parametric sweep
to estimate the parameters of the design which will satisfy the specifications.
For later usage, the widths of the transistors will be set as variables as the table below.
Variable
Width of M1,M2
Width of M3,M4
Width of M6
Width of M7
Name
w12
w34
w6
w7
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Name
w12
w34
w6
w7
Sweep range
1.5u to 30u
1.5u to 10u
1.5u to 300u
1.5u to 200u
Total steps
5
5
5
5
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Figure 13: Calculate the phase margin (up) and unity gain frequency (down)
Figure 14: Output results of the phase margin (left) and the output voltage in kV (right)
There are multiple combination of the sizes of M1, M2, M3, M4, M6, M7 which can
produce the gain bigger than or equal the required gain (72dB) and the phase margin
bigger than 60deg.Choosing one parameter set among those and perform the individual
checking (for open loop gain, phase margin, slew rate).
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Observation: At this point, based on this graph (Figure 14) we can draw three
observations as follow:
-
For first simulation, to ensure the phase margin will not be violated, I chose a set of
transistor sizes which produce the gain of 4kV (72dB) and the phase margin (through the
calculator) is more than 63 deg. The parameters set are:
Device
M1, M2
M3,M4
M6
M7
Sweeping size
8.6u
3.6u
76u
51u
Chosen size
9u
3.6u
75.6u
50.4u
Simulate again using the same test bench while configure the variables to their optimized
values (See Figure 16):
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Since we monitor the gain, unity gain frequency and the phase margin using expression
of the calculator on the simulation profile, we can see the rough values of those specs as
follow:
Gain
Unity gain bandwidth
Phase margin (using calculator)
71.79dB
5.388MHz
61.92 DEG
Figure 18: Characteristic of the optimized circuit (using calculator without testing on specific test bench)
These results above is the raw calculation and might not be very accurate (which I
observe later that they are indeed not very accurate in comparison to the values calculated
using specific test benches), therefore we will use specific test benches to test for the
specifications.
There are in total 5 test benches:
-
Unity gain buffer: This test bench is used to test the output in time domain
when the OPAMP acts as a unity gain buffer. This also tests for any distortion
during OPAMP operation. For a good OPAMP, we expect the output to be
closely follows the input. In the ideal case, we expect the output to be exactly
identical to the input voltage.
Common mode range: This test bench is used to test the input common mode
range of the circuit. We will sweep the input voltage from Vss to Vdd and
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We will test the transient behavior of the amplifier by run a transient simulation in 10ms
(10 cycles), plot the input and output voltages. The setup is as below:
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Comments:
The output follows the input very closely (nearly no distortion) which means the
amplifier successfully performs as a unity gain buffer.
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DC analysis
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Vin (V)
-2.39
-1
1.5
2.5
Gain (times)
1.040289 (max)
1.000054
999.6048
839.5372(min)
Table 3: ICMR simulation output table
Comment:
The gain is very close to 1 during the input common mode range -1V to 1.5V, therefore
the design satisfy the specification.
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The voltage swing from -2.498V (at -2.5V) to 2.346V (at 2.5V)
Next, the sweeping range will be changed to -5mV to 5mV with total steps of 100 to
zoom in to the transition part. The settings are captured as follow:
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The input offset is measured where the output is 0. The value measured is 54.4203uV.
This is a good value consider the desired ideal value is 0.
Gain = slope =
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Run this simulation again and check for the output voltage where the input voltage (dc) is
zero.
Since Vout = 0 would be the ideal case, we accept Vout which is less than 100mV (when
there is no dc input voltage).
When there is no dc input voltage, the output voltage in this case is 2.47mV < 100mV
(This means the voltage compensate Vos must have value -54.4203uV instead of
54.4203uV. However, at this state this mistake will not affect the results very much
because of two reasons: First the offset still less than 100mV therefore its effect will not
be noticeable. Second, this set of variables does not match the gain and slew rate
anyway). For 3rd and 4th try, the compensate voltage can reduce the offset to nano volts.
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Now we are ready to perform observe the output voltage when the frequency changes.
Firstly setup the test bench as follow:
Then, create a simulation profile which sweeps the frequency of the input AC voltage
source from 100Hz to 100MHz.
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Figure 39: Output gain (yellow curve) in dB and phase (green curve)
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Figure 40: Use marker to find the frequency where gain is 0dB
Then we setup another marker to mark the phase (in deg) at the unity gain frequency.
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Running a transient simulation to 600ns (3 cycles) and plotting the input and output
voltages with the following setups:
Choosing Cc = 3pF gives the slew rate of 0.99V/us which is very low compared to the
requirement.
5 Third try
Since the first set of parameters did not produce the expected output, we try to sweep the
values again using wider range:
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Chosen size
30.6u
3.6u
76u (choose 75.6u)
51u (choose 50.4u)
3pF
30uA
Figure 49: Devices sizes
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Figure 50: Output voltage still follows the input voltage closely
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Vin (V)
-2.5V
-2.39
-1
1.5
2.5
Gain (times)
999.3933mV
1.007471V (max)
999.9477mV
999.666mV
812.2921(min)
Figure 52: ICMR results
Figure 53: Output voltage swings from -2.498V (at -2.5V) and 2.341V (at 2.5V)
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71.3dB
8.65203MHz
53DEG
Again, the phase margin and the gain do not match specification.
6 Fourth try
Since the phase margin will be increased once we increase the size of M7, we choose
another set of sizes as follow:
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Chosen size
22.87u (choose 22.95u)
3.6u
150.75u(choose 150u)
100.75u (choose 100u)
3pF
30uA
Figure 58: Optimization variables
Run the simulations again and the slew rate does not satisfy. After some changing (all by
hand), new parameters are:
Device
M1, M2
M3,M4
M6
M7
Cc
Ib
Chosen size
22.95u
3.6u
150u
100u
2.5pF
30uA
Figure 59: Change the simulation profile
Figure 60: Unity gain buffer (output still closely follows input)
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Vin (V)
-2.5
-1
1.5
2.5
Gain (times)
0.9996982
1.000022
0.999586
0.8151529(min)
Figure 62: ICMR satisfy
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Figure 67: Transfer function (72.3571dB) and phase margin (60.55deg), unity BW (9.55948MHz)
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6.6 Power
Using the same test bench as unity gain buffer case, we setup the simulation profile as
follow:
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7 Summary
Device
M1, M2
M3,M4
M6
M8, M5
M7
Cc
Ib
ICMR
Unity gain at -1V input
Unity gain at 1.5V input
Unity gain frequency
Low frequency gain
Phase margin
Slew rate
No load
With load
Power
Chosen size
22.95u
3.6u
150u
5.4u
100u
2.5pF
30uA
1.000022
0.999586
9.55948MHz
72.3571dB
60.55deg
Rising
11.63V/us
11.79V/us
4mW
Falling
10.392V/us
11.07V/us
8 Discussion
After changing sizes and values trying to optimize the design to match the specifications,
there are some observations/conclusions as follow:
1. Increase the minimum length of the transistors can help to increase the overall
gain because the channel length modulation effect would be less noticeable.
2. The slew rate depends heavily on Cc (can increase 10x when the capacitor changes
from 3pF to 2.5pF). The slew rate where there is not load is smaller than the slew
rate with load and the slew rate on the rising edge is bigger than the slew rate on
falling edge.
3. To some extend increase size of M1, M2 can increase the gain. However, when
increase too much; it might come into the combination (with other sizes of M6,
M7, M3, m4) where the gain is very small.
4. Choose a parameter set in which size of M7 is big will ensure a good phase
margin.
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9 Conclusion
This paper has successfully designed a twostage OPAMP which can meet the design
specifications stated at the beginning of the report. Since we try to keep the sizes of the
transistors to be as small as possible, the achieved specifications neatly meet the design
specifications. As a result, good layout is necessary because if the layout is well-done, the
post layout simulation can produce the same or even better specifications. On the other
hand, bad layout might result an OPAMP which fails to meet the design specifications.
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