1

1
Shyama P. Das
Department of Electrical Engg.
IIT Kanpur
E-mail: spdas@iitk.ac.in
Unified Power Quality Unified Power Quality
Conditioner (UPQC) for Conditioner (UPQC) for
Power Distribution Systems Power Distribution Systems
2
Introduction
Motivation
Design, Simulation and Hardware Implementation of
Unified Power Quality conditioner (UPQC)
(Single phase and Three phase)
Optimum UPQC
Conclusion and Scope of future research
2
3
Power Quality Power Quality: Measure of proper utilization of power by
customers
Electrical Pollutant vs Clean Utility
Advent of wide spread use of high power high frequency
switching devices
Additional System required to maintain quality
Deregulation, tariff
+
Power Supply
Authority
Consumer
Power
Quality
Responsibility of Both!
Clean Power
Supplyf
Correction
Neasure
No Electrical
Pollution
3
5
PCC
L
O
A
D
Line Impedance
Polluting Load
Voltage
Voltage
Power Quality Affected by Polluting Load
Other loads connected at the Point of Common
Coupling (PCC) suffer!
6
Two Main PQ Problems
Harmonic and reactive current drawn
by the loads.
voltage sagf Distortion.
4
7
Harmonic Polluting Loads
Computers
Computer controlled machine tools
Photo-copying machines
Various digital controllers
Adjustable speed drives
PLCs
Uncontrolled or phase controlled rectifiers
8
Some Important Observations of
Power Quality(PQ) Surveys
More low r.m.s. voltage sag occur at the PCC
Majority of voltage sag are 10-20%
More disturbances occur above 70% of nominal line
voltage
The occurrence of most severe sag events are least
frequent.
5
9
POWER QUAL!TY STANDARDS
1.5 1 Above 161 kv
2.5 1.5 115 -161 kv
5 3 69 kv and
below
Naximum
THD
()
Naximum !ndividual
Harmonic
components ()
Bus voltage
(PCC voltage)
IEEE 519 Voltage Limits
10
Local
Solution
Load/
Equipment
Load/
Equipment
Global Solution
(Series/Shunt)
PCC
PCC
OTHER LOADS
Power Quality Solution Strategies
6
11
(a) Providing ride-through capability to the
equipment so that they can be protected against
certain amount of voltage sag and swell
(b) Equipment are provided with an arrangement
so that they draw low reactive power and
harmonics
(c) Disadvantage of this approach is that it cannot
take care of existing polluting installations and
further it is not always economical to provide the
above arrangement for each and every equipment
12
(a) Here independent compensating devices are
installed at PCC so that overall PQ improves at
PCC.
(b) Advantages of this approach are
Individual equipment need not be designed
according to PQ standards
Existing Polluting installations can be taken
care of.
7
13
Nodern Solutions
a)Shunt (parallel) Active Filter (STATCOM)
b) Series Active Filter (DVR)
1+
STATCOM
Static Synchronous Compensator
Compensates For
- Reactive Current
- Harmonic Current
8
15
STATCOM
16
9
17
STATCON
18
STATCON
10
19
STATCOM Control Strategy
i
s
is at Unity Power Factor
20
DVR (Dynamic Voltage Restorer)
V
pcc
V
dc
VS
V
s
V
inj
Corrects For
- voltage sag
- voltage harmonics
11
21
Reactive Power Transfer
V
s
2
=V
L
2
-2V
L
V
dvr
Sin +V
dvr
2
22
In-Phase Compensation
12
23
Phase cum Magnitude Compensation
2+
DeveIopmenf of MuIfipurpose Cusfom Power Equipmenf
Load harmonic and VAR compensation
Voltage sag mitigation and unbalanced voltage
correction
Fast dynamic response, and steady state accuracy
Unified Power QuoIify Condifioner (UPQC) Unified Power QuoIify Condifioner (UPQC)
13
25
Unified Power Quality Conditioner
(UPQC)
26
Inverter-I compensates for sag through a tuned filter and voltage
transformer
Inverter-II (SLCVC) Synchronous Link Converter VAR
Compensator provides VAR to the load, isolates load current
harmonics, makes input power factor unity
SLCVC maintains the charge of the dc link capacitor
Low Pass
Filter
Load
Synchronous
Link Inductor
Inverter- I Inverter- II
C
dc
Utility supply
Injection
Transformer
i
s i_load
i
c
L
SLC
V
inj
14
27
Phasor diagram of UPQC-Q for fundamental power frequency, when <
Quadrature Compensation UPQC Quadrature Compensation UPQC- -Q Q
28
Quadrature Compensation UPQC Quadrature Compensation UPQC- -Q Q
Where, x is p.u. sag
m = Modulation Index (max MI=1)
and transformer ratio 1:1
1
2 1
. ) 2 ( . 2 2
2 / 2
2 2
s
dc inj
s s inj
V x x m
mV V
V V V
=
=
=

cos
cos
2 2 l s I I
From power balance
15
29
Series vA Loading of UPQC-Q
Series VA loading of UPQC-Q
0
0.2
0.4
0.6
0.8
1
0 0.1 0.2 0.3 0.4
p.u. Sag
V
A

p
.
u
.
p.f.=0.25
p.f.=0.5
p.f.=0.6
p.f.=0.7
p.f.=8
p.f.=0.9
30
Shunt vA Loading of UPQC-Q
Shunt VA loading of UPQC-Q
0
0.2
0.4
0.6
0.8
1
1.2
0 0.1 0.2 0.3 0.4
p.u. Sag
V
A

p
.
u
.
p.f.=0.9
p.f.=0.8
p.f.=0.7
p.f.=0.6
p.f.=0.5
p.f.=0.25
16
31
Combined vA Loading of UPQC-Q
Combined Loading of UPQC-Q
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 0.1 0.2 0.3 0.4
p.u. Sag
V
A

p
.
u
.
p.f.=0.9
p.f.=0.8
p.f.=0.7
p.f.=0.6
p.f.=0.5
p.f.=0.25
.
32
17
33
Four Modules
ConfroIIer for moinfoining DC Iink VoIfoge
- PC bosed soffwore confroI
Currenf ConfroIIer for Shunf Inverfer
- AnoIog confroI, insfonfoneous response
Dynomic sog ConfroIIer
- Feed forword ond feedbock confroI combined
PWM VoIfoge ConfroIIer for Series Inverfer
- AnoIog ConfroI
3+
Fig.3.15 Block diagram of hardware implementation
Computer
PCL-208
V
dc
Vs_peak
v75
vsec
v90
DA
0
DA
1
pwm
modulating
signal ( m
3
)
i
s
*
[ADC, DAC,
Timer, DIO]
AD0
AD1
AD2
AD3
AD4
V
s
SPWM
Gate
Drive
N-L Load
Hysteresis
Control
Vs_peak
Peak
Detector
Ckt. Filter
V
inj
Gate
Drive
i
s
i
s
*
DA
0
DA
1
i
s
18
35
Fig. 3.22 Simulation result of
supply and load current
corresponding to Fig. 3.21
X axis = 5 ms/div Y axis =
5 A/div
Supply current ( i
s
)
Load current (i
L
)
Fig. 3.21 Experimental result of
supply current and load current
X axis : 5 ms/divY axis: 5 A/div
36
Fig. 3.23 Load current
(i_load) spectra
(Experimental) 0
20
40
60
80
100
120
1 5 9 13 17 21 25 29 33 37 41 45 49
Harmonic Number
R
e
l
a
t
i
v
e

P
e
r
c
e
n
t
a
g
e
Fig. 3.24 Supply
current ( i
s
) spectra
(Experimental)
0
20
40
60
80
100
120
1 5 9 13 17 21 25 29 33 37 41 45 49
Harmonic Spectrum
R
e
l
a
t
i
v
e

P
e
r
c
e
n
t
a
g
e
19
37
Fig. 3.25
Experimental results
of supply current (i
s
)
and supply current
reference (i
s
*
)
X axis : 5 ms/div Y
axis: 10 A/div
Fig. 3.26 Simulation
results of supply
current (i
s
) and
supply current
reference (i
s
*
)
X axis : 5 ms/div Y
axis: 10 A/div
38
Fig. 3.27 Experimental result of v
L
,
v
s
and vsec
Trace-1: Load voltage (v
L
)
y axis : 50 v/div
Trace-2: Supply voltage (v
s
)
y axis : 50 v/div
Trace-3: Series injected voltage
(vsec) /38. y axis : 1 v/div
x axis : 20ms/div
Fig. 3.28 Simulation result
of v
L
, v
s
and vsec
Trace-1: Load voltage (v
L
)
y axis : 50v/div
Trace-2: Supply
voltage(v
s
) y axis :
50v/div
Trace-3: Series injected
voltage ( vsec) /38.
y axis : 1v/div

Load voltage
Source voltage
Injected voltage
20
39
Fig. 3.29 Load voltage (v
L
) spectra
0
20
40
60
80
100
120
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Harmonic Number
R
e
l
a
t
i
v
e

P
e
r
c
e
n
t
a
g
e
THD = 3.6%
+0
Fig. 3.30 Steady state experimental
results of DC link voltage (Vdc),
supply ( i
s
) and load current ( i
L
)
X axis : 50ms/div Y axis : vdc
20V/div, i
s
, i
L
5A/div
Dc link voltage (vdc)
Supply current (i
s
)
Load current (i_load)
Fig. 3.31 Steady state
simulation results of DC
link voltage (Vdc/1000),
supply (i
s
) and load
current ( i
L
)
X axis : 50 ms/div Y axis :
Vdc .1 V/div, i
L
= 2 A/div
, i
s
= 10 A/div
21
+1
3-
AC
Source
3-
Non-
linear
Load
i
s
i
c
i_load
Vdc
SLCVC Series
Compensator
Low Pass
Filter
secv
L
SLC
+2
Computer
PCL-208 PCL-726
DA
0
DA
1
v
dc
Vs_peak
secv_a
secv_c
secv_b
v90-A
v90-B
m1-A
m1-B
PI-outA
(m2-A)
PI-outB
(m2-B)
PI-outC
(m2-C)
i
sa
*
i
sb
*
ADC,DAC,
COUNTER
TIMER, DIO
6 ch-DAC,
DIO
AD0
AD1
AD2
AD3
AD4
AD5
AD6
DAC
1
DAC
2
DAC
3
DAC
4
DAC
5
N
V
sb
V
sa
V
sc
SPWM
Gate
Driver
3-
N-L Load
Hysteresis
Control
Vs_peak
Peak
Detector
Ckt. Filter
secv_a
secv_b
secv_c
Gate
Driver
i
sa
i
sb
i
sc
i
sa
i
sb
i
sc
m3-( A B C)
5 kHz
i
sa
*
i
sb
*
i
sc
*
22
+3
isa
i_loada
Fig. 4.20a Experimental results of
supply current and load current of
phase-A
X axis: 50 ms/div, Y axis: 5 A/div
for isa, 2 A /div for i_loada
Fig. 4.20b Simulated results of
supply current and load current of
phase-A
++
Fig. 4.21b Simulated results of supply
current and supply voltage of phase-A
Fig. 4.21a Experimental results of
supply current and supply voltage of
phase-A
X axis: 50 ms/div, Y axis: 5A/div for
isa, 20 V/div for vsa
23
+5
Load Current (A-phase) Supply current ( A-phase) Harmonic
order
Magnitude % fundamental Magnitude % fundamental
1st 1.645 A 100 2.652 A 100
5th 313.47 mA 19 38.989 mA 1.46
7th 204.86 mA 12.45 19.43 mA 0.73
11th 113.09 mA 6.87 23.4 mA 0.88
13th 80.05 mA 4.86 10.18 mA 0.38
17th 31.43 mA 1.91 16.68 mA 0.62
19th 28.13 mA 1.71 15.76 mA 0.59
23rd 13.674 mA 0.83 12.3 mA 0.46
25th 9.159 mA 0.5 10.1 mA 0.38
THD 23.28% 2.957%
Displacement
Factor
0.768 0.992
+6
Fig. 4.23a Experimental result of peak of
supply voltage and load voltage of phase-
A
X axis: 100 ms/div, Y axis: 50 V/div for
v_loada, 10.48 V/div for Vsa_peak,
Peak of supply voltage (A)
Load Voltage (a)
sag
Fig. 4.23b Simulated result of peak of
supply voltage and load voltage of
phase-A
24
+7
Fig. 4.24b Simulated result of peak
of supply voltage and supply
current phase-A
Fig. 4.24a Experimental result of peak
of supply voltage and supply current of
phase-A
X axis: 100 ms/div, Y axis: 20.96
V/div for Vsa_peak, 2 A/div for
i_loada
+8
Fig. 4.25a Experimental result of peak of
supply voltage and injected voltage and
supply voltage of phase A, X axis: 10
ms/div, Y axis: 10 V/div for secv_a,
50 V/div for vsa, 52.4 V/div for Vsa_peak
Fig. 4.25b Simulated result
of injected voltage and
supply voltage of phase-A
25
+9
Fig. 4.26b Simulated result of
injected voltage and supply
voltage of phase-B
Fig. 4.26a Experimental result of
peak of supply voltage and injected
voltage and supply voltage of phase-
B, X axis: 10 ms/div, Y axis: 50
V/div for vsb, 10 V/div for secv_b,
52.4 V/div for Vsa_peak
50
v
inj
by DvR in phase with the supply
voltage
DvR consumes active power
No sharing of Load vAR between
STATCON and DvR
Can compensate for both voltage sag
and swell
Conventional UPQC-P
26
51
Operation under Sag (UPQC-P)
52
Series vA Loading of UPQC-P
Series VA loading of UPQC-P
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 0.1 0.2 0.3 0.4
p.u. Sag
V
A

p
.
u
.
p.f .=0.25
p.f .=0.5
p.f .=0.6
p.f .=0.7
p.f .=0.8
p.f .=0.9
27
53
Shunt vA Loading of UPQC-P
Shunt VA loading of UPQC-P
0
0.2
0.4
0.6
0.8
1
1.2
0 0.2 0.4
p.u. Sag
V
A

p
.
u
.
p.f .=0.9
p.f .=0.8
p.f .=0.7
p.f .=0.6
p.f .=0.5
p.f .=0.25
5+
Combined vA Loading of UPQC-P
Combined Loading of UPQC-P
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.2 0.4
p.u. Sag
V
A

p
.
u
.
p.f .=0.9
p.f .=0.8
p.f .=0.7
p.f .=0.6
p.f .=0.5
p.f .=0.25
28
55
Limitations of UPQC-QfP
UPQC-Q
Unable to mitigate voltage unbalance in magnitude
Unable to mitigate voltage unbalance in phase shift
Does not compensate for voltage swell
UPQC-P
Capable of compensating both voltage sag and swell
Capable of mitigating voltage magnitude unbalance
Unable to mitigate voltage phase unbalance
56
vA Ninimization by !njecting voltage at
an Optimum Angle
29
57
Unbalanced Sag Mitigation
DvR control is done to inject voltage at
an optimized phase angle.
58
DVR Control Strategy
30
59
Source voltages during normal and sag condition
Simulation
Results
Sag end
Sag start
60
Load voltages during normal and sag condition
Simulation
Results
Sag end
Sag start
31
61
Case Study (Optimized UPQC)
Load p.f. angle {) = 30
0
lag, PU voltage sag
{x) = 20%
optimum angle {) = 24
0
Effectiveness of the scheme
through comparison
vA (UPQC-Q) = 0.7 p.u., (0 = 36.7
0
)
vA (UPQC-P) = 0.6 p.u., (0 = 0
0
)
vA (UPQC-proposed) = 0.+8 p.u., (0 = 2+
0
)
62
1. UPQC can mitigate voltage sag.
2. Hybrid (combined analog and digital) control
implemented, the control scheme is applicable for
both single phase and three phase.
3. No additional energy storage device required for sag
compensation, long duration sags and under voltages
can also be compensated.
4. Dynamic response is fast.
32
63
5. UPQC can supply VAR to the load.
6. It isolates the load current harmonics from flowing to
the utility.
7. It maintains input unity power factor at all conditions.
8. Optimized UPQC leads to minimum VA loading of the
converters.
6+
UPQC for fhree phose four wire sysfem
VoIfoge sweII compensofion
33
65