LECTURE BY: SRIKANTH JADCHERLA

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Does the design meet a given timing requirement?!! How fast can I run the design?!!!

Static Timing analysis is a technique used in digital circuit design to analyse if the circuit will satisfy timing constraints. Timing closure refers to a set of optimization techniques which modify the circuit layout to meet the defined performance goals.

 Library elements and timing representation. Liberty format Definition of timing paths Setup Hold PVT (revision) Latch vs. register timing Clock latency and skew (clock uncertainty skew, jitter)

Format of the library is liberty - .lib Library elements will have various attributes connection details , properties of the cell (name , area, pins , maximum capacitance, maximum fan-out ,timing tables.. ) For example:
Pin names, capacitance, Input slopes Vs. Propagation delays etc.,
A B C

Varying slopes

Different loads:
(small Capacitance) (large Capacitance)

Hence propagation slopes will vary according to the slopes and loads Therefore inputs A and B will have different loads and transition slopes.

NON LINEAR DELAY MODEL The loads and slopes are represented using Non-Linear-Delay-Models or Composite Current Source Models. NLDMs use Look Up Tables(LUT) consisting of different load values, rise time values, fall time values etc.,

NLDMs are alone not sufficient. Timing requires functionality.

Why the timing needs functionality??

In the above example:

Timing arc for a given rise or fall times at A and for a given load at C, NLDM gives rise or fall times at C indirectly the transition time from A to C. Transition over input has an effect on output. This is called transition delay. Sometimes it is not necessary. For example:

LOGIC ZERO

A shows continuous transitions and B holds a value of zero so the output always remains zero. No timing is required.

Timing must know the logic of the cells. Timing path can be defined as the propagation of the change at an input pin to an output pin. Every path operates with a clock and/or similar constraint.

So generalising a circuit different timing paths would be:

gate Ff/latch/ primary Input

gate

ff

Clk

gate

ff

Three flip-flops resulting in four timing paths

CONTINUED..

So the path starts at the source and propagates to the sink. The source can be a flip-flop, a latch, primary input, hard macro input. The sink can be a flip-flop or a latch, data pins, hard macro input, primary output. The rest of them would include propagation path. In the previous example the gates form the propagation path.

C1

Ff/latch/ primary Input

gate

gate

Ff/latch/ primary Input C2

Launch edge of flipflop

The delays associated must be in such a way that data has to go out of the flop propagate through this and be ready in time with the clock.
NOTE: In the same clock how is it going?? Each pulse reaches C1 to C2. So the following inequality may be derived. Q1 + (clock to flop delay) (D1 + D2) + SETUP TIME <= CLOCK PERIOD (gate delays) (internal delay of the flop)

Flip-flop internal delay should not be confused with path set up delay. Both are different. Data has to travel from source to sink within the

CLOCK PERIOD C1(since launch happens hurting setup time) + C2 (due to its longer time)

CONTINUED
When there is a launch of data propagating and set up amounts to a period where the data must be ready i.e., After the time d2(delay of last gate) by the time the you through this period data must be propagated through d2 and data ready for the capture while 2nd flip-flop. This is actually the set up time.

: Now if the flip-flops are connected back to back???

Ff/latch/ primary Input

Ff/latch/ primary Input

Here data for the next flip flop will be launched and captured at the same edge . The inequality condition would be Q1(CLOCK TO FLOP DELAY) + C1 <= C2

Soo.. After the clock edge the data set earlier. When there is a clock edge the data must be stable around the edge. This is called hold time.

As soon as the launch data before launch edge reaches C2 it will actually hit flip-flop2 and registered as next gate. Data moves one cycle!!! Difficult to debug.

How to reduce the problem??

Place hold tick buffers to increase the delay:

Q1 + C1 + TBUF <= C2
This delays the capture event

SUMMARY OF SET UP AND HOLD TIME

Period of stability before clock edge is set up and after clock is hold. To avoid problem data must be stable Before tsup of clock and after th of the clock

tsup th

SET UP HOLDTIME (Source launches) (Sink captures) L1 to C1 L1 to C0 L2 to C2 L2 to C1 L3 to C3 L3 to C2

L1 C0

C1 L2

C2 L3

CLOCK UNCERTAINTY SKEW AND JITTER

Variation in propagation of clock from C1 to C2 can help or damage. This is called uncertainty. And the difference between C1 and C2 is the actual skew. Uncertainty is to be considered during synthesis /placement-Routing. Why???? Before clock tree synthesis or before we actually place buffers into end points the difference between C1 & C2 is not known. So uncertainty is the constraint during synthesis. UNCERTAINTY = JITTER + SKEW + MARGIN + SOME OTHER VARIATIONS.

Generally clocks are produced by PLL. Eg: If u have 10ns of clock u would get only 9.9 or 10.1ns. The 0.1ns is the variation. This is termed as Jitter

WHAT IS SKEW???
Actual Clock Skew is the maximum difference in latency to the clock end points . NOTE: The actual concept of finding maximum number and median out of million random numbers is useful here.
As the design increases the difference has to be computed.

FF

FF
Clock pin FF

FF

FF

Consider an example:

If there was a class to attend and if the student is late by 2min then he will miss the class where as if it was the lecturer who is late then there is no problem. Comparing this with launch and capture paths. If the launch path is running late then there would be a problem

EXAMPLE IN THE CASE OF CIRCUITS

Ff/latch/ primary Input Ff/latch/ primary Input

In the above example if C1 is increasing the amount of time available for setup increases. If C2 increases the amount of time available for setup decreases. That is why if there is clock period of 10ns Vs. 11ns, for 11ns Timing would be easier. So as clock period increases timing becomes easier

PROCESS VOLTAGE TEMPERATURE

How does the set up and hold time vary with PVT???
Conditions SLOW Process Voltage V Temp T Effect on setup and hold times.

Set up time becomes worst. Propagation delay increases Less hold violations.
Typical set up and hold times Hold time becomes worst. Propagation delay decreases Less setup violations.

TYPICAL

P
P

FAST

LATCH UP Vs. REGISTER TIMING

CLK

Register

Enable

latch

Basically Involves Non blocking Involves Blocking Assignments. Assignments. Reflection of setup and the No set up and behaviour of the elements. reflection behaviour Samples by capture edge. Sequential logics use registers Combination logics use latches