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Experiment No: -1 Aim: - 1. TTL & CMOS ICs pin diagram, specifications & rating.

Topic Study of 7400 TTL Series / CD 4000 series.

PRIOR CONCEPTS:Symbols & truth tables of AND, OR, NOT, NAND, NOR, EX-OR gates. IC, breadboard.

Proposition:TTL (Transistor Transistor Logic) is bipolar logic family. CMOS (Complementary Metal Oxide Semiconductor) is unipolar logic family. CMOS employs both P-channel and N-channel MOSFETS. 74XX is a series of TTL circuits. 40XX is a series of CMOS circuits.

Pinout Diagram:74XX Series ( TTL ) 1. 7400 40XX Series ( CMOS ) 1. 4001

Quad 2 input

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PVPIT (DEPT. OF ELECTRONICS) NOR gate 2. 7402

2.

4011

Quad 2 input NOR gate 3 7404

Quad 2 input NAND gate 5. 7486

Not gate

4.

7408

Quad 2 input EX-OR gate

Quad 2 input AND gate 5. 7432 OR Gate

Circuit diagram
Quad 2 input OR gate

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Theory:Characteristics of TTL & CMOS ICs : 1) Speed of operation : The speed of operation is specified in terms of the propagation delay. The propagation delay time is the time it takes for the output of a gate to change after the inputs have changed. 2) Power dissipation : This is the amount of power in milliwatts dissipated in an IC. 3) Fan-Out : This is the number of similar gates which can be driven by a gate. 4) Current and Voltage Parameters : High level input voltage, VIH : This is the minimum input voltage which is recognized by the gate as logic 1. Low level input voltage, VIL : This is the maximum input voltage which is recognized by the gate as logic 0. High level output voltage, VOH : This is the minimum voltage available at the output corresponding to logic 1. Low level output voltage, VOL : This is the maximum voltage available at the output corresponding to logic 0. High level input current, IIH : This is the minimum current which must be supplied by a driving source corresponding to 1 level voltage. Low level input current, IIL : This is the minimum current which must be supplied by a driving source corresponding to 0 level voltage. High level output current, IOH : This is the maximum current which the gate can sink in 1 level. Low level output current, IOL : This is the maximum current which the gate can sink in 0 level. High level supply current, ICC (1) : This is the supply current when the output of the gate is at logic 1. Low level supply current, ICC (0) : This is the supply current when the output of the gate is at logic 0.

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5) Noise Immunity : Stray electric and magnetic fields may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. This may cause the voltage at the input to a logic circuit to drop below VIL or rise above VIL and may produce undesired operation. The circuits ability to tolerate noise signals is referred to as the noise immunity. 6) Operating Temperature : The temperature range for consumer applications is 0 to 70o C.

7) Power Supply Requirements : The supply voltage and the amount of power required by an IC are important characteristics required to choose the proper supply voltage.

TTL Subfamilies

High Speed TTL : 74 H Series : Devices in this series use internal resistors of lower value which reduces propagation delay, but this also causes increase in power dissipation. Low power TTL : 74L Series : Devices in this series use internal resistors of larger values, which reduces power dissipation, but this also causes increase in propagation delay. Schottky TTL : 74S Series : Schottky diode is used along with each bipolar transistor of a TTL circuit. Schottky TTL devices are very fast. Low power schottky TTL : 74LS Series : By using larger internal resistances and schottky diodes these devices give the best compromise between low power and high speed. Advanced schottky TTL : 74AS Series : These TTL devices have highest speed. Advanced low power schottky TTL : 74ALS Series : These TTL devices have very low power consumption & the propagation delay is also reasonably low.

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Specifications:1) 2) 3) 1 4) 2 5) 3 6) 4 Parameter Specifications Standard TTL 7400 Series Power supply range Temperature range Fan Out Power dissipation in mw per gate 5 6 Noise immunity Propagation delay in ns per gate QUESTIONS:a. Implement three input OR gate using IC 7432. b. Implement three input AND gate using IC 7408. c. Implement three input NOR gate using IC 4001. d. Implement three input NAND gate using IC 4011. e. What is fan out for standard TTL ICs (74 series) and CMOS ICs (CD 4000 series). Very good 10 4.75V 5.25V 0 to 70oC 10 16 CMOS CD 4000 Series 3V 15V -40 to 85oC >50 0.01 static 1.00 at 1MHz Very good 70

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Experiment No: -2 Aim: - To study and verify the Truth Table of the Basic Logic Gates.
(7400, 7402, 7404, 7408, 7432, 7486, 74266.)

Components & Instruments: ICs 7400, 7402, 7404, 7408, 7432, 7486, 74266, power supply, breadboard, Wires etc.

Theory:Digital circuits are different from analog circuits. Almost all digital circuits are designed for two state operations. This means using only two non-adjacent points on the load line, typically saturation and cutoff. As a result the output voltage has only two states, either low or high. Thus, the digital electronics deals with binary numbers, which has only two values 1 & 0. Logic gates are the digital circuits with one or more voltage but only one output voltage. The most basic gates are called the NOT gate, the OR gate, the AND gate. By connecting these gates in different ways, we can build circuit that performs arithmetic and other function. The symbol and truth table & pin configuration of various gates are given below.

1) Not gate (IC 7404) NOT is a one input and one output logic gate. The output is given as Q = A. Truth table is shown in table. IC 7404 is an NOT gate IC contains total 6 NOT gates.

Input A 0 1

Output Q=A

NOT GATE

2) AND gate (IC 7408) This gate has two input (A, B) and one output Q. The output is related with input as Q = A.B. Truth table is shown in table. IC 7408 is a two input AND gate IC.

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Input 1ut A B 0 0 0 1 1 0 1 1

Output Q=AB

AND GATE

3) OR gate (IC 7432) An OR gate have two inputs (A&B) and only one output Q. The output can be related with two inputs as Q = A+B. Truth table is shown in table. IC 7432 is a two input OR gate IC. This IC contains total 4 OR gates. Input 1ut A 0 0 1 1 B 0 1 0 1 Output Q=A+B

OR GATE

4) NAND gate (IC 7400) The construction and input and output system is same as IC 7404 except that output is related to the input by the equation. Q = AB Symbol and the truth table for 2 input NAND gate is shown below.

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Input 1ut A 0 0 1 1 B 0 1 0 1

Output Q=AB

NAND GATE

5) NOR gate (IC 7402) The explanation of this IC is same as IC 7432. The output of two input NOR gate is given as Q = A+B. A symbol of two input NOR gate and truth table is given below. Input 1ut A 0 0 1 1 B 0 1 0 1 Output Q=A+B

NOR GATE

6) The Exclusive-OR gate The last five gate types are all fairly direct variations on three basic functions: AND, OR, and NOT. The Exclusive-OR gate, however, is something quite different. Exclusive-OR gates output a "high" (1) logic level if the inputs are at different logic levels, either 0 and 1 or 1 and 0. Conversely, they output a " low" (0) logic level if the inputs are at the same logic levels. The Exclusive-OR (sometimes called XOR) gate has both a symbol and a truth table pattern that is unique:
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A 0 0 1 1

B 0 1 0 1

Output

XOR GATE

7) The Exclusive-NOR gate Finally, our last gate for analysis is the Exclusive-NOR gate, otherwise known as the XNOR gate. It is equivalent to an Exclusive-OR gate with an inverted output. The truth table for this gate is exactly opposite as for the Exclusive-OR gate: A 0 0 1 1 B 0 1 0 l Output 1 0 0 1

XNOR GATE

Procedure: 1. Study the circuit diagram. 2. Connect the circuit as shown in fig. by using connecting wires. 3. Switch 'ON' the power supply. 4. Apply the corresponding inputs and verify the truth table.

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Observations:Input Output A Q=A 0 1 1) NOT GATE Input Output A B Q = AB 0 0 0 1 1 0 1 1 2) AND GATE Input Output A B Q = AB 0 0 0 1 1 0 1 1 4) NAND GATE A 0 0 1 1 B Output 0 1 0 1 6) XOR GATE Input Output A B Q = A+B 0 0 0 1 1 0 1 1 3) OR GATE Input Output A B Q = A+B 0 0 0 1 1 0 1 1 5) NOR GATE A B Output 0 0 0 1 1 0 1 1 7) XNOR GATE

Conclusion:Questions:1. Why NAND gate is called as universal gate? 2. Why NOR gate is called as universal gate?

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Experiment No:- 3 Aim:- To study and verify the NAND and NOR as a Universal Gates (7400, 7402). Components & Instruments: - IC 7400, 7402, power supply, breadboard, wires. Circuit Diagram:NAND/NOR as Universal Gate

Theory:NAND gate and NOR gate are called as universal gates because every basic gate can be constructed using these gates. 1. NAND gate: - Logic Equation is Y = A. This gate gives an output of 1 if all of its inputs are 0 or any one of them is 0. In fact it a NOT of AND gate. It is constructed by connecting a NOT gate at the output of AND gate.

A] NAND as NOT gate: - NOT gate can be constructed using NAND gate by connecting both its inputs together. Y = A.A = A
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B] NAND as AND gate: - AND gate is constructed by connecting NAND as NOT gate at the output of NAND gate. Y = A.A = A

C] NAND as OR gate: - Y = A. B = A+B

2. NOR gate: - Logic Equation is Y= A+B. This gate gives an output of 1 if all of its inputs are 0. If any of the input is 1 then o/p will be 0.

A] NOR as NOT gate:-It is constructed by connecting both its input together. Y = A+A = A

B] NOR as OR gate: - It is constructed by connecting a NOR as NOT gate at the output of a NOR gate. Y = A+B =A+B

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C] NOR as AND gate: - Y = A + B = A.B

Observations:-

Conclusion:-

Questions:1. What is the Logic Gate? 2. What are the different Types of the Logic Gate?

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Experiment No:- 4 Aim:- To study and verify the De-Morgan's Theorem. Components & Instruments: - IC 7404, 7432, 7408, power supply, breadboard, wires etc. Circuit Diagram:PART A PART B

Theory: PART A: Statement: The law states that, compliment of the sum is equal to the product of individual complement. As follows, Case1: when A=0, B=0; A+B = 0+0 = 0 = 1 A.B = 0.0 = 1 = 1 Case2: when A=0, B= l; A+B = 0+1 = 1 = 0 A.B = 0.1 = 0 = 0 Case3: when A=l,B=O; A+B = 1 + 0 = 1 = 0 A.B = 1.0 = 0 = 0 Case4: when A=l, B=l; A+B = 1+1 = 1 = 0 A.B = 1.1 = 0 = 0 PART B: Statement: The law states that, compliment of the product is equal to the sum of individual complement. As follows, Case l: when A=0, B=0; A.B = 0.0 = 0 = 1 A+B = 0+0 = 1 = 1
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Case2: when A=0, B= l; A.B = 0.1 = 0 = 1 A+B = 0+1 = 1 = 1 Case3: when A=l, B=O; A.B = 1 . 0 = 0 = 1 A+B = 1+0 = 1 = 1 Case4: when A=l, B=l; A.B = 1.1 = 1 = 0 A+B = 1+1 = 0 = 0

Observation:PART A PART B

A 0 1 0 1

B 0 0 1 1

A+B A.B

A 0 1 0 1

B 0 0 1 1

A.B A+B

Conclusion:-

Questions:1. What is the Demorgans first theorem? 2. Prove the following boolean expressions A+AB = A+B (A+B+AB)(A+B)(AB)=0 AB+ABC+AB=A AB+AB+AB+AB=1

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EXPERIMENTS NO. 5 Aim:Study of K-MAP.

Components & Instruments: - ICs , power supply, breadboard, wires etc. Theory: In digital design there are some disadvantages while using Boolean expression for designing.

1. Reduction is complicated. 2. Ckt since depend on equation. 3. Truth table. To overcome all these remedies us K-map. There is different type of K-map but we will be only 2-variables, 3-variable & 4-variable.

2 variables K-map include four steps. In this step K-map A is always MSB

0 0 0 2

3 VARIABLE K-MAP

include 8 steps. In this type of K-map it can represent in 3 ways.

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00

01

5 11

2 4 VARIABLE K-MAP

10

Include 16 steps. In this type of K-map it can represent in 2 ways. USING TRUTH TABLE WE CAN DRAW K-MAP

AB

CDCD
0

CD

CD

CD

AB

AB

4 12

5 13

7 15

6 14

AB AB

11

10

Conclusion:
Form above we can conclude that K-map is graphical mean for simplifying & manipulating Boolean expression.

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Experiment no. 6 Aim: To study and verify the Half Adder & Full Adder. Components & Instruments: Power supply, bread board, IC 7404, IC 7408, IC 7486, IC
7432, wires etc.

Circuit Diagram:HALF ADDER & FULL ADDER

Theory:
Half & Full Adder: By combining logic gate in the right way we can built circuits that can add and subtract binary bits. In binary system, any number can be represented with the combination of any digits 0 and 1 as shown by binary addition. 0+0=0 1+0=1 0+0=1 Half Adder: Fig. shows a block symbol of half adder. 1+1=0, carry=1

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Inputs A 0 0 1 1

B 0 1 0 1

Outputs Sum 0 1 1 0

Co 0 0 0 1

The output of the X-Or gate is called the (S) sum O/P while the O/P of the AND gate is the Carry (Co). The AND gate produce a high O/P only when both I/P's are high (logic 1). The X-OR gate produces a high O/P if, either of I/P is high. If A & B=0. Output sum = A.B + A.B = 0.0 + 0.0 = 1.0+0.1 =0+0 Sum= 0 Output carry = A .B Co = 0.0 Co= 0 Hence For A =0, B=0, sum= 0 & Co = 0. If A=0, B=1 Output sum = 1 Output carry = 0 Hence If A =0 & B=1, then sum = 1 & carry = 0 if A = 1, B = 0 then Output sum = 1 Output carry = 0 If A & B =1 then Output sum = 0 & Output carry =1 (to next MSB) For Full adder: Half adder circuit is used to add two bits at a time. Full adder circuits are used for addition of three at a time giving sum and carry out.

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Inputs Cin 0 0 0 0 1 1 1 1

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Outputs Sum 0 1 1 0 1 0 0 1

Co 0 0 0 1 0 1 1 1

Consider any case of input combination. e.g. Cin = 1, B =0, A = 1 Now refer fig. Output of P gate, Y 1 = A.B + A.B. = 1.0 + 1.0 =1 Q gate, Y2 = A.B =1.0 =0 S gate, Y3 = Cin. Yl = 1.1 =1 Sum =Cin. Yl = Yl.Cin =1.0 = 0.1 =0+0 =0 Carry out Co. = Y3 +Y2 =1+0 =1 For Cin =1, B =0 & A =1, then Sum O/P= 0 and carry O/P=1. Procedure: 1) Study the circuit diagram. 2) Connect the circuit as shown in fig. by using connecting wires. 3) Switch 'ON' the power supply. 4) Apply the corresponding inputs and verify the truth table.
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Observation: For Half Adder: Inputs A 0 0 1 1 B 0 1 0 1 Outputs Sum Co

For Full Adder: Inputs Cin 0 0 0 0 1 1 1 1 Outputs Sum Co

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Conclusion:Questions: 1) How the multiplexer is used as the Function Generator? 2) What is demultiplexer? 3) What do you mean by half adder and full adder and what they do?

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Experiment no: - 7 Aim: - To study and verify the Half Subtractor and Full Subtractor. Components & Instruments: -Bread board, connecting wires, power supply, ICS
7400,7402,7404,7408, 7486.

Circuit Diagram: -

Theory: By combining logic gate in the right way we can built circuits that can add and subtract binary bits. Binary systems there are only two numbers, 0 & 1. There are four basic cases of binary Subtraction. Half Substractor:Half subtractor is a logic circuit that performs the subtraction of one Binary bit only. It Subtracts B (Subtracted) from A (minuend) and generates the difference (D) and borrow (Bo). Following figure shows the block systematic of half substractor.

Inputs A 0 0 1 1

B 0 1 0 1

Outputs D 0 1 1 0

B 0 1 0 0

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The output of the Ex-OR gate called differences while the O/P of AND gate is the barrow. Consider the Condition A=0, B=0 O/P Difference =AB + AB = 1.0 + 0.1 =0 O/P of Borrow= A.B. = 1.0 =0 Full Subtractor:Substractor is a Logic Circuit that performs the Subtraction of 3 bits, where A (minuend), B and Cn-1 (borrow from previous Stage) are the I/P's and Difference (D) and Borrow (B).

Inputs Cn-1 0 0 0 0 1 1 1 1

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Outputs D 0 1 1 0 1 0 0 1

B 0 1 1 1 0 0 0 1

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Procedure: 1) Study the circuit diagram. 2) Connect the circuit as shown in fig. by using connecting wires. 3) Switch 'ON' the power supply. 4) Apply the corresponding inputs and verify the truth table.

Observation Table:
Half Subtractor Input Output A B D B 0 0 0 1 1 0 1 1 Full Subtractor

Cn-1
0 0 0 0 1 1 1 1

Inputs A OutputsB
0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Output D B

Conclusion: -

Questions: 1)What is the Karnaugh map? 2)What do you mean by half and full subtractor and what they do?

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Experiment no: - 8 Aim: -To study and verify the 4 Bit Adder. (IC-7483). Components & Instruments: - Breadboard, connecting wires, power supply, IC 7483. Circuit & PIN Diagram:

Theory:A full adder capable of adding two 1 bit binary no. and carry-in. When two n-bit binary numbers are to be added, the number of full adder required will be equal to the number of bits 'n' in each number. The addition of LSB can be done by half adder or full adder (with making carry ground). A parallel adder is used to add to two numbers in parallel form and to produce the sum of bits as parallel output. A block diagram of 4 bit is shown below, is capable of adding of two 4 bit numbers designated as A3 A2A1A0and B3B2B1B0.The resulting output sum bits are S3S2S1S0.

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Procedure:1) Study the circuit diagram. 2) Connect the circuit as shown in fig. by using connecting wires. 3) Switch 'ON' the power supply. 4) Apply the corresponding inputs and verify the truth table.

Observation:Cin 0 0 0 0 A4 1 0 1 0 A3 1 0 0 1 A2 1 1 0 0 INPUT Al 1 1 1 1 B4 1 1 0 0 B3 1 1 1 0 B2 1 0 0 0 B1 1 0 0 1 Cout S4 OUTPUT S3 S2 S1

Conclusion: -

Questions:1.What is ripple carry adder ? 1. Explain BCD adder.

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Experiment no: -9 Aim: -To study and verify the 4 Bit comparator (IC-7485). Components & Instruments: - Breadboard, connecting wires, power supply, IC 7485. Circuit & PIN Diagram:

Theory:Comparator is a logic circuit, used to compare the magnitudes of two binary numbers, depending on the design, it may either simply provide an output that is active when the two numbers are equal, or additionally provide outputs that signify which of the numbers is greater when equality does not hold X-NOR gate is a basic comparator, because its output is 1 only if its two input bits are equal, i.e. the output is a 1 if and only if the input bit coincides. Fig shows the operation of an X-NOR gate is a comparator. Two binary numbers are equal, if and only if all their corresponding bits coincide. For example, two 4-bit binary numbers A3A2A1Ao and B3B2B1Bo are equal, if and only if A3=B3, A2=B2, A1=B1 and A0=B0.Thus,equality holds when A3 coincides with B3, A2 coincides with B2, Al coincides with B1, and A0 coincides with B0.

Procedure: 1) Study the circuit diagram. 2) Connect the circuit as shown in fig. by using connecting wires. 3) Switch 'ON' the power supply. 4) Apply the corresponding inputs and verify the truth table.

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Observation: Sr. No. 1 2 3 4 5 A3 0 0 0 0 0 A2 0 1 0 1 1 INPUT Al A0 0 1 0 1 0 0 1 1 1 1 B3 0 0 0 0 0 B2 0 1 0 1 0 B1 1 0 0 1 0 B0 0 0 0 0 0 OUTPUT A>B A=B A<B

Conclusion: Questions: 1. What is the Combinational Logic Design? 2. What is the difference between the Sequential & the combinational Logic circuit?

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Experiment no: - 10 Aim: - To study and verify the Multiplexer (IC-74151) & De-Multiplexer (IC-74138). Components & Instruments: - IC 74151, IC- 74138, DC Supply Voltage (+5v). Circuit & Pin Diagram:A) Multiplexer

B) Demultiplexer

Theory:A) A multiplexer is a circuit with many inputs but only one output. i.e. Multiplex means many into one. By applying control signals, we can select many inputs into to the output. The circuit has 'n' input signals 'm' control signals & Only One Output signal. S 2S1S0=000, then complement of data I/P I0 is transmitted at the output.

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The 8:1 multiplexer has 8 input bits, 3 control bits and 1 output bit. IC 74151 is a 8:1 TTL multiplexer with the pin diagram shown in given fig. This is a 16 pin IC. It has 8 Data Input I0-I7, Three Control (Select) S2, S1 S0 I/P signal and one O/P (Y), which is Compliment of Selected Data. The pin 7 is active Low Enable/Strobe I/P. A low enable/strobe enables the Mltiplexer. But a high strobe disable O/P becomes high If strobe/enable is low, then O/P Y equals the complement of the Data I/P depending upon the control Signal S2S1S0,Data I/P I0- I7 is transmitted at the O/P which is compliment of this Data Y =In. Where 'n' is the decimal equivalent of S2S1S0Control Signals. S2S1S0=000, then complement of data I/P I0 is transmitted at the output Y =I0 If I0 is low, Y will be high If I0 is high, Y will be low Similarly If S2S1S0= 111 then Y = I7 I7 is high/low then O/P Y becomes low / high respectively. B) The demultiplexer performs the reverse operation of a multiplexer. It accepts single input and distributes it over several outputs. The select input code determines to which output the data input will be transmitted. The number of output lines is n and the number of select lines is m where n=2m.The data bit is transmitted to the data bit of the output lines and this depends on the value of A0A1A2,the control input. When A0A1A2=000, the upper AND gates is enabled while all other gats are disabled. Therefore, data bit is transmitted only to the D0 output, giving D0=0. If the control A0A1A2 is changed to ABC =111, all the gates are disabled except the bottom AND gate. The data bit is transmitted only to the D7 output, giving D7=0. The demux circuits are used in binary to decimal decoder. The multiplexer with gates are used to realize the Boolean expression in standard SOP form. The IC 74LS138 can be used as DEMUX.

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Procedure: 1. Study the circuit diagram. 2. Connect the circuit as shown in fig. by using connecting wires. 3. Switch 'ON' the power supply. 4. Apply the corresponding inputs and verify the truth table.

Observation:A) Multiplexer: E 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 S1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S0 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 X X X X X X X X X X X X X X I0 INPUT I1 I2 X X X X X X 0 X 1 X X 0 X 1 X X X X X X X X X X X X X X X X X X X X I3 X X X X X X X 0 1 X X X X X X X X I4 X X X X X X X X X 0 1 X X X X X X I5 X X X X X X X X X X X 0 1 X X X X I6 X X X X X X X X X X X X X 0 1 X X I7 X X X X X X X X X X X X X X X 0 1 OUTPUT Y Y

B)Demultiplexer: INPUT El 1 X X 0 0 0 0 0 0 0 0 E2 X 1 X 0 0 0 0 0 0 0 0 E3 X X 0 1 1 1 1 1 1 1 I A0 X X X 0 1 0 1 0 1 0 1 Al X X X 0 0 1 1 0 0 1 1 A2 X X X 0 0 0 0 1 1 1 1 D0 D1 D2

OUTPUT D3 D4 D5 D6 D7

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Conclusion: Questions: 1. How the Karnaugh map is importance in the Digital Circuit? 2. How to construct 8:1 mux using 2:1 mux.

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EXPERIMENT NO. 11 Aim :-Study of 7-SEGMENT display. Components & Instruments: -Bread board, power supply, connecting wires, 7-segments
display, IC 7447, LT 542 (Seven Segment Display)

Theory:We can display any no. from 0 to 9 by turning on various combination segment. Actually each segment (A to F) is nothing but an LED is in segment form. Their connection leads are brought out and by applying a forword vgt. To the segment to turned on, we can display any no between 0 to 9. If we want to display the no 7 then the segment a, b, c should be off similarely the other no can be displayed. Types of 7 segment Display There are two types of 7 segment display. 1. Commomn anode Display 2. Common Cathod Display Common Anode Display : The name indicated the anode terminal of all LED are the segments connected togrther to VCC. Many times the 7 segment LED display are connected at o/p of digital Ics as counter. The counter o/p is in the BCD from which has only fair lines. It cant drive IC between the counter o/p & seven segment display.

Circuit Diagram:-

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Common Cathode Display : The cathode terminal is made common & all the anode terminal are brought out separately. A current limiting resistor is external connected in series with each segment to be illuminated are connected to positive supply voltage VCC. The o/p of this decoder are active high. Therefore whenever a segment is to be turned on the corresponding o/p of the decoder goes high. For displaying the 7 segments is to be connected to the ground.

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Conclusion:-

Questions:1. Write the applications of 7-seg. display

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Experiment no: -12 Aim: -To study and verify the Truth Tables of S-R Flip/Flop (IC-7474), J-K Flip/Flop.
(IC- 7473), T- Flip/Flop, D- Flip/Flop.

Components & Instruments:- Digital Multimeter, Patch Chords, IC 7474, IC 7473, LED,
power supply.

Circuit & Pin Diagram:S-RFlipFlop

Fig.1 J-K FlipFlop

Fig.2 D FlipFlop

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Fig.3 T Flipflop

Fig.4

Theory: A flip-flop is a bistable electronic circuit that has two stable states i.e. its output is either 0 or +5Vdc. The main difference between the analog and digital circuit is that, the digital circuits are designed for two state operations. That means the O/P of the digital circuit has only two states (values), either low or high. In other words the O/P of the digital circuit changes when the I/P changes. However, there are requirements for a digital device or circuit. Whose O/P will remain unchanged, once set, even if there is a change in input. A flip-flop is one such circuit, whose O/P will remain unchanged once set. There are basic three types of Flip-Flops 1. SR Flip-Flop 2. D Flip-Flop 3. JK Flip-Flop A flip-flop is a bistable electronic circuit that has two stable states i.e. its output is either 0 or +5Vdc. One of the easiest methods to construct a flip-flop is to connect two inverters in series. But basic flip-flop can be improved by replacing two inverters with either NAND or NOR gate. The additional input of these gates provides a conventional means for application of input signals to switch the flip-flop from one stable state to another. Two input NAND gates are
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connected to from flip-flop circuit. These two inputs are R&S. The flip-flop has two outputs terms as Q and Q. If flip-flop is put into one state it will remain in that state as long as power is applied or until it is changed. In digital circuit, flip-flops are used in variety of storage, counting, sequencing and timing application. 1. R- S Flip-Flop:The R-S flip-flop is the simplest. It has two inputs, S & R input; it will put the latch into one state or the other. When a flip-flop is set by S input, it is said to be storing binary 1. (O/P= high). When reset by R input, it is said to be storing binary 0 ( O/P = low). An RS flip-flop constructed by cross- coupling two NAND gates as shown in fig.1. Both Q& Q' output goes high, when both R-S inputs are binary 0.This condition is not allowed in normal use of flip-flop, as the Q' represents the complement output of Q. The truth table for RS flip-flop is given. Truth Table:Input R 0 0 1 1 Output Q Q 0 0 0 1 1 0 Not determinant

S 0 1 0 1

2. D Flip-Flop: The R -S Flip flop has two data inputs R & S. Generation of two signals to drive a flipflop is a disadvantage in much application. Furthermore, the forbidden condition of both R and S high may occur inadvertently. This has led to the D Flip Flop a circuit that needs only a single data input. Fig. 3 shows the simple diagram of D Flip- Flop using NOR Gate. Truth Table:Input Output D Q 0 0 1 1 In this circuit the D input is just transferred to the output e.g. If D =0 then output Q is also & If D = 1 output is also 1, as shown in the truth table. 3. T Flip -Flop: The basic digital memory circuit is known as flip flop. It two stable states which are known as the 1 state 0 state. It can be obtained by using NAND or NOR gates. Generally there are two inputs to the flip flops (R, S or J K) and two outputs Q and Q. The outputs Q and Q are always complementary. The circuit has two stable state Q=1 which is referred to as the 1 state ( or set state) whereas in the other stable state Q=0 which is referred to as the 0 sate ( or reset state) If the circuit is in 1 state. It continues to remain in this state and similarly if it is in 0 state, it continues to remain in this state. This property of the circuit is referred to as memory, which is it can store 1 bit of digital information.

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In a JK flip flop, if J=K the resulting flip flop is referred to as a T Flip Flop, as shown in fig. it has only one input, referred to as T input. Its truth table is given in table 1. If T=1 it acts as a toggle which for every clock pulse the output Q changes.

Truth Table:Input T 0 1 Output Q 1 0

4. J-K Flip-flop:JK Flip-Flop is the most versatile binary strange element. It can perform all the functions of SR and D flip-flop. The uncertainty in the State of SR flip- Flop when S = R = 1 can be eliminated by using JK Flip-Flop. Truth Table:Input J 0 0 1 1 Output Q Qn 0 0 Qn

K 0 1 0 1

Procedure: 1. Study the circuit diagram. 2. Connect the circuit as shown in fig. i.e. JK Flip Flop by using connecting wires. 3. Switch 'ON' the power supply. 4. Apply proper I/P to J & K I/Ps of Flip-Flop from Logic I/P. 5. Check the O/P on Logic O/P Section. 6. Change the I/P & Verify the Truth Table.

Observation:
S-R Flipflop: OPERATING MODE Set Reset Undetermined INPUT SD L H L RD H L L CP X X X OUTPUT D Q X X X Q

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D Flipflop: OPERATING MODE Set Reset INPUT OUTPUT Q

SD RD CP D Q H H L H H H

T Flipflop: INPUT T L H OUTPU T Q

J-K Flipflop OPERATING MODE Asynchronous Reset Set Reset Toggle L H H H INPUT RD1 CP1 X OUTPUT Q1

J1 K1 Q1 X X H L L H H H L H

Hold Toggle H (No Change)

Conclusion:-

Questions:2. What is the Latch? 3. What is the Race around condition in the Flip Flop? 4. Draw schematic of 4-bit magnitude comparator. Derive expression for A=B, A>B & A<B.
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Experiment no: -13 Aim:- To study and verify the Decade Counter (IC-7490). Components & Instruments: - IC-7490, Digital Multimeter, Patch Chords, power supply,
etc.

Circuit Diagram:-

Theory: Sequential logic circuits are used for a variety of things, sequencing and storage functions. The O/P of sequential logic circuits is combined function of the various I/P states and the result of previous operation, which are stored in the circuit itself. The sequential operations are generally sequenced by a clock signal. A counter driven by clock can be used to count the number of clock cycles. A decade counter is sequential circuit that counts by tens. It has ten discrete states which represent decimal numbers from 0 to 9. The integrated circuit 7490 a decade counters using the standard 8421 binary code. But reset to 0000 on the tenth count. Following fig shows the pin configuration of IC 7490. IC 7490 internally consists of Mod-2 & Mod-5 Converters. It has two reset pins i.e.R1& R2pin no. 2 & 3 respectively. Both the pins to be connected to logic 1 for clearing O/P. The IC can be reset to 0000 by giving appropriate (high & low) input which are shown in truth table. For counting both inputs either R1 and S1 OR R2 and S2 must be low.

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Input R1 H X L

R2 H L X

S1 L X L

S2 X L X

Output Q3 L Count Count

Q2 L

Q1 L

Q0 L

Procedure: 1) Study the pin configuration of IC 7490. 2) Connect pin no 1 to pin no 12 using connecting wire and apply logic I/P's to pin no. 2,3,6,7 using connecting wires. 3) Switch ON the power supply. 4) Reset the O/P to 0000 by applying logic 1 to R1 and R2 & logic 0 to S1 and S2. 5) Give logic to R2 & S2 and now apply the clock pulse to the pin no 14 and observe the O/P after each clock pulse.

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Observation:Input CP X X X MR1 H H X L XH L H MR2 H H X XH L XH L MS1 L X H L XH XH L MS2 X L H XH L L XH Output Q3 Q2 Q1 Q0

Conclusion: Questions:1. What are the Different Types of the counter? 2. What is the Synchronous Counter? 3. Explain clock skew effect on cascaded flip-flop also explain strategies for minimizing clock skews.

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