Short Paper Proc. of1nt.

Con/, on Advances in Recent Technologies in Communication and Computing 2011

VHDL IMPLEMENTATION OF BIST CONTROLLER

l 2 Jamuna. S and Or. VK Agrawal 1 2 0ept of ECE, OS CE, 0irector, Crucible of Research and Innovation, PES Institute of Technology, Bangalore, India js.jamuna@gmail.com, vk.agrawal@pes.edu functions. In the test mode, a set of test patterns are applied to the circuit and responses are collected. The test responses are then compared with fault-free responses to determine if the CUT works properly.
BIST TECHNIQUE

Abstract: Built-in selftest (BIST) is a design technique

that allows a circuit to test itself It is a set of structured test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks. The principle is to generate test vectors, apply them to the circuit under test or device under test, and then verifY the response. Being an automated testing, BIST enables testing at high speed and high fault coverage. BIST controller coordinates the operations of different blocks of the BIST. Based on the test mode(TM) input to the controller, the system either operates in the normal mode or in the test mode. In this paper we explain an implementation of a restart able logic BIST controller for a combinational logic circuit using VHDL. It allows us to suspend the signature generation at any desired point in the test sequence. In this case, the BIST circuit is considered to comprise hold logic and a signature generation element. The hold logic will be implemented such that an external signal (HOLD) can temporarily suspend signature generation in the signature generation element at specified times during the BIST session.
Keywords: BIST, LFSR, MISR, PRPG, OFT INTRODUCTION

Built-In Self Test is a technique of integrating the functionality of an automatic test system onto a chip. It is a Design for Test technique in which testing (test generation and test application) is accomplished through built in hardware features. The general BIST architecture has a BIST test controller which controls the BIST circuit, test generator which generates the test address sequence, response verification as a comparator which compares the memory output response with the expected correct data and a CUT. We have used LFSR and signature analyzer for testing a three input combinational logic circuit. The BIST controller can be implemented by either hardwired logic in the form of a Finite State Machine (FSM), microcode controller or processor-based [5].
RESTARTABLE LOGIC BIST CONTROLLER

BIST Controller is a finite state machine, whose state transition is controlled by the Test Mode (TM) input. It provides the clock signal to the test pattern generator (LFSR), Circuit Under Test ( C UT) and the signature generation circuit (MISR). The B1ST controller also decides the input to the circuit under test based on whether the module is in normal mode or test mode on seeing the Test Mode (TM) input. A BIST circuit comprises a scan monitor with hold logic and a signature generation element. The hold logic is operable to suspend signature generation in the signature generation element at any desired point in the test sequence. In some embodiments, the hold logic comprises a scan-Ioadable signature hold flip-flop which allows the logic BIST controller to be restarted 188

As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that gnarantee very high fault coverage while minimizing test costs and chip area overhead have become essential [1]. As the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. Integrated circuits are presently tested using a number of structured design for testability (OFT) techniques. These techniques rest on the general concept of making all or some state variables directly controllable and observable [4]. We have designed a circuit that works in two modes. In the normal mode, the circuit elements perfo= their regular

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Short Paper Proc. of1nt. Con/, on Advances in Recent Technologies in Communication and Computing 2011 from any selected pattern within a pattern range and to run to any subsequent pattern. The BIST session can be run incrementally, testing and reporting intermediate MISR signatures. External automatic testing equipment can suspend signature generation at selected times during BIST session to prevent tainting of the signature generation element. Fault detection block diagram is as shown in fig. I. Initially, the registers in LFSR and MISR are reset. Then checking for Test Mode or NOlmal Mode is done by seeing the TM input pin. If TM is low, external inputs are applied to the circuit under test and the circuit works in normal mode. When the TM signal is changed to high, the BIST Controller enters the test mode. Now BIST Controller sets or resets the ENABLE signal depending on whether the HOLD signal is high or low respectively. When the ENABLE is high, LFSR
Fig 1. Block diagram for fault detection

generates the test vectors. These test vectors are applied to the circuit under test and the output is fed to the MISR. MISR computes the signature. When all the test vectors are applied to the circuit, the signature computed by the MISR is compared with a reference value learned from a fault free replica of the circuit under test. outputs

We have three input bits and three output bits for the given circuit to be tested. So we design an LFSR with three output bits to generate the test vectors. Let the LFSR be of maximal length so that we get the test vector sequence or pseudo random binary sequence as (111, 011, 001, 100, 010, 101, 1l0) as explained earlier. This pseudo random binary sequence is applied to the circuit under test and the output is recorded. The output at the end of 7th clock is taken as the signature. We can See that the signature value is 110 for a fault free circuit.
In(O) wire[5 ] QulO

If the signatures match, the circuit is

and DONE to high. Then the

considered as fault free. The BIST Controller sets the PASS/FAIL registers are reset and the Controller waits for the next TM signal. If while the B1ST is in Test Mode, when HOLD signal is enabled, the ENABLE signal is reset by the BIST Controller. In this case, the circuit goes back to the normal mode and the external signals are applied to the circuit under test. Here the registers are not reset. Instead, they will hold their current values, so that the LFSR can continue generating test vectors from the point where it got the HOLD signal and the MISR also will continue computation from the paused value. BIST Controller will check for the HOLD signal low to resume testing the circuit under test. Fault detection using restat1able logic BIST is implemented as shown in the fig!. Two replicas of same circuit are used for implementing fault detection. One circuit is taken as a reference fault free circuit and on the other; logic is added for introducing s_@_O or s_@_1 faults for any wire. Signatures are generated for both the circuits and are compared to detect the fault.

'\.Vire[6] Out1

wirc {7] wire[2 ] Out[2j

Fig2. Circuit interpretation for s_@_* faults

S_@_O[8] and S_@_1[8] are 8 bit input vectors corresponding to the wires in the circuit as shown in the th figlU"e. A 1 at O bit of S_@_O indicates a S_@_O fault at the h wire[O]. Similarly, when 4t bit of S_@_l is set, a S_@_l fault is simulated on the wirer 4]. If both S_@_l and S_@_O is enabled for a wire, the fault free value is taken for that particular wire but faults on other wires will be simulated.

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Short Paper Proc. of1nt. Con/, on Advances in Recent Technologies in Communication and Computing 2011 structures in the design to assist that testing.. In this
SIMULATION RESUL TS OF VHDL IMPLEMENTATION

paper we have shown the simulation results for a BIST controller using VHDL. Restart able BIST controller is designed to monitor fault detection activity with hold logic and a signature generation element. The hold logic is operable to suspend signature generation in the signature generation element at any desired point in the test sequence. Signature mismatch with the reference signature means that the circuit is faulty. There is a small probability that the signature of a bad circuit will be the same as a good circuit.
REFERENCES

When TM

0, the circuit works in normal mode. The external the output is provided.

inputs are applied to the circuit and

The complete BTST logic will be inactive. We can introduce faults using the inputs s_@_O and s_@_l for the required wire and the test circuit output will reflect the fault. When TM and HOLD
= =

I,

0; the circuit works in test mode. The test

vectors from LFSR are applied to the circuit and the output is given to MISR. Faults may be introduced using the inputs s_@_O and s_@_l for the required wire and the test circuit output will reflect the fault.

[I]. M.Bushnell and V.D. Agarwal, " Essentials of Electronic Testing for Digital, Memory and Mixed signal VLSI Circuits" Kluwer Academic Publishers, 2000. [2]. Resve Saleh, Steve Witten, Shariar Mirabbasi et all, "System on Chip: Reuse and Integration", proceedings of IEEEI vol 94, No 6, June 2006

Fig 3. Nonnal Mode: No faults in the test circuit

[3]. Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman," Digital System Testing and Testable Design" [4]. L.T. Wang, Cheng- Wen Wu and Xiaoqing Wen, "VLSI Test Principles & Architectures Design for testability". [5].Sudhakar M. Reddy, Xiang Du, Nilanjan Mukhel:ji, Wu- Tang Cheng" Full- speed Field Programmable Memory BIST Architecture", lTC, 2005. [6] P.H. Bardell, W.H.McAnney and J. Savir, Built-in test for VLSI: Pseudorandom Techniques, John Wiley & Sons, Newyork, 1987. [7]. V.D. Agrawal, C.R. Kime and K.K. Saluja, " A tutorial on BIST pat11:
Fig 5. Test Mode: HOLD enabled

Fig 4. Test Mode: Faults introduced in the test circuit

[Wire 2 S_@_O]

IEEE Design & Test of

Computers, March 1993, pp 73-82. [8]. M.l. Smith, "Application Specific Integrated

CONCLUSION

Circuits". [9]. Mohd Yamani Idna Idris, Mashkuri Yaacob, Zaidi Razak, "A VHDL Implementation Of Uart Design BIST Capability", 2004. 190

Accessibility to internal dense circuitry is becoming a greater problem, and thus it is essential that a designer consider how a device will be tested and incorporate

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