MICROCONTROLLER

Microcontroller is a general purpose device, which integrates a number of the components of a microprocessor system on to single chip. It has inbuilt CPU, memory and peripherals to make it as a mini computer. A microcontroller combines on to the same microchip: The CPU core Memory(both ROM and RAM) Some parallel digital i/o Microcontrollers will combine other devices such as: A timer module to allow the microcontroller to perform tasks for certain time periods. A serial I/O port to allow data to flow between the controller and other devices such as a PIC or another microcontroller. An ADC to allow the microcontroller to accept analogue input data for processing. Microcontrollers are: Smaller in size Consumes less power Inexpensive Micro controller is a stand alone unit, which can perform functions on its own without any requirement for additional hardware like I/O ports and external memory. The heart of the microcontroller is the CPU core. In the past, this has traditionally been based on a 8-bit microprocessor unit. For example Motorola uses a basic 6800 microprocessor core in their 6805/6808 microcontroller devices.

In the recent years, microcontrollers have been developed around specifically designed CPU cores, for example the microchip PIC range of microcontrollers. AT89C51 is the 40 pins, 8 bit Microcontroller manufactured by Atmel group. It is the flash type reprogrammable memory. Advantage of this flash memory is we can erase the program with in few minutes. It has 4kb on chip ROM and 128 bytes internal RAM and 32 I/O pin as arranged as port 0 to port 3 each has 8 bit bin .Port 0 contain 8 data line(D0-D7) as well as low order address line(AO-A7). Port 2 contain higher order address line (A8-A15). Port 3 contains special purpose register such as serial input receiver register SBUF, interrupt INT0,INT1 and timers T0 , T1 many of the pins have multi functions which can be used as general purpose I/O pins (or) Special purpose function can be decided by the programmer itself.

4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes

The

AT89C51

is

low-power,

high-performance

CMOS

8-bit

microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel is high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications

1. ARCHITECTURE OF AN 8051 MICROCONTROLLER The 8051 consist of: P3 Eight-bit CPU with registers A (the accumulator) and B Program counter (PC) Data pointer (DPTR) Flags and the Program Status Word (PSW) Eight-bit stack pointer (SP) Internal ROM or EPROM or FLASH ROM Internal RAM of 256bytes(128bytes general purpose): Four register banks, each containing eight registers Two 16-bit timer / counter: T0 and T1 Full duplex serial data receiver/transmitter; SBUF Interrupts Oscillator and clock circuits Thirty-two input/output pins arranged as four 8-bit ports P0-

PIN OUT DIAGRAM OF THE 8051

P1.0
P1.1

P1.2
P1.3

P1.4
P1.5

P1.6
P1.7

RST (RXD)P3.0
(TXD)P3.1

(INT0)P3.2 (INT1)P3.3 (T0)P3.4

(T1) P3.5

(WR) P3.6
(RD) P3.7

XTAL2 XTAL1 GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vcc
P0.0 (AD 0)

P0.1 (AD 1)
P0.2 (AD 2)

P0.3 (AD 3)
P0.4 (AD 4)

P0.5 (AD 5)
P0.6(AD 6) P0.7 (AD 7)

EA/VPP .
ALE/PPOG

PSEN
P2.7 (A15)

P2.6 (A14)
P2.5 (A13)

P2.4 (A12)
P2.3 (A11)

P2.2 (A10)
P2.1 (A9)

P2.0 (A8)

2. CPU REGISTERS The 8051 contain 34 general-purpose, or working, registers. Two of these, registers A and B hold results of many instructions, particularly for arithmetical and logical operations. The other 32 are arranged as part of internal RAM in four banks, Bank0-Bank3, of eight registers each. 3. PROGRAM COUNTER (PC) The 8051 contain two 16-bit registers: the program counter (PC) and the data pointer (DPTR). Each is used to hold the address of a word in memory. Program instruction bytes are fetched from locations in memory that are addressed by the PC. Program ROM may be on the chip at addresses 000h to FFFh, external to the chip for address that exceed FFFh, or totally external for all address from 0000h to FFFFh. The PC is automatically incremented after every instruction byte is fetched and may also be altered by certain instructions. The PC is the only register that does not have an internal address. The Program Counter (PC) is a 2-byte address that tells the 8051 where the next instruction to execute is found in memory. When the 8051 is initialized PC always starts at 0000h and is incremented each time an instruction is executed. It is important to note that PC isnt always incremented by one. Since some instructions require 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases. There is no way to directly modify its value. The Program Counter is special in that. That is to say, you cant do something like PC=2430h. On the other hand, if you execute LJMP 2340h youve effectively accomplished the same thing.

It is also interesting to note that while you may change the value of PC (by executing a jump instruction, etc.) there is no way to read the value of PC. That is to say, there is no way to ask the 8051 "What address are you about to org 00h 4. DATA POINTER (DPTR)

The DPTR register is made up of two 8-bit registers, named DPH and DPL, which are used to furnish memory addresses for internal and external code access and external data access. The DPTR is under the control of program instructions name, DPH and DPL. DPTR does not have a single internal address; DPH and DPL are each assigned an address. The Data Pointer (DPTR) is the 8051s only user-accessible 16-bit (2-byte) register. DPTR, as the name suggests, is used to point to address something like HL register pair in 8085 microprocessor. It is used by a number of commands that allow the 8051 to access external memory and internal memory. While DPTR is most often used to point to data in external memory, many programmers often take advantage of the fact that its the only true 16-bit register available. It is often used to store 2-byte values that have nothing to do with memory locations. 5. PROGRAM STATUS WORD (PSW) Flags are 1-bit registers provided to store the results of certain program instructions. Other instructions can test the condition of the flags and make decisions based on the flag states. In order that the flags may be conveniently addressed, they are grouped inside the program status word (PSW) and the power control (PCON) registers. The 8051 have four math flags that respond automatically to the outcomes of math operations and three general-purpose user flags that can be set to 1 or

cleared to 0 by the programmer as desired. The math flags include Carry (CY), Auxiliary Carry (AC), Overflow (OV), and Parity (P). User flag is named F0; this general-purpose flags that may be used by the programmer to record some event in the program. Register bank selection may be done by the use of RS0 and RS1 Note that all of the flags can be set and cleared by the programmer at will. The math flags, however, are also affected by math operations.

CY AC

F0 RS1 RS0 OV

--

CY AC F0 RS1 RS0 OV -P

PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

Carry flag Auxiliary carry flag Flag 0 (User Flag) Register bank selector bit1 Register bank selector bit0 Overflow flag Reserved for future use Parity flag

FIGURE

RS1 0 0 1 1

RS0 0 1 0 1

Register Bank 0 1 2 3

Address 00H-07H 08H-0FH 10H-17H 18H-1FH

The program status word is shown above. The PSW contains the math flags, user program flag F0, and the register select bits RS0, RS1 that identify which of the four general-purpose register banks is currently in use by the program.

6. THE STACK AND THE STACK POINTER The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quickly. The 8-bit Stack Pointer (SP) register is used by the 8051 to hold an internal RAM addresses that is called the top of the stack. The address held in the SP register is the location in internal RAM where the last byte of data was stored by a stack operation. When data is to be placed on the stack, the SP increments before storing data on the stack so that the stack grows up as data is stored. As data is retrieved from the stack, the byte is read from the stack, and then the SP decrements to point to the next available byte of stored data.

CPU Action
SP = 0A Address 0A

CPU Action Store data

SP = 0A

Get data

SP = 09

Address 09

Store

SP = 09

Get

data
SP = 08 AddressStore 07

data
SP = 08

Get

data
SP = 07 Address 08

data
SP = 07

Storing data on the stack the stack (Increment then store) decrement)

internal RAM

Getting Data from (get then

Operation of the stack and the SP is shown above. The SP is set to 07h when the 8051 is reset and can be changed to any internal RAM address by the programmer, I.e., default address location of stack pointer is 07h. Using a data move command we can change the stack pointer address. The stack is limited in height to the size of the internal RAM. The stack has the potential (if the programmer is not careful to limit its growth) to over write valuable data in the register banks, bit-addressable RAM, and general purpose (scratchpad) RAM areas. The programmer is responsible for making sure the stack does not grow beyond predefined bounds! The stack is normally placed high in internal RAM, by an appropriate choice of the number placed in the SP register, to avoid conflict with the register, bit and scratch-pad internal RAM areas. The Stack Pointer, like all registers except DPTR and PC, may hold an 8bit (1-byte) value. The Stack Pointer is used to indicate where the next value to be removed from the stack should be taken from. When you push a value onto the stack, the 8051 first increments the value of SP and then stores the value at the resulting memory location. When you pop a value off the stack, the 8051 returns the value from the memory location indicated by SP, and then decrements the value of SP. That is last in first out method (LIFO)

This order of operation is important. When the 8051 is initialized SP will be initialized to 07h. If you immediately push a value onto the stack, the value will be stored in Internal RAM address 08h. This makes sense taking into account what were mentioned two paragraphs above: First the 8051 will increment the value of SP (from 07h to 08h) and then will store the pushed value at that memory address (08h). SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an interrupt is triggered. (More on interrupts later).

7. INTERNAL MEMORY

A functioning computer must have memory for program codes, commonly in ROM, and RAM memory for variable data that can be altered as the program runs. The 8051 has internal RAM and ROM memory functions. Additional memory can be added externally using suitable for these circuits.

Unlike Microcontrollers with Von Neumann architectures, which can use a single memory address for either program code or data, but not for both, the 8051 has a Harvard architecture, which uses the same address, in different memories, for code and data. Internal circuitry accesses the correct memory based on the nature of the operation in progress. Harvard architecture uses separate buses to fetch the data and the address

8. INTERNAL ROM

The 8051 is organized so that data memory and program code memory can be in two entirely different physical memory entities. Each has the same address range. The structure of the internal RAM will be discussed later. Generally 8051 microcontroller is available with 4Kilo Bytes internal ROM.

A corresponding block of internal program code, contained in an internal ROM, occupies code address space 000h to FFFh. The Program Counter is ordinarily used to address program code bytes from address 0000h to FFFFh. Program addresses higher than 0FFFh, which exceed the internal ROM capacity, will cause the 8051 to automatically fetch code bytes from external program memory.

Code bytes can also be fetched exclusively from an external memory, address 0000h to FFFFh, by connecting the external access pin (EA pin no 31 on the DIP) to ground. The PC does not care where the code is, the circuit designer decides whether the code is found totally in internal ROM, totally in external ROM, or in a combination of internal and external ROM. Each register bank address are Bank 0 Bank 1 Bank 2 Bank 3 00h-07h 08h-0fh 10h-17h 18h-1fh

T2 . SERIAL PORT . T1 . EX1 . T0 . EX0 . RESET

FFFh . . . . . . . . . . . . . . . . . 2B . 23 . 1B . 13 . 000B . 0003 . 0000h

8051 microcontroller has 16-bit address bus and 8 bit data bus, with 16-bit address bus we can address maximum of 64Kilobytes of external memory that is from 0000h to FFFF.

051 is available with 4kilobytes of internal ROM its derivatives 8751, 8951 are available with EPROM, FLASH ROM respectively with 4kilobytes capacity.

9. INTERNAL RAM OF 256 BYTES (128BYTES GENERAL PURPOSE): As mentioned at the beginning of this chapter, the 8051 includes a certain amount of on-chip memory. On-chip memory is really one of two types: Internal RAM and Special Function Register (SFR) memory. The layout of the 8051's internal RAM is presented. As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile, so when the 8051 is switched off this memory is cleared. The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes (00h - 07h) are "register bank 0". By manipulating certain SFRs, a program may choose to use register banks 1, 2, or 3. These alternative register banks are located in internal RAM in addresses 08h through 1Fh. So the registers are part of internal RAM. Bit Memory also lives and is part of internal RAM. Bit memory actually resides in internal RAM, from addresses 20h through 2Fh. It can be bit addressed from 00h to 7fh (totally 128 bits)

The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by user variables that need to be accessed frequently or at high-speed. This area is also utilized by the microcontroller as a storage area for the operating stack.

10. INTERNAL RAM ORGANIZATION

1F

Bank 3

18 17

R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 2F R7 R6 R5 R4 R3 R2 R1

7F

Bank 2

10

0F

Bank 1

7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07

78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
30

08

R0 R7 R6 R5 R4 R3 R2 R1 20 R0

07

Bank 0

00

. The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by user variables that need to be accessed frequently or at high-speed. This area is also utilized by the microcontroller as a storage area for the operating stack. This fact severely limits the 8051s stack since, as illustrated in the memory map, the area reserved for the stack is only 80 bytes and usually it is less since these 80 bytes has to be shared between the stack and user variables. 11. REGISTER BANKS The 8051 use 8 "R" registers, which are used in many of its instructions. These "R" registers are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7). These registers are generally used to assist in manipulating values and moving data from one memory location to another. For example, to add the value of R4 to the Accumulator, we would execute the following instruction: ADD A, R4 Thus if the Accumulator (A) contained the value 3 and R4 contained the value 3, the Accumulator would contain the value 6 after this instruction was executed. However, as the memory map shows, the "R" Register R4 is really part of Internal RAM. Specifically, R4 is address 04h. Thus the above instruction accomplishes the same thing as the following operation: ADD A, 04h This instruction adds the value found in Internal RAM address 04h to the value of the Accumulator, leaving the result in the Accumulator. Since R4 is really Internal RAM 04h, the above instruction effectively accomplished the same thing.

But watch out! As the memory map shows, the 8051 has four distinct register banks. When the 8051 is first booted up, register bank 0 (addresses 00h through 07h) is used by default. However, your program may instruct the 8051 to use one of the alternate register banks; i.e., register banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address 04h. For example, if your program instructs the 8051 to use register bank 3, "R" register R4 will now be synonymous with Internal RAM address 1Ch. The concept of register banks adds a great level of flexibility to the 8051, especially when dealing with interrupts (we'll talk about interrupts later). However, always remember that the register banks really reside in the first 32 bytes of Internal RAM. Register banks can be selected with the help of RS0, RS1 bits in the program status word (PSW). If you only use the first register bank (i.e. bank 0), you may use Internal RAM locations 08h through 1Fh for your own use. But if you plan to use register banks 1, 2, or 3, be very careful about using addresses below 20h as you may end up overwriting the value of your "R" registers! 12. THIRTY-TWO INPUT / OUTPUT PINS All four ports in the 8051 are bi-directional each contains a latch, an output driver and input buffer. The output drivers of port0 and 2, and the input buffers of port 0 are used in access to external memory. In this application port 0 is used as a lower byte of the external memory address multiplexed with data bus and port 2 is used as a higher byte of the external memory address when address is sixteen bit wide. Otherwise it can be used as general purpose I/O P0 (Port 0, SFR Address 80h, Bit-Addressable) : This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0 i.e. pin number 39 in microcontroller bit 7 is pin P0.7 i.e., pin number 32 in the IC. Writing a value of 1 to a bit of this SFR will

send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. While the 8051 has four I/O port (P0, P1, P2, and P3), if your hardware uses external RAM or external code memory (i.e., your program is stored in an external ROM or EPROM chip or if you are using external RAM chips) or if your hardware consists of any peripheral interface like ADC or DAC, you may not use P0 and P2). This is because the 8051 use ports P0 and P2 to address the external memory. Thus if you are using external RAM or code memory or peripheral interface you may only use ports P1 and P3 for your own use. P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0 i.e., pin number 1 bit 7 is pin P1.7 i.e., pin number 8. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 2 is pin P2.0 i.e., pin number 21, bit 7 is pin P2.7 i.e., pin number 28. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will being it to a low level. While the 8051 has four I/O port (P0, P1, P2 and P3), if your hardware uses external RAM or external code memory (i.e., your program is stored in an external ROM or EPROM chip or if you are using external RAM chips) you may not use P0 or P2. This is because the 8051 uses ports P0 and P2 to address the external memory. Thus if you are using external RAM or code memory you may only use ports P1 and P3 for your own use.

P3 (Port 3, Address B0h, Bit Addressable): This is input/output port 3. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 3 is pin P3.0 i.e., pin number 10, bit 7 is pin P3.7 i.e., pin number 17. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. While the 8051 has four I/O port (P0, P1, P2 and P3), if your hardware uses external RAM or external code memory (i.e., your program is stored in an external ROM or EPROM chip or if you are using external RAM chips) you may not use P0 or P2 and p3.6, p3.7. This is because the 8051 uses ports P0 and P2 to address the external memory and P3.6 and P3.7 for write and read operations. Thus if you are using external RAM or code memory you may only use ports P1 and P3 for your own use. Port 3 can also used for timer/counter, interrupts, serial ports also. P3.0 is also used for serial data reception, P3.1 is for serial data transmission, P3.2 & P3.3 is for external interrupts, P3.4 & P3.5 is for timer0 and timer1 respectively. P3.6&P3.7 for write and read operations respectively. 13. TWO 16-BIT TIMER / COUNTER Many microcontroller applications require the counting of external events, such as the frequency of a pulse train, or the generation or precise internal time delays between computer actions. Both of these tasks can be accomplished using software techniques, but software loops for counting or timing keep the processor occupied so that other, perhaps more important, functions are not done. To relieve the processor of this burden, two 16-bit up counters, named T0 and T1, are provided for the general use of the programmer. Each counter may be programmed to count internal clock pulses, acting as a timer, or programmed to count external pulses as a counter.

The counters are divided into two-8 bit registers called the timer low (TL0, TL1) and high (TH0, TH1) bytes. All counter action is controlled by bit states in the timer mode control register (TMOD), the timer/counter control register (TCON), and certain program instructions.

14. FULL DUPLEX SERIAL DATA RECEIVER/TRANSMITTER Computers must be able to communicate with other computers in modern multiprocessor distributed systems. One cost-effective way to communication is to send and receive data bits serially. The 8051 has a serial data communication circuit that uses register SBUF to hold data. Register SCON controls data communication, register PCON controls data rates, and pins RXD (P3.0) and TXD (P3.1) connect to the serial data network. SBUF is physically two registers. One is write only and is used to hold data to be transmitted out of the 8051 via TXD. The other is read only and holds received data from external sources via RXD. Both mutually exclusive registers use address 99h.

There are four programmable modes for serial data communication that are chosen by setting the SMX bits in SCON. Baud rates are determined by the mode chose. We will discuss about serial port later. 15. INTERRUPTS An interrupt is a special feature, which allows the 8051 to provide the illusion of "multi-tasking," although in reality the 8051 is only doing one thing at a time. The word "interrupt" can often be substituted with the word "event."

An interrupt is triggered whenever a corresponding event occurs. When the event occurs, the 8051 temporarily puts "on hold" the normal execution of the program and executes a special section of code referred to as an interrupt handler. The interrupt handler performs whatever special functions are required to handle the event and then returns control to the 8051 at which point program execution continues as if it had never been interrupted.

The topic of interrupts is somewhat tricky and very important. For that reason, an entire chapter will be dedicated to the topic. For now, suffice it to say that Interrupts can cause program flow to change. A computer program has only two ways to determine the conditions that exist in internal external circuits. One method uses software instructions that jump to subroutines on the states of flags and port pins. The second method responds to hardware signals, called interrupts that force the program to call a subroutine. Software techniques use up processor time that could be devoted to other tasks; interrupts take processor time only when action by the program is needed. Most applications of microcontrollers involve responding to events quickly enough to control the environment that generates the events (generically termed real-time programming). Interrupts are often the only way in which real-time programming can be done successfully. Interrupts may be generated by internal chip operations or provided by external sources. Any interrupt can cause the 8051 to perform a hardware call to an interrupt, handling subroutine that is located at a predetermined (by the 8051 designers) absolute address in program memory.

Five interrupts are provided in the 8051. Three of these are generated automatically by internal operations: Timer flag 0, Timer flag 1, and the serial port interrupt (RI or TI). Two interrupts are triggered by external signals provided by circuitry that is connected to pins INT0 and INT1 (port pins P3.2 and P3.3). After the Interrupt has been handled by the interrupt subroutine, which is placed by the programmer at the interrupt location in program memory, the interrupt program must resume operation at the instruction where the interrupt took place. Program resumption is done by storing the interrupted PC address on the stack in RAM before changing the PC to the interrupt address in ROM. The PC address will be restored from the stack after an RETI instruction is executed at the end of the interrupt subroutine.

16. OSCILLATOR AND CLOCK CIRCUITS The heart of the 8051 is the circuitry that generates the clock pulse by which all internal operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting a resonant network to form an oscillator. Typically, a quartz crystal and capacitors are employed, as shown in Figure 3.7 the crystal frequency is the basic internal clock frequency of the microcontroller. The manufactures make available 8051 designs that can run at specified maximum and minimum frequencies, typically 1 megahertz to 24 megahertz. Minimum frequencies imply that some internal memories are dynamic and must always operate above a minimum frequency or data will be lost.

Serial data communication needs often state the frequency of the oscillator because of the requirement that internal counters must divide the basic clock frequency is not divisible without a remainder, and then the resulting communication frequency is not standard.

C2 XTAL 2

C1 XTAL 1

GND Oscillator Circuit Ceramic resonators may be used as low-cost alternative to crystal resonators. However, decreases in frequency stability data accuracy make the ceramic resonator a poor choice if high-speed serial data communication with the systems, or critical timing, is to be done. The oscillator formed by the crystal, capacitors, and an on-chip inverter microcontroller, called the pulse, P, time. The smallest interval of time to accomplish any simple instruction, or part of a complex instruction, however, is the machine cycle. The machine cycle is itself made up of six states. A state is the basic time interval for discrete operations of the microcontroller such as fetching an opcode byte, decoding an opcode, executing an opcode, or writing a data byte. Two oscillator pulses define each state. Program instructions may require one, two, or four machine cycles to the executed, depending on the type of instruction. Instructions are fetched and executed by the microcontroller automatically, beginning with the instruction

located by the microcontroller automatically; beginning with the instruction located at ROM memory address 0000h at the time the microcontroller is first reset. To calculate the time any particular instruction will take to be executed, find the number of cycles, C, The time to execute that instruction is then found by multiplying C by 12 and dividing the product by the crystal frequency:

C x 12 T inst = -------------------------------------------Crystal frequency

For example, if the crystal frequency is 16 megahertz, then the time to execute an ADD A, R1 one-cycle instructions is .75 microseconds. A 12-megahertz crystal yields the convenient time of 1 microsecond per cycle. An 11.0592-megahertz crystal, although seemingly an odd value, yields a cycle frequency of 921.6 kilohertz, which can be divided evenly by the standard communication baud rates of 19200, 9600, 4800, 2400, 1200, and 300 hertz.

Oscillator frequency (f)

P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

State 1

State 2

State 3

State 4

State 5

State 6

One machine cycle

Address Latch Enable (ALE)

8051 Timing

ALE PULSE PER MACHINE CYCLE

There are two ALE pulse per machine cycle. The ALE pulse, which is primarily used as a timing pulse for external memory access, indicates when every instruction byte is fetched.

Two bytes of a single instruction may thus be fetched, and executed, in one machine cycle. Single byte instructions are nor executed in a half cycle, however, Single-byte instructions "throw-away" the second byte (which is the first byte of the next instruction.)