VHDL Programming PDF

Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon

Padmabhooshan Vasantraodada Patil Institute of Technology,
Budhgaon-416304

LAB MANUAL

Prepared by
Mr. A. B. Shinde
Assistant Professor,
Electronics Engineering,
abshinde.eln@pvpitsangli.edu.in
Department of Electronics Engineering
2013-14



------Half Adder (Behavioral)------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ha_adder is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end ha_adder;

architecture Behavioral of ha_adder is

begin
s<= a xor b;
c<= a and b;

end Behavioral

Entity Level Diagram

Architectural Level Diagram



XOR Gate

Device utilization Summary:
---------------------------

Number of Slices: 1 out of 1200 0%
Number of 4 input LUTs: 2 out of 2400 0%
Number of bonded IOBs: 4 out of 96 4%

Simulation Waveform



-------Full Adder (Structural)------
library IEEE;

entity f_adder is
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic);
end f_adder;

architecture structural of f_adder is
signal s1, c1, c2: std_logic;
component ha_adder is
b : in std_logic;
s : out std_logic;
c : out std_logic);
end component;
begin
u1: ha_adder port map(a, b, s1, c1);
u2: ha_adder port map(s1, cin, sum, c2);
carry<= c1 or c2;
end structural;





Device utilization summary:
---------------------------


Simulation Waveform



-------4 bit Full Adder (Structural)------
library IEEE;

entity adder_4bit is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
Sum : out std_logic_vector(3 downto 0);
Cy : out std_logic);
end adder_4bit;

architecture Behavioral of adder_4bit is
component f_adder is
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic);
end component;
signal c1, c2, c3:std_logic;
begin

u1:f_adder port map(a=>a(0),
b=>b(0),
cin=>cin,
sum=>Sum(0),
carry=>c1);
b=>b(1),
cin=>c1,
sum=>Sum(1),
carry=>c2);
b=>b(2),
cin=>c2,
sum=>Sum(2),
carry=>c3);
b=>b(3),
cin=>c3,
sum=>Sum(3),
carry=>Cy);
end Behavioral;





---------------------------


Simulation Waveform



-------16 bit Full Adder (Structural)------
library IEEE;

entity adder_16bit is
Port ( x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
pre_carry : in std_logic;
Carry : out std_logic);
end adder_16bit;

architecture Behavioral of adder_16bit is
component adder_4bit is
cin : in std_logic;
end component;
signal c1,c2,c3:std_logic;
begin
u1:adder_4bit port map(a=>x(3 downto 0),
b=>y(3 downto 0),
cin=>pre_carry,
Sum=>Sum(3 downto 0),
Cy=>c1);
b=>y(7 downto 4),
cin=>c1,
Cy=>c2);
b=>y(11 downto 8),
cin=>c2,
Cy=>c3);
b=>y(15 downto 12),
cin=>c3,
Cy=>Carry);
end Behavioral;





---------------------------


Simulation Waveform



-------4bit Magnitude Comparator (Structural)------
library IEEE;

entity comp_4bit is
altb : out std_logic;
aeqb : out std_logic;
agtb : out std_logic);
end comp_4bit;

architecture comp_arch of comp_4bit is

component adder_4bit is
cin : in std_logic;
end component;

component xnor_4 is
port (s: in std_logic_vector(3 downto 0);
t: in std_logic_vector(3 downto 0);
v: out std_logic_vector(3 downto 0));
end component;

component and_4 is
port ( p,q,r,s:in std_logic;
y:out std_logic);
end component;

component not_4 is
port ( i:in std_logic_vector(3 downto 0);
j:out std_logic_vector(3 downto 0));
end component;
signal s1,s2,s3,s5,s6:std_logic_vector(3 downto 0);
signal s4:std_logic:='0';
begin

u1: adder_4bit port map ( a=>s1,
b=>b,
cin=>s4,
Sum=>s5,
Cy=>altb);
u2: adder_4bit port map ( a=>s2,
b=>a,
cin=>s4,
Sum=>s6,
Cy=>agtb);
u3: xnor_4 port map ( s=>a,
t=>b,
v=>s3);



u4: and_4 port map ( p=>s3(3),
q=>s3(2),
r=>s3(1),
s=>s3(0),
y=>aeqb);
u5: not_4 port map ( i=>a,
j=>s1);
u6: not_4 port map ( i=>b,
j=>s2);

end comp_arch;





---------------------------


Simulation Waveform



-------BCD up-down Counter------
library IEEE;

entity coun_bcd_updn is
Port ( clk : in std_logic;
reset : in std_logic;
updn : in std_logic;
count : out std_logic_vector(3 downto 0));
end coun_bcd_updn;

architecture Behavioral of coun_bcd_updn is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if(reset='1')then
temp<="0000";
elsif(clk'event and clk='1')then
if (updn='1')then
if(temp=x"9")then
temp<=x"0";
else
temp<=temp+1;
end if;
else
if(temp=x"0")then
temp<=x"9";
else
temp<=temp-1;
end if;
end if;
end if;
end process;

count<=temp;

end Behavioral;





---------------------------

Number of Slice Flip Flops: 4 out of 2400 0%
Number of GCLKs: 1 out of 4 25%

Simulation Waveform



-------4bit Binary up-down Counter------
library IEEE;

entity counter_updn is
updn: in std_logic;
count : out std_logic_vector(3 downto 0));
end counter_updn;

architecture Behavioral of counter_updn is
begin
process(clk,reset)
begin
if(reset='1')then
temp<="0000";
elsif(clk'event and clk='1')then
if (updn='1')then
temp<=temp+1;
else
temp<=temp-1;
end if;
end if;
end process;

count<=temp;

end Behavioral;






---------------------------




Simulation Waveform



-------3:8 Decoder------

library IEEE;

entity deco_3_8 is
Port ( input : in std_logic_vector(2 downto 0);
en : in std_logic;
output : out std_logic_vector(7 downto 0));
end deco_3_8;

architecture Behavioral of deco_3_8 is
begin
process(input,en)
begin
if (en='0') then
output<=(others=>'0');
else
case input is
when "000" => output<="00000001";
when "001" => output<="00000010";
when "010" => output<="00000100";
when "011" => output<="00001000";
when "100" => output<="00010000";
when "101" => output<="00100000";
when "110" => output<="01000000";
when others => output<="10000000";
end case;
end if;
end process;

end Behavioral;





---------------------------


Simulation Waveform



-------5:32 Decoder (Structural)------
library IEEE;

entity deco_5_32 is
Port ( i : in std_logic_vector(4 downto 0);
En : in std_logic;
y : out std_logic_vector(31 downto 0));
end deco_5_32;

architecture dec_arch of deco_5_32 is

component deco_2_4 is
e : in std_logic;
end component;

component deco_3_8 is
Port ( input : in std_logic_vector(2 downto 0);
en : in std_logic;
output : out std_logic_vector(7 downto 0));
end component;
signal s : std_logic_vector(3 downto 0);
begin
u1: deco_2_4 port map (i=>i(4 downto 3),
e=>En,
y=>s);
u2: deco_3_8 port map (input=>i(2 downto 0),
en=>s(3),
output=>y(31 downto 24));
en=>s(2),
en=>s(1),
en=>s(0),
end dec_arch;





---------------------------




Simulation Waveform



-------Encoder (When____Else)------
library IEEE;

entity enco_8_3_when is
end enco_8_3_when;

architecture Behavioral of enco_8_3_when is
begin
y<="000" when i="00000001" else
"001" when i="00000010" else
"010" when i="00000100" else
"011" when i="00001000" else
"100" when i="00010000" else
"101" when i="00100000" else
"110" when i="01000000" else
"111" when i="10000000" else
"ZZZ";
end Behavioral;

-------Encoder (With____Select)------
library IEEE;

entity enco_8_3_with is
end enco_8_3_with;

architecture Behavioral of enco_8_3_with is
begin
with i select
y<= "000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when "10000000",
"ZZZ" when others;
end Behavioral;





---------------------------




Simulation Waveform



-------Priority Encoder------
library IEEE;

entity prio_enco is
end prio_enco;

architecture Behavioral of prio_enco is
begin
process(i)
begin
if (i(7)='1')then
y<="111";
elsif (i(6)='1')then
y<="110";
y<="101";
y<="100";
y<="011";
y<="010";
y<="001";
y<="000";
else
y<="ZZZ";
end if;
end process;

end Behavioral;





---------------------------


Simulation Waveform



-------Single Port RAM------
library IEEE;

entity ram_1p is
we : in std_logic;
addr : in std_logic_vector(4 downto 0);
dio : inout std_logic_vector(3 downto 0));
end ram_1p;

architecture Behavioral of ram_1p is
type ram_type is array (31 downto 0) of std_logic_vector(3
downto 0);
signal ram: ram_type;
begin
process (clk)
begin
if (clk'event and clk='1')then
if (we='1')then
ram(conv_integer(addr))<=dio;
else
dio<=ram(conv_integer(addr));
end if;
end if;
end process;

end Behavioral;





---------------------------


Simulation Waveform



-------Dual Port RAM------
library IEEE;

entity ram_2p is
we : in std_logic;
addr : in std_logic_vector(4 downto 0);
din : in std_logic_vector(3 downto 0);
spo : out std_logic_vector(3 downto 0);
dpo : out std_logic_vector(3 downto 0);
x : in std_logic);
end ram_2p;

architecture Behavioral of ram_2p is
type ram_type is array (31 downto 0) of std_logic_vector(3
downto 0);
signal ram:ram_type;
begin
process(clk)
begin
if(we='1')then
ram(conv_integer(addr))<=din;
end if;
end if;
end process;

process(clk)
begin
if (we='0')then
if(x='0')then
spo<=ram(conv_integer(addr));
else
dpo<=ram(conv_integer(addr));
end if;
end if;
end if;
end process;

end Behavioral;





---------------------------




Simulation Waveform



-------4:1 Multiplexer (CASE STATEMENT)------
library IEEE;

entity mux_4_1_case is
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_4_1_case;

architecture Behavioral of mux_4_1_case is
begin
process(a,b,c,d,s)
begin
case s is
when "00" => y<= a;
when "01" => y<= b;
when "10" => y<= c;
when others => y<= d;
end case;
end process;
end Behavioral;
-------4:1 Multiplexer (WHEN__ELSE STATEMENT)------
library IEEE;

entity mux_4_1_when_else is
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end mux_4_1_when_else;

architecture Behavioral of mux_4_1_when_else is

begin
y<= a when s="00" else
b when s="01" else
c when s="10" else
d;
end Behavioral;



-------4:1 Multiplexer (IF__ELSE STATEMENT)------
library IEEE;

entity mux_4_1_if is
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end mux_4_1_if;

architecture Behavioral of mux_4_1_if is
begin
process(s,a,b,c,d)
begin
if (s="00") then
y<=a;
elsif (s="01") then
y<=b;
elsif (s="10") then
y<=c;
else
y<=d;
end if;
end process;
end Behavioral;
-------4:1 Multiplexer (WITH___SELECT STATEMENT)------
library IEEE;

entity mux_4_1_with_select is
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end mux_4_1_with_select;

architecture Behavioral of mux_4_1_with_select is
begin
with s select
y<= a when "00",
b when "01",
c when "10",
d when others;
end Behavioral;





---------------------------


Simulation Waveform



-------8:1 Multiplexer------
library IEEE;

entity mux_8_1 is
y : out std_logic);
end mux_8_1;

architecture Behavioral of mux_8_1 is
begin
with s select
y<= i(0) when "000",
i(1) when "001",
i(2) when "010",
i(3) when "011",
i(4) when "100",
i(5) when "101",
i(6) when "110",
i(7) when others;
end Behavioral;





---------------------------


Simulation Waveform



-------Sequence Detector (Mealy 1011)------
library IEEE;

entity mealy_1011 is
x : in std_logic;
reset:in std_logic;
z : out std_logic);
end mealy_1011;

architecture Behavioral of mealy_1011 is
type state is (s0,s1,s2,s3);
signal current:state;
begin
process(clk,x)
begin
if (reset='1')then
current<=s0;
z<='0';
elsif (clk'event and clk='1')then
case current is
when s0 =>
if (x='1')then
current<=s1;
z<='0';
else
current<=s0;
z<='0';
end if;

when s1 =>
if (x='0')then
current<=s2;
z<='0';
else
current<=s1;
z<='0';
end if;

when s2 =>
if (x='1')then
current<=s3;
z<='0';
else
current<=s0;
z<='0';
end if;



when s3 =>
if (x='1')then
current<=s1;
z<='1';
else
current<=s2;
z<='0';
end if;

when others=>
null;
end case;
end if;
end process;
end Behavioral;






---------------------------


Simulation Waveform



-------Sequence Detector (Moore 1011)------
library IEEE;

entity moore_1011 is
x : in std_logic;
reset:in std_logic;
z : out std_logic);
end moore_1011;

architecture Behavioral of moore_1011 is
type state is (s0,s1,s2,s3,s4);
signal current:state;
begin
process(clk,x)
begin
if (reset='1')then
current<=s0;
elsif (clk'event and clk='1')then
case current is
when s0 =>
if (x='1')then
current<=s1;
else
current<=s0;
end if;

when s1 =>
if (x='0')then
current<=s2;
else
current<=s1;
end if;

when s2 =>
if (x='1')then
current<=s3;
else
current<=s0;
end if;

when s3 =>
if (x='1')then
current<=s4;
else
current<=s3;
end if;



when others=>
current<=s0;
end case;
end if;
end process;

z<='1' when current=s4 else
'0';

end Behavioral;






---------------------------


Simulation Waveform



-------Shift Register using Generate Statement------
library IEEE;

entity shift_generate is
Port ( sin : in std_logic;
clk : in std_logic;
sout : out std_logic);
end shift_generate;

architecture Behavioral of shift_generate is
component d_ff is
Port ( d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
begin
temp(0)<=sin;

sreg:for i in 0 to 3 generate
u:d_ff port map (d=>temp(i),
clk=>clk,
reset=>reset,
q=>temp(i+1));
end generate;

sout<=temp(4);
end Behavioral;





---------------------------


Simulation Waveform

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Digital System Design

Department of Electronics Engg., P.V.P.I.T., Budhgaon

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