Que: Explain with block diagram the steps involved in Post Layout Synthesis?

Ans: Synthesis: After performed functional design & verification of digital system the next stage in the design flow is Synthesis that is refinement of the functional design to a gate level netlist. Synthesis can be performed largely automatically using RTL synthesis tool. Any digital system consists of two parts i.e. Front end design and backend design. Post Layout Synthesis is related to backend design, which consists of floor planning, placement and routing technique. Post Layout Synthesis Final Floorplan Timing Driven Placement STA Clock Insertion Placement Based Optimization Gate-Level Simulation. Formal Verifications Delay Calculations Design Rule Check Timing Signoff Timing Drive Route Physical verification Tape out RC Extraction verification Physical Signoff

Functional Signoff Final ATPG Test Verification DFT Signoff

Figure1. Post Layout Synthesis

Floor plan Floor Plan involves describing where each of the blocks in the partition design is to be located on the chip. There are number of factors that make effects on the floor plan. Blocks that have large number of connections between them should be placed near each other. Since they reduces wire length and wiring congestions. Similarly blocks that are connected to external pins should be placed near the edge of the chip. It also involves the arrangement of power supply and ground pins and distribution of clock signal across the chips. EDA tools can assist by providing graphical tool, to help us to visualize floor plan and re arrange blocks ensuring all the time that a floor plan is feasible. Placement and routing Having determined floor plan for an ASIC we then proceed to placement and routing. This step involves partitioning each cell in a synthesized design and finding path for each connection. The main goals are to position all cells and route all the connections while minimizing area and delay of critical signals. During this process timing constraints are considered. Here clock insertion technique is used. Clock tree synthesis is used to check skew delay. The result of placement and routing is a suite of files to send to the chip foundry for fabrication. We can also generate detail timing information based on the actual positions of components and wires and use this in a more accurate simulation model of GATE level design. This detail timing simulations is a final check that our design meets its timing constraints. RC Extraction:

Figure2 Features available in RC.

As designs migrate to smaller geometries interconnect delays, constitute the larger portion of over all delays. Hence it is imperative that these delays are extracted and back annotated on the design. It is possible to extract both R&C for the design using RC extraction tools. The back annotation can be in the form of SDF (Standard Delay Format) or detailed standard parasitic format. After back annotation data is available, static timing analysis and gate level simulation are performed on the design to verify that the design stills mates the timing. The design simulated after layouts to ensure that timing is met with accurate interconnect delays from layout. Design rule Checking (DRC): Design rule check (DRC) is the area of Electronic Design Automation (EDA) that determines whether a particular chip layout satisfies series of recommended parameters called Design rules. Design rule checking is the major step during Physical verification of the design, which also involves LVS (Layout versus schematic) check, XOR checks, ERC (Electrical rule Check). The Basic DRC checks are Width, Spacing and enclosure. The main objective of the design rule checking (DRC) is to achieve a high overall yield and reliability for the design. Static Timing Analysis (STA): Once the gate level netlist has been generated the next step is to verify the timing of the design. STA is the technique used to verify timing characteristic of the design and used in synchronous circuit. The inputs to static timing analysis tool include the netlist library model of the cells in the technology library and constraints such as clock period, waveform, skews, false paths, input and output delays for block. Using this information STA tools calculates the delays through the combinational logic, the setup and hold up the resistors and identifies slack in all paths of the design Physical Verification This the design methodology task in physical verification. This involves using the refined design expressed as an interconnection of primitive circuit elements and generating the information required manufacture the circuit. Steps in the physical implementation are mapping, placement and routing. Mapping involves determining the particular circuit resources to be used for each of the components in the refined design. Placement and routing determines where each mapped components is to be positioned in the physical circuit and where inter connecting wires runs. Gate Level Simulation: Gate level simulation is used in the late design phase to increase the level of confidence about design implementation and to compliment verification results created by static methods.

Formal Verification As design increase in size and process technology shrinks conventional verifications techniques are fast spiraling out of controls. Equivalence checking (the most common form of formal verification) is a mathematical approach to verify equivalence of reference design and revised design. Verification is done without the need for test vectors. Thus it is faster than logic simulations. It performs only function equivalence checking and does not consider timing. Design for Testability (DFT): Here design is tested against the defects, faults, and failures. The main purpose of the test process, as it is apply to the manufacturing of semiconductor products, is to provide a measure of the quality or reliability of finished semiconductor product. The purpose of DFT is to place the hardware hooks on the die to enable the ability to conduct the quality reliability measurement. ATPG (Automatic Test Pattern generation) Test Verification: The ATPG process is the actual operation of the tool against the design description to generate the vectors sets needed to provide all the patter sets for the various different test modes and constraints. For e.g. A set of vectors may be generated with an on chip bus being in the read mode and another set of vectors may be generated with the bus with the write mode. Tape out: Since the physical wiring details have been determined, propagation delays through the wires can be included in the timing estimates, functionality of designs with no error and DFT with no error occurs, refined estimates are used to perform the final physical verification. Finally one or more files of the information are generated for manufacturing of circuit. When the step is passed, we reach a golden milestone called Tape out for ASIC design. And we get the final circuit.