BANNARI AMMAN INSTITUTE OF TECHNOLOGY

SATHYAMANGALAM

Department of ________EEE________________ Class Subject Code Subject Prepared By IV YEAR/7thSEM EEE 07E703 VLSI DESIGN Mr.N.SARAVANAKUMAR/Mrs.P.SRITHA

Time: 75 minutes Lesson. No [2]/[7] 1. Content List: Architectural design & Logical design, physical design. 2. 3. 4. 5. Skills Addressed: Reading,Questioning,Drawing Mindmap,Summarizing,Drawing Diagrams, Expressing orally and in writing Objectives: To acceralate the students to know about the Y-chart and the concepts ,steps involved in the various stages of VLSI design. Lesson Links: Concepts/ideas /formula/definition/laws about the layout designs. What is VLSI design Flow? What is Y chart? Alpha Breathing : (2 Mins) The three steps for alpha breathing are Breathe in Breathe out Hold (Repeat the three steps for 8 times) Evocation : (5 mins )

6.

7. 8.

Introduction:( 20-25 mins) Attached as power point presentation in Annexure I Brain Activation: (2 mins) Any one of the following activities like Right brain activities Solving puzzles Brain GYM Optical Illusions Perpetual calendar recalling Survey and Reading by students: (15-18 mins)
Sung-Mo Kang, Yusuf Leblechi CMOS Digital Integrated Circuits Analysis and design Page No:8-17

9. 10.

Discussion: ( 9 mins) The students will be asked to discuss the relevant topic among their team/other team/Faculty. The students those who have not taken part will be noted and kindle them to do.

11. 12. 13. 14. 15.

Mind Map: (5-7 mins) Refer Annexure-II Summary: (5 mins) Refer Annexure-III Gazing/Rote memory: (2 mins) A long and fixed look at the Mind map by the students before doing the presentation Assessment: Refer Annexure-IV Learning outcomes: By learning this topic the students will be able to understand design flow of VLSI design hierarchically

Annexure II Mind Map

Annexure III-Summary

System Specification

First step High level representation End results are Size Speed Power and Functionality of the VLSI system

Functional design

Main functional units of the system are identified Identifies the interconnect requirements between the units The area, power and other parameters of each unit are estimated Logic design

Circuit design

Develop a circuit representation based on the logic design net list

Packaging, Testing and Debugging

Include DRC (Design Rule Checking), circuit extraction More chip on a small area Making chip smaller
Physical design

Geometric representation. Exact details depends upon design rules

Fabrication In this process the fabrication process will be carried out

Annexure IV Assessment
1. In modern the MOSFET, the material used for the gate is: (a) High purity silicon

(b) High purity silica (C) Heavily doped polycrystalline silicon (d) Epitaxially grown silicon 2. (a) Increasing the channel dopant concentration (b) Reducing the channel dopant concentration (C) Reducing the gate oxide thickness (d) Reducing the Channel length 3. The advantages of SOI process (a) No well formation and latch up (b) Field inversion problems (c) Body effect (d) all of the above 4.Cmos is equal to (a) NMOS + PMOS (b) PMOS + PMOS (c) VMOS + NMOS (d) None of the above