National Institute of Electronics and Information Technology, Calicut

CDS/CA/7.5.1/F 40/R3

COURSEPROSPECTUS NameoftheGroup:VLSIDesignGroup NameoftheCourse:PGDiplomainVLSI&EmbeddedHardwareDesign CourseCode:VL500 StartingDate:19thAugust2013 Duration:24weeks PREAMBLE: VLSI (Very Large Scale Integration) has emerged as a very significant technology to provide tremendous quantum of processing power and functionality to modern electronic systems. Ubiquitous Computing, Communication and Embedded Systems,basedonVLSIarerevolutionizingeverywalksofourdailylives,beitConsumer Electronics,Communication,Computing,Automation,SpaceApplication,Defenseandto just about everything. With the advancements in silicon processing technologies for MEMS, NEMS and RF components, many of the formerly external components can now be integrated into a single SystemonChip which has resulted in a dramatic improvements in performance while achieving reduction in the size, cost and power consumption .Complexity in such systems arises not only from the diversity of the technologies,fromsensorsandactuatorsandRFfrontendstobasebandDSPsoftware, etc., that must be integrated onchip comprising of tens of millions of transistors, but also from the fact that such systems must be increasingly built from parts that have beendesignedseparatelyandusingdifferenttoolsandflows. OBJECTIVE OF THE COURSE: The PG Diploma in VLSI & Embedded Hardware Design is intended to impart training in designing complex embedded systems using reusable Intellectual Property (IP) Cores as building blocks and employing hierarchical design methods. Emphasis of the teaching curriculum is on design methodology and practical applications. The course contents have been designed keeping in view the emerging trendsinneedsforskilledmanpower. Thecurriculumhasbeendesignedinconsultationwithindustryandacademicexperts and our strategic partners, to map the skill sets and design methodologies, which is high in demand in VLSI & Embedded Systems industries. Our students have been successfully placed in reputed product companies and we enjoy the trust of many reputedcompanies,whohaveenteredintostrategicallianceswithus. OUTCOME OF THE COURSE: This course is frequently updated in synchronization with the industry to provide the trainees indepth knowledge and skills required by Embedded & VLSI markets around the globe. It provides comprehensive understanding aboutthefundamentalprinciples,methodologiesandindustrypractices. This uniquely hybrid course makes the successful participants readily employable in multiple roles available in broad spectrum of relevant industries. For people interested Page 1/10

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in entrepreneurships this would be an excellent launch pad. In addition the course also serves as a concrete platform for people involved in application research, consultancy andhighendproductdevelopmentinbothindustryandacademia. COURSE STRUCTURE: The VL500 contains nine modules. The students are required to doaprojectworkinanyoneofthemodularareas,foraperiodof8weekstobeeligible forissueofPGDiplomainVLSIDesign. VL500 ModuleName Duration VL501 VL502 VL503 VL504 VL505 VL506 VL507 VL508 VL509 AdvancedDigitalDesign VHDLLanguageandCodingforSynthesis VerilogLanguageandCodingforSynthesis CMOSLogicDesign EmbeddedControllerBasedProductDesign ProgrammableSoC FPGADesignMethodologyandPrototyping RTLVerification Project 3weeks 3weeks 3weeks 1week 2weeks 1week 2weeks 1week 8weeks

OTHERCONTENTS a. Course Fees: For SC/ST Category Applicants : Total Fee payable is Rs. 3,500.00/*(Allinclusive,singlepayment.*ConditionsApply). GeneralCategoryApplicants:TotalFeepayableisRs.76,410.00(allinclusive) andcanbepaidinlumpsumORinmaximumofthreeinstallmentsasgivenbelow

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PAYMENTSCHEDULEOFFEESIN03INSTALLMENTSBYGENERALCATEGORYSTUDENTS Installment Amount(Rs) DueDateandremarks No First 35,000.00 7thAugust2013 Due date for the students in the first selection list have to pay the first installment fee for taking provisional admission Second 25,000.00 19thAugust2013(TheDayofcounseling) The students in the additional selection list have to pay boththefirst&secondinstallmentsoffeetogetheronor beforethisdate Third 16410.00 28thSeptember2013 TotalFees 76,410.00(Allinclusive) b. ELIGIBILITY: M.E/M.Tech/BE/B.Tech in Electronics/ Electronics & Communication/ Electrical/ Instrumentation/Computer Science/IT or M.Sc (Electronics/CS). Diploma students may also be considered. Graduates with appropriateexperienceandfinalyearstudents#alsomayapply # Final year students have to include the copies of course completion certificate of their qualifying degree/ diploma or copies of the mark lists up to the last semester/ year. On the date of counseling/ admission, he/she must produce the originalsofcoursecompletioncertificate/marklistsuptothelastsemester/year examination. c. NUMBEROFSEATS:40 SC/STcandidatesandPersonswithdisabilitiesareeligibleforseatreservation andrelaxationintheminimummarksforeligibility. d. HOWTOAPPLY: Procedure for Online application: Students can apply online by filling up the online application form. The students are first required to obtain the DD for Rs.1000.00 towards advance deposit. The students are required to fill the details with regards to the DD/Journal Number, Date and amount. The students arerequestedtonotedowntheirregistrationnumberallottedafterpressingthe "Submit" button and forward the demand draft mentioning their name, their onlineregistrationnumberandcoursecode(i.e.;VL500),onthebacksideofthe DD. Online registrations not containing the advance deposit details will not be consideredforprocessing. Procedure for applying offline using the print copy of Application form: The students can download and print the application form from our web site and fill the particulars and forward the same to the Training Officer along with the requisitefee,asmentionedabove. Page 3/10

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Filled in application forms and Demand Draft (mention the name of the student, name ofthecourseappliedfor[ie;VL500:PGDiplomainVLSI&EmbeddedHardwareDesign] andcontactnumberonthebacksideoftheDD),shouldbesentto: TheTrainingOfficer NationalInstituteofElectronicsandInformationTechnologyCalicut P.B.No.5,NITCampus(Post) CALICUT,Kerala.PIN673601
The name of the course applied for (i.e. ; VL500: PG Diploma in VLSI & Embedded Hardware Design) should be super scribed on the top of the cover in which the application form is forwarded

MODEOFPAYMENT:(Any1of3optionsgivenbelowmaybeusedtopaythefees)

1 2 3

DemandDrafttobedrawninfavorofDirector,NIELIT,PayableatStateBankofIndia, CalicutNITBranch(2207).TheDDshouldreachherebeforethelastdatetoapply. Through any branch of SBI (where this format is accepted) using the pay in slip available in our web site (http://www.calicut.nielit.in/course/payinslip.pdf). The originalcounterfoilshouldreachherebeforethelastdatetoapply. The fees can be paid directly into our account from any bank where core banking facilityisavailable.Thedetailsrequiredfordirectpaymentareasgivenbelow. SavingsAccountNo: 31329537747 AccountName Director,NIELIT,Calicut BankName: SBI,NITChathamangalam BankCode: 2207 IFSCNo: SBIN0002207 MICR: 673002012 The depositor should obtain the UTR Number/Journal No from the branch while depositing cash directly into our account. Depositor should also obtain the counterfoil duly filled up and signed by the staff with seal of the bank through which the amount was deposited. The following details should reach here before the last date to apply, viaemailtotrng@calicut.nielit.inwithcctonanda@calicut.nielit.in 1. 2. 3. 4. 5. 6. 7. NameoftheDepositor NameoftheStudent DateofPayment AmountDeposited NameofBank/branchthroughwhichamountdeposited PurposeCourseID(VL500)AdvanceDeposit/InstallmentFeeetc. ProofofDeposit(counterfoil/acknowledgementinoriginal) Page 4/10

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8. UTR/JournalNumber The counterfoil in original carrying the UTR/Journal Number issued by the bank must beproducedbytheapplicantonthedayofcounselingtoouraccountsdepartmentfor reconciliationandthereceiptissuedbytheaccountsdepartmentmustbekeptsafe. The Institute will not be responsible for any mistakes done by either the bank concernedorbythedepositorwhileremittingtheamountintoouraccount.

e. SELECTIONOFCANDIDATES:Candidateswillbeselectedbasedontheirmarksin their qualifying examination subject to eligibility and availability of seats. Selection of candidates who have completed the course but expecting the results shall be based on the availability of seats. All selected candidates shall be intimated of their selection by email alone. The list of selected candidates shall bepublishedinourwebsite Theadmissiontothecourseshallbebasedonthefollowingcriteria: 1. Shouldhavepassedtheeligibilitycriteriaasmentionedabove. Selectionlistofstudentswillbepreparedandpublishedinourwebsiteasfollows. First selection list will be prepared based on the applications received on or before 25thJuly2013. Additional selection list will be prepared based on the applications received on or before 07th August 2013 and excluding the applicants, included in the first selection list. f. TEST/INTERVIEW(IFAPPLICABLE):NotApplicable g. COUNSELING/ADMISSION:19thAugust2013 h. ADMISSIONPROCEDURE: Students who have been selected for counseling/admission are required to reporttoNIELITontheprescribeddayby9:30hrsalongwiththefollowing 1.AttestedCopiesofProofofAge,Qualifications,etc 2.OriginalCertificatesoftheabove 3. Two copies of passport size photographs and one stamp size photograph for identitycard. 4.SC/STCertificateinEnglish/Hindionly(ifapplicable) 5.IncomeCertificateinEnglish/Hindionly(ifapplicable) 6. Proof of Payment(s) made (counterfoils in original containing the UTR/Journal Number,dulystampedbythebankstaff)

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The students on reaching the NIELIT are required to meet the Front Office Councilor (FOC). The FOC then directs the student to the Course Coordinator. The student gets the enrollment form verified by the Course Coordinator and then meets the FOC who shall direct the student to the Accounts section for paymentoffees.Astudentisthusadmitted. i. DISCONTINUING THE COURSE: No fees under any circumstances shall be refunded in the event of a student discontinuing the course. A student can however, be eligible for module certificates (applicable only for courses which provide for modular admission) which he has successfully completed provided hehaspaidtheentirecoursefees. j. COURSE TIMINGS: The classes and labs are from 9.30 am to 12.30 pm and 1.45 pmto5.00pmMondaytoFriday. k. LOCATIONANDHOWTOREACH: NIELIT Calicut is located very near to NIT (REC)campus and is about 22Kms from the Calicut (Kozhikode) city. A number of buses [Buses to NIT via Kunnamangalam] are available from "Palayam Bus Stand or KSRTC Bus Stand". Our stop is called "CEDT/Pandrandu" & is one stop before NIT. The bus fare is Rs.15/fromCalicutCitytoNIELITanditisontherightsideoftheroad. Calicut (Kozhikode) is well connected by Rail, Road and Air form different parts of the country. The climatic conditions in Calicut are perhaps one of the best in India throughout the year. The maximum and minimum temperatures range between35and20oC.Thecoolbreezefurtheraddstothecomfort.

l. COURSEENQUIRIES:

Students can enquire about the various courses either on telephone or by personal contact between 9.15 A.M. to 5.15 P.M. (Lunch time 1.00 pm to 1.30 pm). ContactDetails VL500CourseCoordinator 9995427802/04952287266.Extn:244 CourseCoordinatorsemail nanda@calicut.nielit.in TrainingOfficer 04952287266/2287268 TrainingOfficersEmail: trng@calicut.nielit.in OfficeFax 04952287168 Page 6/10

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m. IMPORTANTDATES Last date for receiving applicationforms completed First selection list will be prepared based on the applications received on orbefore25thJuly2013. The additional selection list will be prepared based on the applications receivedonorbefore7thAugust2013, andexcludingtheapplicants,included inthefirstselectionlist. Publication of first selection list in the 26thJuly2013. Websitehttp://www.calicut.nielit.in/ th Last date for taking provisional admission 7 August2013 by paying the first installment of fees, for applicantsinthefirstselectionlist Publication of additional selection list in 08thAugust2013 ourwebsite(iftherearevacantseats) Counselingdate 19thAugust2013 ClassCommencementdate 20thAugust2013 Payment of first installment of fees for 7thAugust2013 applicantsinfirstselectionlist Payment of second installment fees for Onorbefore19thAugust2013 applicantsinfirstselectionlist Paymentofthirdinstallmentfees Onorbefore28thSeptember2013.

n. PLACEMENT: We have a placement cell, which provides placement assistance to students who qualify our courses. Partial listofour paststudents, placed is given inthewebsite o. HOSTELFACILITIES: Hostel accommodation is available for boys and girls on daily or monthly chargeable basis. The hostel fee varies from Rs. 700.00 to Rs. 1300.00 (for boys) per month and Rs. 1000.00 to Rs.1400.00 (for Girls) per month depending on the location of accommodation. However, students are required to pay the hostel fees for the duration of the course for which they are seeking admission at the timeofjoiningthecourse.

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p. CANTEENFACILITIES: The Institute has a canteen functioning at the main campus and food at reasonableratesisavailableforbreakfast,lunch,anddinner. q. LABFACILITIES Altera&XilinxDevelopmentBoards&TrainerKits XilinxISE,AlteraQuartusII,NIOSIITrainerKits ASICDesign&VerificationtoolsfromSynopsys CompleterangeofSimulation,SynthesisToolsfromMentorGraphics FPGADesignandVerificationTools ASICDesignVerificationTools&HardwareSoftwareCoverificationTools ICNanometerDesignTools(Backendtools)&SystemModelingTools DigitalStorage&MixedSignalOscilloscopes, LogicAnalyzer&SMDReworkstation r. COURSECONTENTS: 1.AdvancedDigitalDesign a. CombinationalCircuitDesign b. SequentialCircuitDesign c. DesignofcontrollerandDatapathunits d. StateMachines e. ControllerDesignusingFSMs&ASMs f. DesignExamples&CaseStudies 2.VHDLLanguageandCodingforSynthesis a. LanguageConstructs,Datatypes b. DesignStyles c. BehavioralModeling,DataflowModeling d. StructuralModeling e. GenericsandConfigurations f. Subprogramsandoverloading g. PackagesandLibraries h. AdvancedfeaturesofVHDL i. TestBenchDesignandCoding j. Synthesisissues k. MiniProjectandCaseStudies 3.VerilogLanguageandCodingforSynthesis a. IntroductiontoVerilogHDL&HierarchicalModelingConcepts b. LexicalConventions&DataTypes Page 8/10

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c. SystemTasks&CompilerDirectives d. Modules,PortsandModuleInstantiationMethods e. GateLevelModeling f. DataflowModeling g. BehavioralModeling h. RTLDesignandLogicSynthesisandSynthesisissues i. DesignVerificationusingTestbenches j. MiniprojectandCaseStudies 4.CMOSLogicDesign a. MOSFundamentals b. MOSSwitches&Designs c. TransmissionGates d. InverterDC,ACCharacteristics e. CombinationalandSequentialLogic f. IntroductiontoLayoutTools 5.EmbeddedControllerBasedProductDesign a. Introduction:QualityConcepts, b. ProductDevelopmentProcess&IndustrialDesign c. BasicElectronics,Test&MeasurementEquipments d. PCBDesignandEMCGuidelines e. 8051Architecture f. CProgrammingBasics&EmbeddedC g. DevelopingprogramsforEmbeddedProducts h. DebuggingTools i. PeripheralInterfacing:ADC,LCD,SerialPort,LEDs/Relays,Buzzer j. CaseStudy k. DesignSyndicate 6.ProgrammableSoC a. IntroductiontoProgrammableSoC b. PSoCDesignersIDE c. DesignexamplesusingPSoCs 7.FPGADesignMethodologyandPrototyping a. IntroductiontoProgrammableLogicandFPGAs b. PopularCPLD&FPGAFamilies c. ArchitectureofpopularXilinxandAlteraFPGAs d. FPGADesignFlowAlteraQuartusII e. FPGADesignFlowXilinxISE f. ImplementationDetails. Page 9/10

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g. AdvancedFPGADesigntips h. LogicSynthesisforFPGA i. Placement&Routing j. StaticTimingAnalysis k. DesignproblemsusingXilinxPlatforms l. DesignproblemsusingAlteraPlatforms m. CaseStudiesonFPGABasedimplementations n. IPReuseMethodology o. SoftIPvsHardIP p. IPDesignProcess&SystemIntegrationwithreusableIP 8.RTLVerification a. FunctionalVerificationConcepts b. Simulators,CoverageandMetrics c. IntroductiontoVerificationMethodologies d. TestingstrategyDirectedandrandomTesting e. TestCasesVsTestBenches f. VerificationComponents(Drivers,Checkers,Monitors, Scoreboardsetc) g. CasestudyofaVerificationIP 9.Project Thefollowingtextsdonotformpartoftheprospectus: ThisapprovalisvalidforuploadingtoNIELIT,Calicutwebsiteaswell. SignatureoftheCourseCoordinator: SignatureofTrainingOfficer: Approved/NotApproved Director
Guidelines: 1.AllTextinItalicsaretobeenteredbythecoursecoordinator 2.TheCourseProspectustobeputtoDirectorforapprovalthroughTrainingOfficerbefore issue.

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