Analogue Electronics Op-Amp Circuits Analysis

Author: Assist. Prof.
Poenar Daniel Puiu
T1
Analogue Electronics (E2002)
-Additions to TUTORIALSAssist. Prof. Poenar Daniel Puiu Office: S2.2-B2-06 Tel.: 6790 4237 E-mail: epdpuiu@ntu.edu.sg
Author: Assist. Prof. Poenar Daniel Puiu Recapitulation:

BASIC EQUATIONS TO SOLVE ELECTRICAL CIRCUITS = KIRCHOFFs LAWS:
T1
Ii = 0
i =1
E = V + R I
i =1 i i =1 i i =1
i i
I2 I1 In I3
I3
E1
R3
V1 I1 R4 R1
R2 E2
I2
Ii
I4
I2
Tutorial 2: Op-Amps (2)
T2
2.1. An inverting amplifier with a gain of 10 is made from a non-ideal op-amp having an input offset voltage of 1 mV. A sinusoidal input voltage of 0.1 mV peak amplitude is applied. What are the resulting A.C. and D.C. components of the output voltage? Lets draw the circuit so that we can model the input offset Solution: voltage as follows: R1 R2 We are given that A= 10 => R2 = 10. Assume that the v OUT vIN R1 (0.1mVp) op-amp operates in the linear sinusoid region. Then using the linear vIO superposition principle we 1 mV have: (Consider first only vIN and passivate vIO):
R2 ( vOUT )1 = A vIN = v peak sin t = ( 10 ) 0.1sin t = 1 sin t [mV ] R1

Assist.Prof. Poenar Daniel Puiu
1
T2 (Consider first only vIO and passivate vIN => non-inverting amplifier):
Hence:
R2 ( vOUT )2 = Anoninv vIO = 1 + vIO = 11[mV ] R1 2 vOUT = ( vOUT )i = 11 sin t [mV ]

i =1
The (qualitative) graphical representation of the output signal is:
vOUT 11 mV 1 mV time t
T2 2.2. A difference amplifier with a gain of 2 is made from an opamp with the following parameters: VIO= 2 mV maximum; IBIAS= 100 nA; IIO=0. If both inputs are set to zero, what is the maximum expected offset value of vOUT?
Solution:
v1 v2 R1 R3 R4
First, lets remember what is the difference amplifier: Its output voltage is given by: R2 vOUT
vOUT
vOUT
R2 = ( v2 v1 ) and in many practical situations R3=R1 and R4=R2. R1 In our case the gain is 2 => R2= 2 R1.
and the condition to reject common-mode signals (i.e. to have vOUT=0 when v1=v2) is R2/R1=R4/R3 which leads to:
R2 1+ R2 R1 = v1 + v2 R3 R1 1+ R4
T2 Lets re-draw the circuit such that we can calculate the effect of the opamps non-idealities (input offset voltage & input currents). In order to do this we must set to zero other input (signal) sources, as follows: R3 v1=0 R4 VIO 2 mV
I+ I
vOUT
R1 v2=0
R2
Again, using the linear superposition principle we have:

4
T2 Consider first only VIO and passivate I+ and I , i.e. make I+=I=0:
R2 ( vOUT )1 = Anoninv VIO = 1 + VIO R1
Consider only I+ and passivate VIO and I:
( vOUT )2 = ( R3 || R4 ) I + Anoninv
R1R2 R2 = I + 1 + = R2 I + R1 + R2 R1
because R3=R1 and R4=R2. Consider only I and passivate VIO and I+: ( vOUT )3 = R2 I (the common ends of R1 & R2 are at the same virtual potential as the noninverting input of the op-amp, which is connected to GND) Hence: vOUT =
(v )
i =1
OUT i
R2 = 1 + VIO + R2 ( I I + ) and it was given R1

5
that IIO=0; since IIO= I+ I =0 => I+ = I => vOUT= 3VIO = 6 mV.

T2 2.3. An op-amp is connected in the non-inverting amplifier configuration. A voltage source of value vS is connected via a series resistance RS to the v+ terminal. a) Find an expression for vOUT as a function of vS if the op-amp is ideal. b) If the op-amp is non-ideal and has input bias currents I+ and I and input offset voltage VIO, find an expression for vOUT when vS=0. c) Combine the answers to parts (a) and (b) to find the total output when vS is nonzero. d) The feedback resistors in the amplifier are set to 25 k and 100 k, so that the amplifier has a gain of 5. If IBIAS = (I++I)/2= 100 nA, IIO= 40 nA, and VIO= 2 mV, what value of RS will minimize the total D.C. offset component to vOUT? Solution: Again, first lets remember what is the non-inverting amplifier and lets re-draw it for the specific case of this problem:
6
T2 R1 vS RS R2 vOUT a) The ideal gain is: Anoninv
R2 = 1+ R1
vS=0
RS
VIO
I+ I
(no voltage drop across RS since the opamp is considered ideal, i.e. I+=I=0) b) If the op-amp is non-ideal, we need to re-draw the circuit such that we can calculate the effect of the op-amps non-idealities (input offset voltage & input currents). vOUT In order to do this we must set to zero the signal input source.
7
R1
R2
T2 Again, using the linear superposition principle we have: Consider first only VIO and passivate I+ and I , i.e. make I+=I=0:
Consider only I+ and passivate VIO and I:
R2 ( vOUT )1 = Anoninv VIO = 1 + VIO R1
R2 ( vOUT )2 = ( RS I + ) Anoninv = 1 + RS I + R1 Consider only I and passivate VIO and I+: ( vOUT )3 = R2 I
Hence: vOUT =
(v )
i =1
OUT i
R2 R2 = 1 + VIO + R2 I I + RS 1 + R1 R1
c) When vS0, the total output becomes
vOUT
R2 = 1 + ( vS + VIO I + RS ) + R2 I R1
8
T2 d) Since the ideal gain is Anoninv
We are also given that IBIAS= 100 nA, IIO= 40 nA, that is:
R2 = 1+ = 5 R2= 100 k, R1= 25 k. R1
I+ + I I BIAS = = 100 nA 2 I+= 80 nA and I= 120 nA. We are also given that VIO= 2 mV. The D.C. I IO = I + I = 40 nA
( vOUT ) D.C . = Anoninv (VIO I + RS ) + R2 I
component of the previously deduced output voltage is:
We must set (vOUT)D.C.=0 and solve the equation to find the corresponding RS solution. Making the necessary calculations one obtains:
AnoninvVIO + R2 I 5 2 mV + 100 k 0.12 A 22 RS = = = = 55 k Anoninv I + 5 0.08 A 0.4
(V/A = => V/mA =k => mV/A =k)

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T2 2.4. An op-amp is connected in the inverting amplifier configuration. The gain of the amplifier is set to 50 by using 100 k and 2 k resistors in the feedback circuit. A 2 k resistor is used to connect the v+ terminal to ground. The opamp is non-ideal and has parameters IBIAS= 10 mA; IIO=0, VIO= +10 mV, and slew rate SR= 1 V/s. Find the D.C. offset component to the output voltage caused by the non-ideal R2 parameters. R2 Solution: We are given that A= 50 => = 50 R1 Since IIO=0 => I+=I , then a resistor 100 k v vIN R1 OUT with a resistance value R =R ||R will 2 k 3 1 2 precisely cancel the effect of IBIAS. In R3 this case R1||R2 = 1.46 k R3= 2 k. Therefore, 2 k
vOUT
SR parameter is irrelevant to this calculation that deals with D.C. outputs.

R2 = 1 + VIO = 51 10 mV = 510 mV . Note that the R1
10
T2 2.5. A high-gain op-amp circuit is formed by cascading two inverting amplifiers in series. Both op-amps are connected to 15V power supplies. The first stage has a gain of 20. The cascade is to be designed so that the peak output voltage of the second stage comes no closer than 1 V to either power supply voltage. The cascade is built from non-ideal op-amps with VIO= 2 mV and IBIAS0, IIO=0. a) If both stages remain in the linear region, find an expression for the output voltage that includes the effect of VIO. Express the gain of each stage in terms of the ratio of its resistor values. (Stage 1 gain = R2/R1; stage 2 gain = R4/R3.) b) If vIN is a sinusoid of 25 mV peak magnitude, what is the maximum gain of the second stage if vOUT is to remain within the specified swing limits? Solution: The circuit including VIO in each op-amp is:
11
T2 a) Assume we have both VIO VCC (+15V) voltages to R4 R3 vS A1 have the same VCC polarity. Using v (+15V) OUT VIO (vOUT)1 the linear V EE A2 2 mV (15V) VEE superposition VIO (15V) principle we 2 mV obtain: R2 R2 R4 R4 ( vOUT )1 = vS + 1 + VIO and ( vOUT )2 = ( vOUT )1 + 1 + VIO R1 R1 R3 R3 R4 R2 R2 R4 vOUT = ( vOUT )2 = vS + 1 + VIO + 1 + VIO = R3 R1 R1 R3
R2 R4 R4 R4 R2 R2 R4 R4 R4 R2 R4 vS + 1 + 1 + VIO = vS + 1 + VIO R1R3 R3 R3 R1 R1R3 R3 R3 R1R3
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R1
R2
T2
vOUT
R2 R4 R2 R4 = vS + 1 VIO R1R3 R1R3
b) A positive VIO will result in a negative output offset IF R2R4R1R3. Thus, for a positive VIO a maximum negative excursion in vOUT will occur during the negative peak of vS. By setting the condition vOUT= 14 V (so that the peak output voltage of the second stage comes no closer than 1 V to either power supply voltage, as requested by the problem) when vS= 25 mV (i.e. maximal negative input), one can solve for the gain of stage 2, |A2|=R4/R3:
R2 R4 R2 R4 R4 R2 R2 vOUT = vS + 1 VIO = VIO + vS VIO R1R3 R1R3 R3 R1 R1 R4 vOUT VIO R4 14000 2 = = = 25.93 26 R3 R2 v V R3 20 ( 25 2 ) ( S IO ) R1 For the maximum positive input vS= 25 mV => vOUT= 12 V.
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T2 2.6. Consider the op-amp and amplifier circuit described in Probl. 2.4: a) If the input voltage is a 10 mV peak sinusoid, what is the maximum frequency that can be applied before the slew rate limitation is reached? b) Repeat part (a) for an input voltage that consists of a 10 mV peak triangular waveform. c) Sketch the output voltage versus time if the input is a 10 mV peak square wave. R2 Solution: a) The closed-loop gain for the circuit is: Ainv = = 50 R1 For vS= 0.01 sin t => vOUT= 0.5 sin t + (D.C. offset) => By setting this equal to SR we can find he required MAX:
dvOUT dvOUT = 0.5 cos t max = 0.5 dt dt

6
0.5MAX = SR MAX = 2 SR = 2 10 rad
f MAX 318 kHz

14
T2 b) For a triangular input signal, its slope can be easily deduced: vIN 2VP VP=10 mV Slope =
0 T/2 VP= 10 mV
Time t
4VP = T
Since the output is amplified by Ainv= 50 times, we need to set the condition
4VP 4VP SR 106 Ainv SR T Ainv f = = 500 kHz 2 T SR 4VP Ainv 4 10 50

c) For a 10 mV peak square wave, vOUT tends towards AinvvIN= 10 mV50= 0.5V peak level, but the rise and fall of the waveforms are limited by the slew rate of 1 V/s, as shown in the next Figure:
15
T2 vOUT VP=0.5 V 0 0.5 s T/2 Time t
1 s VP= 0.5 V 2.7. An op-amp is connected in the non-inverting amplifier configuration. A gain of 11 is achieved by using 500 k and 50 k resistors in the feedback circuit. The signal source connected to the v+ input has a 50 series Thevenin resistance. a) If the op-amp has an input bias current of 1 A calculate the D.C. value of vOUT when vIN=0. Assume IIO=0. b) Choose an additional resistor to be put in series with the input source so that D.C. offset found in part (a) is forced to zero.
16
T2
Solution:
a)
50 k R1 I+ I
500 k R2 vOUT 50 k R1 I+ RTH 50 I 500 k R2 vOUT
vIN
RTH 50
Assume IIO=0 => I+=I=IBIAS= 1 A. Then, when vIN=0 the circuit becomes: Therefore,
vOUT
R2 = ( I + RTH ) 1 + + I R2 = 1 A 50 11 + 1 A 500 103 = R1
= 0.55 mV + 500 mV= 499.45 mV. b) As IIO=0 then the required total resistance connected to the v+ terminal is R1 | | R2 = 45.45 k. Therefore, the additional resistor RS necessary to be added in series to the existing RTH should be RS= R1| |R2 RTH=45.4 k
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T2 2.8. An op-amp circuit with a D.C. gain of 400 is formed by cascading in series two inverting amplifiers with gains of 20. Both op-amps are connected to 15V power supplies and have slew rates of 1 V/s. a) If the input is a sinusoidal voltage, what peak magnitude drives the output to its full swing range if Vsat-pos= 14.3 & Vsat-neg= 14V? b) For the input voltage found in part (a), what is the maximum frequency in [Hz] that the input voltage can have before the slew rate limitation becomes important ? Solution: a) The overall closed-loop gain of the two stage cascaded op-amp circuit is: AVCL=(AVCL)1.(AVCL)2=(20)(20)= 400 => vOUT= 400 vIN , and we know that vOUT must be limited to 14 V => the input must be limited to vOUT MAX 14 = = 35 mV p v IN = AVCL 400
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T2 b) The largest signal will appear at the output of the second stage, hence only the 2nd op-amp will suffer from slew rate limitations. If vIN= VP sin t => vOUT= AVCL.VP sin t =>
dvOUT dvOUT = AVCLVP cos t max = AVCLVP SR dt dt 106 SR f = = 11368.21 11.4 kHz 3 2 AVCLVP 2 400 35 10
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Tutorial 3: Op-Amps (3)
T3
3.1- a) The op-amp in the Fig.3.1-A below has a unity-gain frequency of 1.2 MHz. i) What is the closed loop BW? ii) What is the closed-loop gain at 600 kHz ? R1 R2 Fig.3.1-A: 5 k vIN b) The op-amp shown in Fig.3.1-B has a SR of 4 V/S and a unity-gain frequency of 2 MHz. Determine whether the amplifier will distort or not the input signal shown. R2 vIN R1 20 k 5V vOUT Fig.3.1-B: 20 k vIN 2V 5 s Time t
1
95 k
vOUT
T3
Solution:
We also know that the 3 dB bandwidth is given by BWCL = f 3dB = f T which applied in this case gives the value f3dB= 0.051.2 MHz= 0.06 MHz = 60 kHz a-ii) At low frequencies ACL-DC= 1/ = 20. At 600 kHz. i.e. one decade beyond 60 kHz the gain will reduce with 20 dB = 10 times. Thus, Note that ACLf3dB= fT =1.2 MHz
a-i) We know that the unity-gain freq. is fT= 1.2 MHz. We can easily calculate the feedback factor (feedback factor) : R1 5 = = = 0.05 R1 + R2 5 + 95
vOUT ACL DC 20 = =2 ACL ( 600 kHz ) = ( 600 kHz ) = vIN 10 10
R2 20 = 1+ =2 b) The closed-loop gain of the circuit is: ACL = 1 + R1 20

2
T3 Therefore, when the input signal varies between 2V to 5V the output changes from 4V to 10V, obviously in the same period of time, t=5 s. Then, V = 14 V = 3.5 s < t
SR
4V
R1 = 0.5 (1). Also, since = R1 + R2
we have BWCL= f3dB-CL= fT =0.52 MHz = 1 MHz Moreover, we know that the eqn. for the settling time is
tsettle
0.35 0.35 = = 6 = 0.35 s << t (2) BWCL 10
From both conditions (1) and (2) => No distortion will occur.
T3 3.2- The op-amp in Fig.3.2 has a slew rate of 0.5 V/s. The amplifier must be capable of amplifying the following input signals: v1 = 0.01 sin(106t) v2 = 0.05 sin(350103t) v3 = 0.1 sin(200103t) v4 = 0.2 sin(50103t) a) Determine whether the output will be distorted due to slewrate limitations on any input. b) If so, find a remedy (other than changing the input signals). R1 R2 vIN 10 k 330 k vOUT Fig.3.2:
Solution:
T3 a) Assuming an ideal op-amp, the closed-loop voltage gain of the stage is: R 330 = 33 ACL = 2 = R1 10 For a sinusoidal input with peak value AP, the upper limit for the stages max. operating frequency is: 0.5 V 4
ACL AP SR (3) MAX
SR s 1.515 10 = = = 33 AP ACL AP AP
Therefore, we can now make the calculations for each case: v1 = 0.01 sin(106t) => AP= 0.01 V, = 106 rad. 1.515 104 1.515 104 MAX = = = 1.515 106 0.01 AP Since <MAX, no distortion will occur. v2 = 0.05 sin(350103t) => AP= 0.05 V, = 3.5105 rad. 1.515 104 1.515 104 MAX = = = 3.03 105 0.05 AP In this case >MAX, hence distortion will occur.
5
T3 v3 = 0.1 sin(200103t) => AP= 0.1 V, = 2105 rad. 1.515 104 1.515 104 MAX = = = 1.515 105 0.1 AP In this case >MAX, hence distortion will occur. v4 = 0.2 sin(50103t) => AP= 0.2 V, = 5104 rad. 1.515 104 1.515 104 MAX = = = 7.575 104 0.2 AP Since <MAX, no distortion will occur. Consequently, both v2 and v3 would cause the SR spec of the op-amp to be exceeded, resulting in distortions of the output. b) Two remedies can be applied to deal with the given signals: i- Use an op-amp with a better SR: The SR value of the new op-amp can be also extracted from the same condition (3) used previously: SR ACL AP (3). Aplying it for v2 yields
6
T3 SR 33 0.05 3.5105 = 5.775105 V/s = 0.5775 V/s whereas for v3 we obtain SR 33 0.1 2105 = 6.6105 V/s = 0.66 V/s. If we want to cover both cases with the same circuit, an op-amp with a SR of min. 0.66 V/s should be used, although it would be wise to also have some safety margin for other practical cases (or for variations in actual device characteristics). Hence, using an op-amp with a SR value of 0.81 V/s would be more realistic. ii- Reduce the ACL of the amplifier stage: This solution is necessary when the whole circuit has already been realized and solution (i) above cannot be implemented. We use again condition (3) to find out the necessary ACL value(s):
SR ACL AP SR (3) ACL MAX AP
Aplying it for v2 yields
T3
ACL 2
SR 5 105 = = 28.57 5 MAX AP 3.5 10 0.05 SR 5 105 ACL 3 = = 25 5 MAX AP 2 10 0.1
while for v3 we obtain
Again, if we want to cover both cases with the same circuit, we must choose the second value, as it would satisfy the conditions for both signals: ACL=25, which can be achieved if we change the R2 value from 330 k to 250 k.
T3 3.3- a) What minimum SR is necessary for a unity-gain amplifier that must pass, without distortion, the input waveform shown in Fig.3.3. b) Repeat (a), if the amplifier is in a non-inverting configuration with R1= 50 k and R2= 100 k. vIN 6V 4V 2V Fig.3.3: 2 3V
10 12
16 18 Time t [s]
T3 a) There are 5 intervals making up the piece-wise signal signal shown in Fig.3.3, but only in 4 of them the voltage changes:
Solution:
V 4 0 = =2 V 1) s t 20 V 6 ( 3) = = 2.25 V 3) s t 16 12
V 4 ( 3) = = 0.875 V 2) s t 10 2 V 60 = =3 V 4) s t 18 16
If we want to cover both cases with the same circuit, an op-amp with a SR of min. 3 V/s should be used. b) For a non-inverting configuration with R1=50 k and R2=100 k (see again Probl.3.1): R2 =3 ACL = 1 + R1 Consequently, having now an ACL1 will increase correspondingly each V by a factor of 3 => the necessary SR value is now 3 larger than that for the previous case: SRmin= 9 V/s.
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T3 3.4- In a certain application, a signal source having 60 k of source resistance produces a 1 V r.m.s. signal. The signal must be amplified to 2.5 V r.m.s. and drive a 1 k load. Assuming that the phase of the load voltage is of no concern, design an opamp circuit for the application. Solution: a) Inverting configuration: The signal source can be represented by Thevenins equivalent circuit: R1 R2 vS= 2 sin t RTH 60 k => v
S
RTH 60 k
vOUT vIN RL 1 k
It is clear that v IN
R1 = vS R1 + RTH
vOUT R2 R2 = vOUT = v IN and combining the At the same time ACL = v IN R1 R1 two relations gives
11
T3
R2 R1 R2 R1 vOUT = vS ATOT = R1 R1 + RTH R1 R1 + RTH In our case it was specified that the signal must be amplified to 2.5 V rms =>ATOT=2.5. The values of the resistors R1,2 should also be high enough so that the currents passing through them should be << IL. For example, one can choose R1= 47 k =>
R1 47 vIN = vS = = 0.43925 0.44 and then R1 + RTH 47 + 60 R1 + RTH 1 R2 = ATOT R1 = 2.5 47 = 267.5 k R1 0.44
A very close practical resistor value is 270 k.
12
T3 b) Non-Inverting configuration: For an ideal op-amp I+=I=0 => vS = vIN and it was given that vIN=1 Vrms and we must have vOUT=2.5 Vrms => ACL= 2.5 vS R2 R2 = 1.5 and must be =2.5 => ACL = 1 + R1 R1 If we choose R1= 100 k => R2= 150 k. c) Voltage follower: vS RTH 60 k vIN A1 vO1 R1 I+ RTH 50 I R2 vOUT RL 1 k
vIN
R1
R2 vOUT A2 RL 1 k
vS = vIN ; vOUT=ACLvO1
and we must have vOUT=2.5 Vrms=> |ACL|= 2.5 R2 = 2.5 R2 = 2.5R1. We can set R1= 100 => R2= 250 k R1 OR R = 47 k and R = 117.5 k; use 120 k.
1 2
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T3 3.5- Fig.3.5 shows an integrator employing an opamp whose frequency response is given by
Solution:
20log
The Bode plots describing the frequency response given for the opamp have a representation of the form:
A( s ) A0
A( s ) =
A0 1+ s
[dB ]
3 dB 6 dB/octave = 20 dB/decade
0 10 20 30
0.1
Determine the transfer function of the overall integrator. Simplify the result if 0>> 1/(RC).
5.7o
10
(log scale)
R v vIN Fig.3.5:
C A(s) vOUT
45 90
()
5.7o
14
o [deg] 45 /decade
T3 Therefore, it would be convenient to express the final result as a product of elementary one-pole functions. Being given the op-amps (not the entire circuits!) frequency response A(s), we can write vOUT= v.A(s) and at the same time
v IN v v vOUT = = sC ( v vOUT ) 1 R sC
We extract v from the first relation, introduce it in the 2nd and carry out the calculations: vOUT
vIN +
A( s ) vIN + vOUT = sRC vOUT [1 + A( s )] vOUT sRC [1 + A( s )] 1} = A( s ) { vIN

15
vOUT A( s ) = sC vOUT R A( s )
T3
A0 A( s ) H ( s) = = 1 + sRC [1 + A( s )] 1+ s
A0 1 + sRC 1 + 1+ s 0
H ( s) =
A0 s A0 1 + 1 + sRC 1 + 1+ s 0 0
16
T3
A0 H ( s) = s s 1 + + sRC 1 + + sRCA0 0 0 0 A0 H ( s) = 0 + s + 0 sRC + s 2 RC + sRCA00 1 H ( s) = s sRC s 2 RC 1 + + + + sRC 0 A0 A0 0 A0 A0 H ( s) 1 1 2 + s s RC + sRC0 ) + sRC ( 0 A0

17
T3
1 1 1 H ( s) = 2 RC s 1 2 RC sRC s + s RC + sRC 1 + +s A A A A 0 0 0 0 0 0 0 0
3.6- Design an integrator that attenuates input frequencies above 100 kHz and exhibits a pole at 100 Hz. Assume the largest available capacitor is 50 pF. Solution: Obviously, the same schematic and starting point can be used as in the previous problem: v v v vOUT IN = = sC ( v vOUT ) C 1
sC
R v vIN Fig.3.6: A0 vOUT
However, in this case we consider the opamp to be characterized by A0 => vOUT= vA0. Again, extracting v from the first relation and then substituting it into the first equation results in
18
T3
vOUT vIN + vOUT A0 = sC vOUT A0 vIN + vOUT = sRC vOUT (1 + A0 ) R A0 vOUT A0 sRC (1 + A0 ) 1 = A0 H ( s ) = 1 + sRC (1 + A0 ) v IN
Lets compare this response with the generic representation of a one-pole transfer characteristic from the previous problem A( s ) =
A0 s
1+ 0 1 . It quickly becomes evident that the pole is at 0 = RC (1 + A0 )
We could thus calculate R if we knew A0. To deduce A0 we use the other piece of data given by the problem: input frequencies above 100 kHz are attenuated. This translates into saying that (see again the Bode plots of the previous problem) |H()|=1 at f= 100 kHz.
19
T3 From the previous expression of A(s) one can easily deduce that the magnitude response is A0
A( ) =
and therefore for our equation |H()|=1 at f= 100 kHz we can write
1+ 0
| H ( ) | f =100 kHz =
A0 1+
f 10 = 1 A0 = 1 + = 1 + 2 100 f0 f f0
5
=> A0 103. If we choose C to have the given max. value, C=50 pF, then we can now calculate the unknown R:
1 1 R= = 31.83 k 12 3 2 f 0C (1 + A0 ) 2 100 50 10 10
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Tutorial 4: The diode (the semiconductor pn junction)T4

Problem 4.1Consider a pn junction in forward bias. (a) To obtain a current of 1 mA with a voltage of 750 mV, how should IS be chosen? (b) If the diode cross-sectional area is now doubled, what voltage yields a current of 1 mA?
Solution:
a) In forward bias, IF=ID=1 mA and VF =VD = 0.75 V. We also know the expression for the dependence of the current on the voltage in this regime: VD (1) I D I S exp
VT
What is VT? VT is the so-called thermal voltage:

kT VT = = q 1.38 10 23 J
19
[ K ] 300 [K ] 25.875 [mV ] 1 38.647 [V ] V 1.6 10 [C ]

1 T
1
T4 From eqn. (1), we can extract and calculate the value of the unknown parameter IS:
VD I S I D exp VT 750 3 16 I S 10 exp A 2.58 10 25.875
VD I D I S exp VT
b) Since IS is directly proportional to area, doubling the area automatically implies that IS has also doubled: now we have IS2= 2IS and at the same time VD 2 ID2 (2) I D 2 I S 2 exp VD 2 VT ln
VT
IS 2
Inserting the values we obtain:
VD 2
10 = 25.875 ln = 732.065 mV 732 mV 16 2 2.58 10

2
T4 4.2- Consider the circuit shown in Fig.4.2, where IS = 2x1015 A. Calculate VD and IX for VX = 0.5 V, 0.8 V, 1 V, and 1.2 V. Note that VD changes little for VX 0.8 V. Fig.4.2: VX
IX
R=2 k
Solution:
Obviously diode D is forward biased, and therefore we can write the corresponding well-known expression for the dependence of the current on the voltage:
VD VD I X = I F = I D = I S exp 1 I S exp VT VT ID IX VD = VT ln = VT ln (3) IS IS
T4 We can easily notice that the sum of voltage drops on the resistor & diode must equal the bias from the voltage source:
ID VX = VR + VD = RI R + VT ln IS
IX = RI X + VT ln IS
(5)
(4)
At the same time, the current through the resistor can also be expressed as:
VR VX VD = ID = I X = IR = R R
The desired final values of VD and ID=IX can be obtained by solving iteratively EITHER eqn.s (3) & (5), OR (4). Lets consider the 1st option, and start with the first given value: VX=0.5 V. We assume that D1 is ON; moreover, in order to obtain the numerical values we assume an initial guess value for VD1 of 0.4V. Then applying eqn.(5) results in: I X =
0.5 0.4 = 0.05 mA which, 2
T4 inserted in eqn.(3) gives
However, it can be easily noticed that this value makes VD >VX, which is obviously impossible! Therefore, our initial assumption is incorrect. This means that for VX = 0.5 V, the diode D is OFF, i.e. NO CURRENT flows through it, hence no current flows through the whole circuit: ID=IR=IX=0 => VD= VX =0.5 V. In fact, this should have been expected, since the first given value of (VX = 0.5 V) is obviously below the typical threshold voltage of a silicon diode (~0.60.8 V). For the second value, VX= 0.8 V, we can assume safely that D is ON (because now VX is above the diodes threshold voltage) and VD= 0.7 V. We repeat the same sequence of calculations: 0.8 0.7
0.05 103 VD1 = 25.875 ln = 619.5 mV 15 2 10
!!!
IX =
and apply successively eqn.s (3) & (5):

= 0.05 mA
T4
Iteration 1
Eqn.(5) (Calc.ID) Eqn.(3) (Calc.VD)
5105 8.875105 8.15105 8.25105
Iteration 2
Iteration 3
Iteration 4
0.7
Guess value
0.6225
0.637
0.635
0.635
No more variation from one step to another: STOP
Hence, the final values are: VD 0.635V, and ID 8.25105 A = 82.5 A The same procedure is thus repeated for the other values. For VX = 1 V, we get: Iteration 1 Iteration 2 Iteration 3 Eqn.(5) 1.5104 1.745104 1.725104 (Calc.ID) Eqn.(3) (Calc.VD) 0.7
Guess value
0.651
0.655
0.655

6
In this third case the final values are: VD 0.655V, and ID 172.5 A.
T4 For the last VD value (VD= 1.2 V), lets try a slightly different approach, based on using eqn. (4): IX (4) VX = RI X + VT ln
IS from which we extract IX: VX VT I X ln IX = R R IS
(4)
and this can also be solved iteratively (fixed-point iteration method):
We can now insert the values, and start the calculations using an initial guess value based again on the result given by eqn.(5):
VX VT ( I X )n ( I X )n+1 = ln R R IS
(4)
( I X )0
1.2 0.7 = = 0.25 mA = 2.5 104 A 2
which we
7
T4 insert and use for the iteration sequence based on eqn (4): (IX)1 2.678104 A (IX)2 2.669104 A (IX)3 2.670104 A (IX)4 2.670104 A Then VD value is then obtained applying eqn. (3):
ID VD = VT ln IS
2.67 104 663.85 mV = 25.875 ln 15 2 10
4.3- For the circuit shown in Fig.4.3 is given that at VX = 1 V IX = 0.2 mA and at VX = 2 V IX = 0.5 mA. Calculate R and IS. Fig.4.3: VX
IX
VD
8
T4
Solution:
Again, diode D is forward biased. At the same time, by KVL
IX IX VD= VX IX R and also VD = VT ln VX I X R = VT ln IS IS

and inserting the given values in the latter equation results in
0.2 (6) 1 0.2 R = VT ln I S (with all voltages in [V] and currents in 2 0.5 R = V ln 0.5 (7) [mA] => all resistances must be in [k]), T IS and subtracting (7)(6) gives 0.5 1 VT ln 0.5 0.2 0.5 0.2 1 0.3R = VT ln VT ln = VT ln R= 0.2 0.3 IS IS 0.5 3 1 25.875 10 ln 0.2 R 3.255 k R= 0.3
9
T4 Now we can find IS substituting the value of R in any of the eqn.s (6) or (7), e.g. in (6): 1 0.2 R 0.2 0.2
1 0.2 R = VT ln
IS
IS
= exp
VT
1 0.2 R 1 0.2 3.255 I S = 0.2 exp = 0.2 exp 3 25.875 10 VT I S 2.76 107 mA = 2.76 1010 A = 0.276 nA
4.4- Fig.4.4 depicts a parallel resistor-diode combination. If IS= 3x1016 A, calculate VD for IX = 1, 2, and 4 mA, respectively. It is clear that ID= IX IR= IX (VD/R) (8), Fig.4.4:
IX
IR
ID
ID and at the same time VD = VT ln IS VD
(9)
Again, these two equations can be solved iteratively for each case.
10
T4
Iteration 1
For IX = 1 mA:
Eqn.(8) (Calc.ID) Eqn.(9) (Calc.VD)
3104 2.82104 2.832104
Iteration 2
Iteration 3
0.7
Guess value Iteration 1
0.718
0.717
0.717
No more variation from one step to another: STOP Iteration 2 Iteration 3
For IX = 2 mA:
Eqn.(8) 1.283103 1.244103 1.245103 (Calc.ID) Eqn.(9) (Calc.VD) 0.717 0.756

Guess value
0.755
0.755
Notice that in the 2nd case the final value from the previous calculation is used as initial guess in order to minimize the number of steps to be calculated.
11
T4 For the last IX value (4 mA), lets use again the fixed-point iteration method
VT I D I D = I X ln which can be re-written in the more suitable form R1 I S
We can now insert the values, and start the calculations using an initial guess value based again on the result given by the final value of the previous case: 3
3
VT ( I D )n ( I D )n+1 = I X ln R1 I S
1.245 10 4 0.752 = 3.248 mA ( I D )0 = 4 25.875 10 ln 16 3 10 further resulting in

(ID)1 3.223 mA => (ID)3 3.2236078 mA => (ID)2 3.223609 mA => (ID)4 3.2236078 mA 3.224 mA 3.223078 103 3 776.39 mV VD = 25.875 10 ln 16 3 10
so that
12
T4 4.5- Sketch VX as a function of IX for the circuit shown in Fig.4.5. Assume: (a) A constant-voltage model, (b) An exponential model. Solution: a) Consider first the extreme case D IR when D= OFF => the circuit ID V =V R D X simplifies as IX IR R IX VR=VX Fig.4.5: and obviously VX is linearly proportional to IX, according to Ohms law. When D= ON, VX is fixed as VD-ON=VF 0.7 V. Therefore, the current flowing through R is also fixed and (quasi)constant IR=VF/R (we implicitly assumed that the current source IX can provide more than this value! Otherwise, D cannot be ON and we are in the previous case!). This means that any additional current (if the current source IX supplies more than the value of IR) must flow through D. Consequently, the plot of VX vs. IX will be:
13
T4 VX VF VF /R Slope=tan =R D= Reverse biased calculations we can use the relations: IX D= Forward biased b) If an exponential I-V model is used for D, we still have two cases but the quantitative values will be different. When D=OFF, the greatest part of IX flows through R, and only a very small part (yet 0 !) flows through D. When D= ON, the current IR is again fixed and any additional current must flow through D. In order to make the
ID VD = VX = VT ln IS
and
VX VX ID = I X I X = I S exp R VT
VX + R
14
It is now clear that in each case one of the term dominates. For instance, in the 2nd case, if IR<<ID (when VX>>VT), then we can approximate
T4
VX IX I X I S exp VX VT ln IS VT
Consequently, the plot of VX vs IX will be: VX D= Forward biased
IF D= Reverse IR>>ID VXIX biased IR<<ID VX ln(IX )
IX
15
T4 4.6- Beginning with VD-ON 800 mV for each diode, determine the change in VOUT, if VIN changes from +2.4 V to +2.5 V for the circuits shown in Fig.4.6. a)
VD
D R1=1 k
VOUT
VIN
In this case it is clear that VOUT=VIN VD and, therefore, the output values when the input varies between 2.4 and 2.5 V will be VOUT =VIN VD-ON= VOUT0.8 => VOUT= 1.61.7 V.
Solution:
b)
VD
D1
VOUT In this case, when the input varies between 2.4 and
VIN
R1=1 k D2 Fig.4.6:
2.5V both diodes are ON and the output values will be the same as in the previous case: VOUT = VIN VD1-ON= VOUT 0.8 => VOUT = 1.61.7 V.
16
T4 D1 R =1 k VOUT Again, when the input varies between 2.4 and 1 2.5V both diodes are ON and the output clearly is: VOUT =VD2-ON = 0.8. V VD1 D2 D2 R1=1 k
VIN
c)
VOUT As in the previous case, when the input varies

D
VIN
d) R2=2 k
VD
between 2.4 and 2.5V the diode is ON and the output clearly is: VOUT =VD-ON = 0.8.
Fig.4.6 (continued):
17
T4 4.7- Determine the AC component of the output voltage, vOUT for the circuit in Fig.4.7 when VSDC= 5 V D.C. The data sheet for the 1N4305 diode has the following voltage and current values: VD1= 0.5 V at ID1 = 250 A VD2 = 0.7 V at ID2 = 10 mA vOUT Solution: We know that RS=0.47 k VD VD vSAC I F = I D = I S exp 1 I S exp D (0.1Vpp) V V T T 1N4305 VSDC VD 2 VD1 I D2 VD 2 VD1 (5V) = exp VT = Fig.4.7: I D2 I D1 VT ln I D1 V V 0.7 0.5 Inserting the values we obtain: VT = D 2 D1 = = 54.217 mV 3 ID2 10 10 ln ln I D1 250 106
18
T4 Now we can easily find IS:
VD 2 0.7 2 8 = = I S = I D 2 exp A 10 exp 2.47 10 0.054217 VT (It is necessary to use the equation for ID2 because the unity in the expression of ID can be easily neglected). Now we can calculate the AC component of the vOUT. For this we need first to carry out 2 consecutive analyses: D.C. and A.C.
DC analysis:
VSDC (5V) RS=0.47 k D 1N4305 ID
The circuit can be re-drawn as: This is identical with the cases studied earlier in Problems 1.2 and 1.3:
I D = I RS
VRS VSDC VD 5 VD (10) and = = = 470 RS RS

(11), which we solve iteratively:
19
ID VD = VT ln IS
ID 3 = 54.217 10 ln 8 2.47 10
T4 Eqn.(10) 9.1489103 9.1592103 9.15907103 (Calc.ID) Eqn.(11) (Calc.VD) 0.7

Guess value Iteration 1 Iteration 2 Iteration 3
0.69518
0.695238
0.695238
In this case we need to consider the small-signal dynamic resistance of the diode at its DC bias point calculated above. The dynamic resistance is given by: V 0.054217
AC analysis:
vOUT
vSAC (0.1Vpp) RS=0.47 k iD rd
rd =
ID
9.159 10
vOUT
= 5.92
and, evidently
rd vSAC = = rd + RS
20
5.92 = 0.1 = 1.244 mV pp 5.92 + 470
Tutorial 5: BJTs
T5
5.1. a) Measurements taken on a variety of transistors are found to be incomplete (or possibly in error). Available data are as shown. Provide the missing data and calculations, and point out inconsistencies if any. Device IC [mA] 10 0.02 0.63 98 10 10.1 0.99 0.001 0.2 0.1 0.01 0.015 IB [mA] IE [mA] 10.1 1.12 99 0.011 10.1 10 0.984 0.99 0.99 0.995 100 63 98 10 100 99 193
1
a b c d e f g h i
T5 5.1.b) If the base voltage on an npn transistor is +5V with respect to (w.r.t.) ground and the emitter voltage is +6V w.r.t. ground, is the base-emitter junction properly biased for linear applications? Explain. 5.1.c) If the junction voltages in the following transistor have the values listed, is it properly biased for linear applications ? Si npn; VBE= 0.7V, VCB= 10V. 5.1.a) Device a: IE= IB+IC => IB= IE IC = 0.1 mA.
Solution:
We also know that = = and, using the first relation, in 1+ 1 this case we obtain = 0.99.
Device b: IE 1.12 1 = 1 = 55 = IE=(+1)IB => =
Also, IC= IEIB= 1.120.02= 1.1 mA. Alternatively, one can use IC=.IB
IB
0.02
55 = = 0.982 1 + 56
2
T5 Device c (we can first check that & are correct: =63/640.984): IC=.IB Alternatively, one can do calculations using the relation IC=.IE IC=.IB
0.63 = = 0.01 mA and IE=(+1)IB => IE= =0.64 mA. => I B = 63
IC
Device d: (we can first check that & are correct: =98/990.99):
IB in the initial Table must be wrong. However, since we now that IE=IC+IB must hold true, we can only assume that IB= 0.1 mA and are correct =>
98 = = 1 mA OR IB= IEIC = 1 mA. => I B = 98 IE 0.011 1 = 1 = 10 The value shown Device e: IE=(+1)IB => = IB 0.001 in Table is correct. 10 IC=.IB => IC= 10.0.001=0.01 mA and = = 0.9091 1 + 11 I C 10 . Device f: IC= IB => = = = 50 Either the entry for or that for I B 0.2
3
IC
T5
100 we can now check that the value of is correct: = = 0.9901 1 + 101
Device g: First, we should notice that in the Table IC>IE, which is an impossibility. For real devices the two values of the two currents must be swapped, i.e. the correct values are IC= 10 mA & IE= 10.1 mA. Then both IB and values in the Table are correct and we can calculate :
100 = = 0.9901 1 + 101

Device h: The value of either or in Table is incorrect. Since IC=.IB => =IC/IB = 99 must be correct, and therefore the correct value of is
99 = = = 0.99 1 + 100
Then IE=(+1)IB = 100.0.01=1 mA OR OR IC=.IE => IE= IC/ = 1 mA.
IE= IB+IC = 1 mA;

4
T5 Device i: From the values of IB & it results that IC=.IB => IC= 193.0.015= 2.895 mA and IE= IB+IC = 2.91 mA. Then, from IC= .IE =>
I C 2.895 = = = 0.9948. 2.91 IE

5.1.b) VBE= VBVE = 56= 1V. Consequently, the base-emitter (B-E) junction of the transistor is not properly biased for operation in the normal active regime for linear & analog amplification. To enable such an operation we must forward bias the B-E junction, i.e. VBE= 0.60.8 V (typically around 0.7V). 5.1.c) So we have a Si npn transistor with VBE= 0.7V, VCB= 10V. As in the previous case, the base-emitter (B-E) junction of the transistor is not properly biased as VBE<0.
T5 5.2. For the circuits in Fig.5.2 find the labelled currents and voltages. Let =100 and IVBEI= 0.7 V. VCC=+10 V a) IB VBB= 0 V Q1 VE RE = 10 k VEE= 10 V
VEE=+10 V b) RE = 5 k VE IB VBB= 0 V Q2 VC RC = 5 k VCC= 15 V

6
RC = 10 k VC
Fig.5.2:
T5
Solution:
a) IB
VCC=+10 V RC 10 k Q1 IC
By KVL around the GND-BE jct.-RE-VEE loop: VBE+REIE= VEE =>
VC and for biasing in the active regime we must have VBE=0.7V, hence VE IE
VEE VBE IE = RE
VBE= 0.7 V VBB= 0 V RE 10 k VEE= 10 V
10 0.7 IE = = 0.93 mA 10 IE 0.93 IB = = = 9.2 A; + 1 101 I C = I B = 0.9208 mA
VC= VCC RCIC = 10 9.208= 0.792 V, and obviously VE= VBE= 0.7 V => VCE= VC VE= 1.492 V 1.5 V. Also VCB= VC VB= VC = 0.792 V, i.e. C-B jct. is reverse biased, and, therefore, Q1 is indeed in the active regime.
7
T5 b) VEE=+10 V RE 5 k VEB= 0.7 V VBB= 0 V IB RC 5 k VCC= 15 V IE VE Q2 VC IC By KVL around the GND-BE jct.-RE-VEE loop: VBE+REIE= VEE =>
VEE VBE IE = RE
and for biasing in the active regime we must have VBE=0.7V, hence
10 0.7 IE = = 1.86 mA 5 IE 1.86 IB = = = 18.42 A; + 1 101 I C = I B = 1.842 mA
VC= VCC +RCIC = 15 + 9.208= 5.79208 V, and obviously VE= VEB= 0.7V => VCE= VC VE= 6.49208 V 6.5 V. Also VCB= VC = 5.8 V, i.e. the C-B jct. is reverse biased, and, therefore, Q2 is indeed in the active regime.
8
T5 5.3. The transistors in the circuits shown in Fig.5.3 have very large values of , so we may assume the base currents to be negligibly small. If, in addition, it is determined by measurement that IVBEI=0.7V, find the values of the labelled voltages. VEE = +10 V VCC = +10 V b) a) RC = 10 k RE = 5 k VC VE Q1 Q2 RB = 10 k RB = 10 k VE VC VB VB RE = 10 k
RC = 5 k Fig.5.3: VCC = 15 V
9
VEE = 10 V
T5
Solution:
a) VCC=+10 V RC 10 k V Q1
B
RB 10 k
We are given that => IB=0 => IC IE. Additionally, IB=0 => RBIB=0 hence VB=0. IC Thus, since for biasing in the active regime we VC must have VBE=0.7V => VE= 0.7V => VE IE
VBE= 0.7 V RE 10 k VEE= 10 V
VE + VEE 10 0.7 = = 0.93 mA. IE = 10 RE

IC IE => VC = VCC RCIC = 109.3= 0.7 V => VCE= VC VE= 1.4 V. Also VCB= VC VB= VC = 0.7 V, i.e. the C-B jct. is reverse biased, and, therefore, Q1 is indeed in the active regime.
10
T5 VEE=+10 V b) R
E
5 k
VEB= 0.7 V RB VB 10 k RC 5 k VCC= 15 V
VE Q2 VC
We are given that => IB=0 => IC IE. Additionally, IB=0 => RBIB=0 hence VB=0. Thus, since for biasing in the active regime we must have VEB=0.7V => VE= +0.7V =>
VEE VE 10 0.7 IE = = = 1.86 mA. 5 RE

IC IE => VC = VCC + RCIC = 15+9.3= 5.7 V => VCE= VC VE= 6.4 V. Also VCB= VC = 5.7 V, i.e. C-B jct. is reverse biased, and, therefore, Q2 is indeed in the active regime.
11
T5 5.4. A single measurement indicates the emitter voltage of the transistor in the circuit of Fig.5.4 to be 1V. Under the assumption that |VBE|=0.7V, what are VB, IB, IE, IC, , and ? VB= VE VEB = 10.7= 0.3 V, and obviously Solution: VEE = +5 V RE 5 k VEB= 0.7 V VB RB 20 k IB RC 5 k IE VE Q VC
VB 0.3 IB = = = 15 A. RB 20 VEE VE Also VE+REIE= VEE => I E = RE 5 1 IE = = 0.8 mA 5 I C = I E I B = 0.8 0.015 = 0.785 mA;
IC
Fig.5.4: VCC = 5 V
IC = = 52.333 IB 52.333 = = 0.98125 1 + 53.333

12
T5 5.5. Identify whether the circuits in Fig.5.5 operate in the active or saturation mode. What is the emitter voltage in each case? If active, what is the collector voltage? IVBEI=0.7V, =100. Solution: Lets start by assuming that Q1 is in the active regime => VBE= +0.7 V. It is evident that VCC=+6 V VE= VBB VBE= 1.3 V, and a) RC IC VE 1.3 IE IE = = = 1 mA I B = 3 k +1 RE 1.3 VC 1 IB Q1
IB =
VBB= +2 V VBE= 0.7 V RE 1.3 k Fig.5.5:
VE IE
101
= 9.9 A I C = I B = 0.99 mA
VC= VCC RCIC = 630.99= 3.03 V VCB= VC VBB= 3.032 = 1.03 V, i.e. the C-B jct. is reverse biased, and VCE= VC VE= 1.73 V. Consequently, Q1 is indeed in the active regime.
13
T5 Assume that Q2 is in the active regime => VEB= +0.7 V. It is evident that VE= VBB+VEB= 1.7 V, b) IE RE and VEE VE 6 1.7 IE = = = 0.43 mA 10 k VE RE 10 VEB= 0.7 V If we consider IC IE => VC= RCIE = 4.3 V VBB= +1 V Q2 VCB= VC VBB= 4.31= 3.3 V, i.e. C-B jct. VC is forward biased => Q is in the saturation 2 IB regime NOT the active one, hence VCE= RC IC =VCEsat= 0.3 V => VC= VEVCEsat= 1.4 V Fig.5.5 10 k =>VCB= 0.4 V (still forward biased). Notice (continued): that these are very different values from those previously obtained above when we started from the assumption that IC IE. This shows clearly that that assumption was not correct, hence we must recalculate IC: VC 1.4 IC = = = 0.14 mA I B = I E I C = 0.43 0.14 = 0.29 mA RC 10
14
VEE=+6 V
T5 VEE=+95 V RE 200 k VEB= 0.7 V VBB= 5 V IB RC 20 k VCC= 50 V Fig.5.5 (continued): c) Assume that Q3 is in the active regime => VEB= +0.7 V. It is evident that VE= VBB+VEB= 4.3 V, IE and VEE VE 95 ( 4.3) IE = = = 0.4965 mA VE RE 200 If we consider IC IE => VC= VCC+RCIE = Q3 50+9.93= 40.07 V => VCB= VC VBB 35 VC V, i.e. C-B jct. is reverse biased => Q is in the 3 active regime. Then we can make more IC accurate calculations:
IE 0.4965 = = 4.92 A IB = +1 101 I C = I B = 0.49158 mA

=> VC= VCC+RCIC = 50+9.8316= 40.17 V => VCB= VC VBB 35.17 V => VCE= VC VE= VCB VEB 35.87 V.
15
T5 VCC= 10 V d) RC 2 k IB Q4 VE IE IC VC Assume that Q4 is in the active regime => VBE= +0.7 V. It is evident that VE= VBBVBE= 20.7 V, and V +V 20.7 + 30
IE =
EE
RE
= 1.86 mA
VBB= 20 V VBE= 0.7 V RE 5 k VEE= 30 V Fig.5.5 (continued):
VC= VCC + RCIC = 10 21.8416= 13.6832 V VCB= VC VBB= 13.6832+20= 6.3168 V, i.e. the C-B jct. is reverse biased, and VCE= VC VE= 13.6832+20.7=7.0168 7 V. Consequently, Q4 is indeed in the active regime.
IE IB = = 18.416 A +1 I C = I B = 1.8416 mA
16
T5 5.6. Find the voltages at all nodes and the currents through all branches in the circuit of Fig.5. Assume that =50 and the IC and VBE for the transistor is described by VBE=0.026.ln(IC/1014). Solution: We start by replacing the R1-R2 group connected to B with a VCC= +9 V Thevenin equivalent source: R2 Vth = VCC VCC= +9 V RC R1 + R2 I C RC R1 50 k 0.47 50 k V Q 2.878 V C Vth = 9 1 M 1 IB 1 + 0.47 R th => Q1 1 0.47 B VE Rth=R1 | | R2 = RE 1 + 0.47 V th VBE= 0.7 V 30 k R2 0.31973 M =319.73 k. IE RE 470 k Vth= RthIB+VBE+REIE 30 k with IE= (+1)IB => Fig.5:
17
T5
Vth VBE Vth VBE IB = IC = Rth + ( + 1) RE Rth + ( + 1) RE
(1)
However, we cannot assume automatically VBE= 0.7V, since the problems hypothesis already indicated that IC (2) VBE = VT ln
1014
It is now obvious that these two equations will have to be solved iteratively:
Iteration 1
Eqn.(1) (Calc.IC ; in [mA]) Eqn.(2) (Calc.VBE ; in [V])
59103
62103
Iteration 2
Iteration 3
62103
Iteration 4
0.7
Guess value
0.585
0.586
0.586
Hence, we now have IC 0.062 mA and VBE 0.585 V.

18
T5
+1 51 IE = IE = I C = 0.062 = 0.06324 mA 50 and IB=IC/= 0.06324/50 = 1.2648 A; VE= REIE = 0.0632430= 1.8972 V => VB= VE+VBE = 2.5972 V, and VC= VCCRCIC = 9500.06324= 5.838 V => VCB= VCVB 3.24V, hence the C-B jct. is reverse biased, and consequently, Q1 is indeed in the active regime. VCE= VC VE= 5.838 1.8972 3.94 V.
IC
19
Tutorial 6: MOSFETs
T6
6.1- A certain NMOS fabrication process yields Kn = 50 A/V2 and VTN= 1 V. Determine the width-to-length ratio needed if it is required that IDS= 0.5 mA when VGS= VDS= 5 V. State any assumption made. Solution: We first need to determined the operation regime/region. Since VGS>VTN and VDS VGSVTN= 4V => the NMOS transistor operates in the saturation region. Consequently, we can use the corresponding equation describing the transistors operation in this region, assuming that the channel length modulation factor =0: Kn 2 W I DS = VGS VTN where K n = nCox is the transistor gain factor L 2
Kn =
(VGS VTN )
2 I DS
1 = = 0.0625 mA 2 = 62.5 A 2 V V 16
W W K n 62.5 Because K n = Kn ' = = = 1.25 L L Kn ' 50
T6 6.2- Two points in the saturation region of an NMOS transistor are: (VGS1= 2 V and IDS1= 0.5 mA) and (VGS2= 3 V and IDS2= 2 mA). Assuming =0 find the values of VTN and Kn.
Solution:
As we know clearly that the NMOS transistor operates in the saturation region, we can use the corresponding equation describing the transistors operation in this region, again assuming that the channel length Kn 2 modulation factor =0:
I DS =
and inserting in it the data for the two points we derive a system of two equations with two unknowns:
2 2 I DS 1 (VGS 1 VTN ) 2 I DS 1 = K n (VGS 1 VTN ) = 2 2 I (VGS 2 VTN ) DS 2 2 I DS 2 = K n (VGS 2 VTN ) I DS 1 VGS 1 VTN = (VGS 2 VTN ) = a (VGS 2 VTN ) I DS 2
(VGS VTN )
T6
aVGS 2 VGS 1 aVGS 2 VGS 1 = ( a 1) VTN VTN = a 1 I DS 1 0.5 0.5 3 2 In our case a = = = 0.5 VTN = = 1V . I DS 2 2 0.5 1
We can now introduce this value in one of the eqn.s and find Kn:
Kn =
(VGS 2 VTN )
2 I DS 2
( 3 1)
= 1 mA 2 V
T6 6.3- Two points on the characteristic curve for VGS= 3 V of an NMOS transistor are: (VDS1= 5 V and IDS1= 1 mA) and (VDS2= 10 V and IDS2= 1.25 mA), and VTN= 1 V. Determine the value of . Solution: Obviously, now we must consider the equation describing the transistors operation in the saturation region without neglecting the channel length modulation factor :
I DS
and inserting in it the data for the two points we derive a system of two equations with 2 two unknowns, 2 I DS 1 = K n VGS VTN 1 + VDS 1 and Kn: 2
Kn 2 = (VGS VTN ) (1 + VDS ) 2
I DS 1 1 + VDS 1 1 + VDS 1 1 b = b= = 1 + VDS 2 I DS 2 1 + VDS 2 bVDS 2 VDS 1

4
( ) ( ) 2 I DS 2 = K n (VGS VTN ) (1 + VDS 2 )
T6
I DS 1 1 1 0.8 In our case b = = = 0.8 = = 0.06667 V 1 I DS 2 1.25 0.8 10 5

We can now introduce this value in one of the eqn.s and find Kn:
Kn =
(VGS VTN ) (1 + VDS1 )

2
2 I DS 1
Kn =
mA 2 0.375 = 2 V ( 3 1) (1 + 0.06667 5)
2 1
T6 6.4- Given VTN= 1 V, =0 and Kn= 0.5 mA/V2, check if the NMOS transistor in Fig.6.4 is operating in the saturation region and determine IDS and VDS. Solution: For any MOSFET transistor it is usually safe to consider that IG=0 => VG=0 and by KVL in the RG-VGS-RS-VSS loop: VDD= +15 V VG=0 =VGS+RSIDSVSS => VGS= VSSRSIDS . We assume RD that the transistor operates in the saturation region, Fig.6.4: 1 k again considering a channel length modulation factor IDS =0: Kn 2 Q1
I DS =
and introducing in it the 1st eqn. above we obtain: RG 1 M VGS RS 3 k VSS= 15 V
(VGS VTN )
I DS
Kn 2 = (VSS RS I DS VTN ) 2
which is a 2nd
order eqn. in IDS that we need to solve. Inserting the values results in: IDS=0.25.(153IDS1)2 <=> 9IDS288IDS+196=0 =>
6
T6
I DS 1,2
We need to choose the solution which validates our initial assumption of working in the saturation regime. In order to do this analysis we must calculate first VGS, then VDS, and compare the latter with VGSVTN. From the circuit it is clear that VDD+VSS=(RD+RS)IDS+VDS => VDS= VDD+VSS (RD+RS)IDS For the first IDS solution: VGS= VSSRSIDS= 1536.346= 4.038 V <<VTN !! Obviously, this is an unrealistic value since it would not allow the transistor to conduct current. For the second IDS solution: VGS= VSSRSIDS= 1533.4317= 4.705 V => VGSVTN= 3.705 V. VDS= 3043.4317= 16.27 V > VGSVTN hence this second solution describes correctly the operation of the transistor in the saturation regime. In conclusion, the quiescent D.C. operating point is at VDS=16.27 V and IDS= 3.43 mA.
88 882 4 9 196 = I DS 1 = 6.346 mA; I DS 2 = 3.4317 mA 18
T6 6.5. Given VTN= 4 V, =0 and Kn=2 mA/V2, repeat problem 4 for the circuit shown below in Fig.6.5. Solution: Again we consider that IG=0 => VG is established solely by the VDD= +20 V resistive potential divider formed by RG1 and RG2 at a value VG=VDD/2= +10 V. By KVL in the VG-VGS-RSRD GND loop: VG= VGS+RSIDSVSS =>VGS= VSSRSIDS+VG RG1 1 k <=>VGS=10IDS. We assume that the transistor 1 M IDS operates in the saturation region, again taking =0: Q1 VG RG2 1 M Fig.6.5: VGS RS 1 k
Kn 2 I DS = (VGS VTN ) and introducing in it the 1st 2 eqn. above we obtain: Kn 2 I DS = (VSS RS I DS + VG VTN ) which is a 2nd 2
order eqn. in IDS that we need to solve. (Alternatively, we can express IDS as a function of VDS and solve for the latter). Inserting the values results in: IDS= (10IDS4)2 <=> IDS213IDS+36=0 =>
8
T6
I DS 1,2
We need to choose the solution which validates our initial assumption of working in the saturation regime. In order to do this analysis we must calculate first VGS, then VDS, and compare the latter with VGSVTN. From the circuit it is clear that VDD=(RD+RS)IDS+VDS => VDS= VDD (RD+RS)IDS For the first IDS solution: VGS= 10IDS= 109= 1 V < VTN= 4 V!! Obviously, this is an unrealistic value since it does not allow the transistor to conduct current (cut-off). For the second IDS solution: VGS= 10IDS= 6 V => VGSVTN= 2 V. VDS= 2024= 12 V > VGSVTN hence this second solution describes correctly the operation of the transistor in the saturation regime. In conclusion, the quiescent D.C. operating point is at VDS=12 V and IDS= 4 mA.
9
13 132 4 36 = I DS 1 = 9 mA; I DS 2 = 4 mA 2
T6 6.6. Find the quiescent point of the PMOS transistor in Fig.6.6 given that VTP= 2V and Kp=100 A/V2. Solution: Again we consider that IG=0 => VG=VD=RDIDS. By VSS= +12 V KVL, VSS=RDIDS+VSD => VSD= VSS RDIDS (1). IDS Because the drain and the gate have the same VGS potential => VGS= VDS= VSD=> the condition VG |VDS|=|VGS||VGS||VTP| is satisfied and therefore the transistor is certainly operating in the saturation RG V SD Q1 Kp 2 1 M VGS VTP VD region. Hence, I DS = 2 RD and after introducing in it eqn.(1) above rewritten 100 k VSS VSD 12 + VGS Fig.6.6: we obtain: = in the form I DS =
RD
100
12 + VGS = 100 0.05 ( VGS 2 ) 5 VGS 19 VGS + 8 = 0

2 2
10
T6
VGS 1,2
19 192 4 8 5 = VGS 1 = 0.4823 V ; VGS 2 = 3.318 V 10
Evidently, only the second value has real physical meaning since the first one is below the threshold: |VGS1|<|VTP| and would therefore place the transistor in cut-off, not in saturation. Finally, we can deduce VDS= VGS= 3.318 V and the corresponding current is 12 + V 12 3.318
I DS =
GS
100
100
= 86.82 A.
11
T6 6.7. Determine the region of operation for the transistor in Fig.6.7 given that VTP= 1 V and Kp= 250 A/V2. Clearly VG=0 => VGS= VSS= 4V, and we assume that Solution: the transistor operates in the saturation region, again VSS= +4 V considering a channel length modulation factor =0: IDS VGS Kp 2 2 I DS = VGS VTP = 0.125 ( 4 1) = 1.125 mA. VG 2
Q1 RD 1.6 k Fig.6.7:
VSD
I DS = 2 K p 2 V V V V ( ) GS TP DS DS
2
At the same time VSS= RDIDS+VSD => VSD= VSS RDIDS= 4 1.61.125 = 2.2 V => |VDS|=2.2 < |VGS||VTP|=3 V => our initial assumption of operating in the saturation regime is not correct. At the same time, we notice that |VGS|>|VTP|, hence the device can be only in the linear (triode) region => and
I DS
VSS VSD = RD
12
T6 and inserting the values results in: 4|VDS|=1.620.25[2 (41)|VDS||VDS|2] <=> 0.8|VDS|25.8|VDS|+4=0 =>
VDS 1,2
5.8 5.82 4 4 0.8 = VDS 1 = 0.7718 V ; VDS 2 = 6.478 V 1.6
Obviously only the first value has real physical meaning since only this value satisfies the condition |VDS|<|VGS||VTP|=3 V necessary for operating in the linear regime. Consequently,
I DS
VSS VSD 4 0.7718 = = = 2.018 mA. RD 1.6
13
Author: Assist. Prof. Poenar Daniel Puiu
T2
Analogue Electronics (EE2002)
-Addition to TUTORIAL 7Assistant Professor Poenar Daniel Puiu Office: S2.2-B2-06 Tel.: 6790 4237 E-mail: epdpuiu@ntu.edu.sg
1
Author: Assist. Prof. Poenar Daniel Puiu Recapitulation:

Bipolar transistors (continued): Input and output characteristics in amplification IB [A] VB (1+)RE IBQ VBEQ
IC [A]
T2
ib(t)
IBE=IS.exp t
qVBE mkT
VBE [V]
Max. power dissipation
Saturation t VCC RC ICQ
vbe(t) VCC ibe(t) t
IB=0.01 A
VCE [V] VCC Cut-off

2
VA (Early voltage due to base width modulation)
VCEQ t vce(t)
Author: Assist. Prof. Poenar Daniel Puiu Recapitulation (continued):
T2
Bipolar transistors (continued): Single-stage Amplifier Configurations RC A.C. in VBB RC A.C. in VBB RE RB A.C. out IC VCC b) Common collector (Emitter follower): A1 Zin= high Zout= low
3
IC A.C. out VCC
RB
a) Common emitter: A= moderate (tens) Zin= moderate Zout= moderate

RC RB IC VBB RE A.C. in A.C. out VCC c) Common base: A moderate Zin= low Zout= high Cin=low
T2
vin
A.C. in
vout (gain=AV= ) vin

Energy (D.C. supply)
Amplifier
vout
A.C. out
4
Author: Assist. Prof. Poenar Daniel Puiu Recapitulation (continued): To determine Rin:
Apply a voltage source vx at the (input) terminals where Rin is to be measured; Note with ix the current due to vx (which is provided by the new voltage source); Rin = vx/ix
T2
To determine Routput:
Remove the load RL and replace it with a voltage source vx at the output terminals; Note with ix the current due to vx (which is provided by the new voltage source); At the same time, passivate the input signal source (vi or ii); R0 = vx/ix

Input resistance as seen from the emitter: Input resistance as seen from the base: ix v
be
T2
Rin=re
vx
vx ie
vbe
ix v VT be rin = = = re ie IE
vbe VT rin = = = r = = ( + 1) re ib IB gm
1 re = gm gm
=>
Rin=r
What is VT? VT is the so-called thermal voltage:

kT 1.38 10 23 [ J ] 300 [ K ] 1 1 [ ] VT = = 25 . 875 mV 38 . 647 V q 1.6 10 19 [C ] VT
[ ]
6

The equivalent A.C. hybrid small signal model of a transistor:
T2
C
B C
vbe r C E
ro
gmvbe
VA ro = IC
where VA= the Early voltage
BOTH npn & pnp transistors have the same A.C. small signal model !!! The simplified equivalent A.C. hybrid small signal model of a transistor: IC B C vbe gm = 38I C mA ; V kT / q r g v
m be
vbe VT r = = = ( + 1) re ib I B gm

Another simplified equivalent A.C. hybrid small signal model: B
T2
For a transistor with hFE= independent of current h = h

fe FE
ib r
E
hfeib
However, in practice, this approximation does not always hold:
The relevant small-signal current gain hfe is:
dI C hFE h fe = dI B 1 I C dhFE hFE dI C
IC (log scale)
8
Author: Assist. Prof. Poenar Daniel Puiu
T2
Other simplified equivalent A.C. A.C. Problem Solving Procedure: hybrid small signal models: 0) Identify parts of schematics which can C be simplified (e.g. have a specific function) B ib vbe The T-models (looking from the emitter!) gmvbe re E C
or discarded! 1) Very careful DC analysis => VCE, IC => 1.A) CHECK IF TRANSISTORS ARE IN ACTIVE REGIME !! 1.B) Calculate gm, r, etc. 2) Simple AC analysis: 2a) Passivate the DC sources; 2b) Consider the relevant capacitors; 2c) Redraw the schematics for a.c. 2d) Replace transistors by a simplified equivalent a.c. model; 2e) Calculate A, Rin, Rout. 3) Complete A.C. analysis: full model and with all the capacitors, including feedback.
9
ib
B re
ie ie
E
Tutorial 8: A.C. circuits with MOSFETs & BJTs (2)
T8
8.1- (a) A circuit is to be biased at a current of 10 mA and achieve an input resistance of at least 1 M. Should a BJT or MOSFET be chosen for this circuit and why? (b) A circuit requires the use of a transistor with a transconductance of 0.5 S. A bipolar transistor with = 60 and a MOSFET with Kn= 25 mA/V2 are available. Which transistor would be preferred and why? (c) A common-emitter amplifier has a gain of 50 dB and is developing a 15 V peak-to-peak A.C. signal at its output. Is this amplifier operating within its small-signal region? If the input signal to this amplifier is a sine wave, do you expect the output to be distorted? Explain your answer. Solution: a) Since a relatively high RIN is required at a relatively high current, a MOSFET should be used. If a BJT were selected, it would be very difficult to achieve the required input resistance because its value of r is low (assume we have a = 100 for the BJT):
1
T8
r =
gm
VT
IC
100 25.875 10 = 10 103

gm 2Kn
2
= 258.75
= 12.94 mA 13 mA
b) For the BJT: I C = g mVT = 0.5 25.875 10 For the MOSFET:
Id =
2 ( 25 10
( 0.5)
2 3
=5 A
The results clearly indicate that the BJT can achieve the required transconductance at a current 400 lower than that of the MOSFET ! For a given power supply voltage, a BJT will therefore use 400 times less power. It should be noted, however, that as we have just seen above- that r is small for BJT. In this particular case:
60 r = = = 120 g m 0.5
versus (theoretically; practically =RGM) for the MOSFET.

2
T8 c) We know that for the small-signal operation of a BJT the following condition must be obeyed: vbe<<2VT. As usual, lets consider that a factor of 10 difference between the quantities is sufficient to replace the inequality: |vbe|0.2VT = 5 mV. Since we are given both the gain and the output signal, we can calculate the actual input signal amplitude and check if it satisfies the above requirement: AV [ dB ]
AV [dB ] = 20log AV AV = 10
50 20
20
AV = 10 | vbe |=
= 316.228 15 = = 47.43 mV >> 5 mV 316.228

3
VOUT pp AV
Consequently, the input signal is far too large to be considered as small signal. Therefore, significant distortion of the sine wave will occur.
T8 8.2- The amplifier in Fig.8.2 is the common-emitter amplifier circuit discussed in the lecture, with the same transistor parameters (= 65 and VA= 50 V), except that the currents have been reduced by a factor of approximately 10. What are the voltage gain, input resistance and output resistance of this amplifier? Solution: The problem is very similar VCC= +5 V with Problem 7.2 of the RC previous tutorial. 100 k C3= vout As usual, we must start first RS with: 0.33 k R3 S1) D.C. analysis: In order to 220 k Q vin 1 simplify our calculations we C1= R1 can use a simpler equivalent RE 1 M 160 k C2= circuit: Fig.8.2: VEE= 5 V
4
T8 VCC = +5 V We can only continue by assuming that Q1 is working in the ACTIVE regime => VBE=0.7 V => Fig.8.2-A: RC 100 k IC VEE = IBR1 + VBE + ( +1)IBRE => IB Q1 VEE VBE 5 0.7 IB = = R1 + ( + 1) RE 1000 + 66 160 R1 IE 4 1 M 3.72 10 I = mA = 372 nA VBE= B 0.7 V I C = I B = 65 3.72 104 mA = 24.1782 A; RE=160 k 4 I I mA = 24.55 A = + 1 = 66 3.72 10 ( ) VEE = 5 V E B VC= VCC RCIC = 5 10024.1782103 2.582 V and VB= R1IB = 10003.72104= 0.372 V <<VC. Consequently, the C-B junction is reverse biased, hence our initial assumption of working in the active regime is valid. VCE= VCC+VEE RCIC REIE= 10 100 24.1782103 16024.55103 VCE= 3.654 V.
5
T8 Hence the quiescent operating point is: Fig.8.2-B: (24.1782 A; 3.654 V). RC S2) Simple small signal A.C. RS 100 k analysis: Passivate D.C. sources, consider 0.33 k only relevant capacitors (in this case all of them have zero reactance), redraw the vin R1 Q1 schematics for A.C.: 1 M
vout R3 220 k
Now we can replace the transistor with its equivalent small signal A.C. RIN model: RC RS 100 k C B 0.33 k
vin
Fig.8.2-C:
vbe
R1 1 M
r
E
rO
gmvbe
R3 220 k
vout
ROUT which can be re-drawn in a more convenient form:

6
T8 Fig.8.2-D: RS= 0.33 k
gmvbe vin
Rbe=R1| |r 65.0375 k
vbe
RL= RC | | R3 | | rO 66.684 k
vout
IC = 24.1782103 mA => gm= 38.467 24.1782103 0.9344 mA/V and r= 65/0.9344 = 69.56163 k => Rbe= R1 | | r = 65.0375 k.
VA + VCE 50 +3.654 ro = = = 2219.1064 k 3 IC 24.1782 10
RL = R3 | | RC | | rO = 66.684 k Rbe Rbe vout= gmvbeRL and vbe = vin vout = g m RL vin Rbe + RS Rbe + RS vout Rbe RL 65.0375 66.684 AV = = gm = 0.9344 62 vin Rbe + RS 65.0375 + 0.33
7
T8 Looking at the previous circuit in Fig.8.2-D it becomes clear that RIN= Rbe 65.04 k, and ROUT= RC | | rO = 95.68 k. 8.3- Draw the small-signal equivalent circuit of the commonemitter amplifier in Fig.8.3. What are the voltage gain, input resistance, output resistance and current gain if gm= 20 mS, = 75 and ro= 100 k? Solution: We begin by directly replacing vOUT the transistor with its equivalent small RS signal A.C. model: 0.5 k RC 12 k Q vin 1 R 15 k
B
Fig.8.3:
RE 0.2 k
T8 RIN1 RS=0.5 k B Fig.8.3-A: gmvbe rO C
iC vOUT
vin
iin R vIN1 R B IN iB 15 k
r vbe
ibe
E
RC 12 k ROUT
vE gm= 20 mA/V => r= 75/20 = 3.75 k RE 0.2 k rO= 100 k We can simplify our study of the circuit if we consider first the influence of RS and RB: RIN v IN 1 = vin and obviously RIN= RIN1 | | RB.
iE
RS + RIN
so that we can focus our attention only on the right-hand circuit with vIN1 as input. It is also evident that the presence of rO will significantly complicate calculations. Therefore, it is very relevant to establish what is the influence of rO on the final results. For this purpose we shall examine BOTH cases,
9
T8 without and with rO, respectively. Lets start with the simpler one, in which we neglect the presence of rO: iC= gmvbe => vOUT= RCiC= RC gmvbe vbe iC and vbe iE= iC + ibe= gmvbe+vbe/r= + 1 RE v r vIN1 ibe r gmvbe E At the same time iE vIN1= vbe + vE = vbe + REiE <=> i
Fig.8.3-B:
vOUT AV 1 = vIN 1
RE v IN 1 = vbe 1 + ( + 1) (1) r RC g m RC = = RE r R 1 + + ( ) E 1+ ( + 1)
RC
vOUT
75 12 AV 1 = 47.5 3.75 + 76 0.2

and
10
T8
v IN 1 RIN 1 = ibe
and inserting eqn.(1) and ibe= vbe/r in this relation =>
=>RIN1= 3.75+760.2= 18.95 k. Hence the overall input resistance is: RIN= RIN1 | | RB = 18.95 | | 15 8.373 k. Now we can finally calculate the total voltage gain.
RE vbe 1 + ( + 1) r = r + ( + 1) R RIN 1 = E vbe r
RIN v IN 1 RIN vin vin = Since v IN 1 = RS + RIN vOUT RS + RIN vOUT RIN RIN 1 1 = AV = AV 1 AV 1 RS + RIN AV RS + RIN
11
T8
8.373 AV = AV 1 0.94365 AV 1 = 44.82 0.5 + 8.373 iOUT The current gain is evidently defined as: AI = (2) iIN
with iOUT= gmvbe and, looking on the initial circuit in Fig.8.3-A, we can
v IN 1 v IN 1 RIN 1 + RB + = v IN 1 , in which we introduce (1): write iIN = RB RIN 1 RIN 1 RB RE r + ( + 1) RE + RB iIN = vbe 1 + ( + 1) r r + ( + 1) RE RB
r + ( + 1) RE + RB Using this relation together with the iIN = vbe r RB expression of iOUT and inserting them
in eqn.(2) we finally obtain AI:
12
T8
iOUT RB 75 15 AI = = AI = 33.14 iIN r + ( + 1) RE + RB 3.75 + 76 0.2 + 15

The only parameter we still need to calculate is ROUT. Lets remember what is the exact detailed procedure of calculating ROUT in ANY circuit: - Remove the load RL and replace it with a voltage source vX at the output terminals; - Note with iX the current due to vX (i.e. the current which is provided by the new voltage source); - At the same time, passivate the input signal source (vin or iin); - ROUT = vX/iX If we apply the same procedure, the modified circuit from which we need to calculate ROUT is: vbe
iX
RS | | RB=RSB Fig.8.3-C:
ibe
r iE
RE
vE
gmvbe
vX
13
T8 From Fig.8.3-C we can deduce the following relations:
RSB iX= gmvbe and vE= vbe RSBibe = vbe 1 + while at the same time r
+ 1) RE vbe ( + g m vbe = vbe vE = RE iE = RE ( ibe + g m vbe ) = RE r r

From these last two relations it results that
and therefore the only possible solution is vbe=0 => iX=0 =>ROUT = !!! Indeed, theoretically this is correct since the C-B junction is reverse biased, hence it should always provide an ideal infinite resistance. Practically, however, it is evident that this result is not realistic, and more detailed calculations need to be performed, now taking rO into account.
14
RSB RE vbe 1 + + ( + 1) = 0 r r
T8 For the sake of comparison, we repeat all previous calculations. The circuit to be considered in this case is obtained from Fig.8.3-A re-drawn in a more convenient form: vIN1= vbe + vE (3) vIN1 vbe vE= vO + vOUT (4) and vE= REiE (5). ibe r Also iC= gmvbe + iO => iO= iC gmvbe (6)
iC
iE vE
RE
iO
rO
gmvbe vOUT
RC
vOUT iO = g m vbe RC
gives
(6')
vO Using (6) in a re-written form of (4)

vE= rOiO + vOUT <=>
iC v = r vOUT + g v + v E O m be OUT RC
Fig.8.3-D:
rO vE = vOUT 1 + + g m rO vbe RC
(7)
15
T8 It is also evident that
vbe vout iE = ibe + iC = r RC
which we can insert in (5)
vbe vOUT vE = ( ibe + iC ) RE = RE RC r

vbe vOUT rO vOUT 1 + + g m rO vbe = RC RC r r RC + rO + RE (9). vbe = vOUT RC RE rO
(8).
RE
Now we can eliminate vE by equating (7) with (8):
By introducing the expression of vbe as given by (9) into (7) we obtain the expression of vE as a function of vOUT:
rO r RC + rO + RE vE = vOUT 1 + + g m rO vOUT RC RC RE rO
16
T8
vE = vOUT
RE RC + ( + 1) rO RC ( RE rO )
(10). Having now obtained the
expressions of vbe and vE by eqn.s (9) & (10), we can replace them in eqn.(1):
vIN 1 = vbe + vE = vOUT
RE RC + ( + 1) rO r RC + rO + RE + vOUT RC RE rO RC ( RE rO )
r ( RC + rO + RE ) + RE RC + ( + 1) rO v IN 1 = vOUT RC ( rO RE ) RC ( rO RE ) AV 1 = r ( RC + rO + RE ) + RE RC + ( + 1) rO (11)
12 ( 7500 0.2 ) AV 1 = = 46.315. 3.75 (12 + 0.2 + 100 ) + 0.2 ( 7600 + 12 )

17
T8 We must now determine RIN1 in order to calculate the overall AV and RIN:
v IN 1 v IN 1 RIN 1 = r and using eqn.(9) to insert the expression of vbe in = ibe vbe this relation => vIN 1r RIN 1 = r ( RC + rO + RE ) vOUT RC ( RE rO )
1 RC ( rO RE ) RIN 1 = AV 1 RC + rO + RE
12 ( 7500 0.2 ) 1 RIN 1 = = 17.32 k . 46.315 12 + 0.2 + 100

Hence the overall input resistance is: RIN= RIN1 | | RB = 17.32 | | 15 8.038 k. Now we can finally calculate the total voltage gain:
18
T8
RIN 8.038 AV = AV 1 AV = AV 1 46.315 0.9414 = 43.6 RS + RIN 8.038 + 0.5 vOUT iOUT with iOUT = and, looking The current gain is: AI = iIN RC
at the initial circuit in Fig.8.3-A, we can write
vbe vbe + vE vE iIN = ibe + iB = + = vbe ( r | | RB ) + r RB RB
We use again eqn.s (9) & (10) and introduce the expressions of vbe and vE in the relation above, resulting in:
RC + ( + 1) rO r + RB r RC + rO + RE vOUT RE iIN = vOUT + r RB RC RE rO RB RC ( RE rO ) iIN RC + ( + 1) rO ( r + RB )( RC + rO + RE ) + RE = vOUT RB RC ( RE rO )

19
T8
15 ( 7500 0.2 ) AI = 31.024 (15 + 3.75)(12 + 0.2 + 100 ) + 0.2 (12 + 7600 )
Again, the only parameter we still need to calculate is ROUT. The modified circuit from which we need to calculate ROUT is:
RB ( rO RE ) AI = ( r + RB )( RC + rO + RE ) + RE RC + ( + 1) rO
vbe
iX iE
RE vE
RS | | RB=RSB
ibe
iO
rO
gmvbe
vO iX From this circuit we can vX extract/deduce the
Fig.8.3-E:
following relations:
20
T8
ROUT
vX = iX
(11)
with iX= gmvbe+ iO while vX= vO + vE
(12) => iO= iX gmvbe (12), (13), with vE= REiE (14),
and iE= iX + ibe
(15). Combining (14) and (15) gives
RE vE = RE i X + vbe (16). r RSB At the same time, vE= vbe ibeRSB => vE = vbe 1 + (17), r
by equating (16) with (17) to eliminate vE we will finally obtain
so
RE r vbe = i X (18), which we can insert e.g. back in (16) r + RSB + RE to express vE as a function of iX: RE ( r + RSB ) RE RE r vE = RE i X iX vE = i X (19). r r + RSB + RE r + RSB + RE
21
T8 Also vE= iOrO = rO(iX gmvbe) and using again (18) =>
vO = i X
rO r + RSB + ( + 1) RE r + RSB + RE
(20).
Now we can use (19) and (20) and insert them back in (13), which ultimately leads to:
ROUT
r + RSB + ( + 1) RE + RE ( r + RSB ) v X rO = = iX r + RSB + RE
(21)
Here we can notice that there is a large difference between the two terms of the numerator: since both RE<<rO and r+RSB<< r+RSB+(+1)RE => the second term can be neglected, hence (21) can be expressed in a simpler form:
ROUT
RE rO 1 + (21') r + RSB + RE
22
T8
ROUT
Indeed, if we used (21), the result would be 438.496 k, proving thus that the error given by using the latter approximation is extremely small. CONCLUSION: Lets summarize all the results obtained in both cases: Parameter Without considering rO Taking into account rO 8.373 RIN [k] 8.038 47.5 AV1 46.3153 0.94365AV1= 44.82 AV 0.9414AV1= 43.6 31.024 AI 33.137 438.5 ROUT [k] !? These results clearly show that ROUT is the ONLY parameter that is radically different when rO is considered. Therefore, we must consider rO ONLY when calculating ROUT. It is NOT necessary to take into account rO when calculating all the other parameters.
75 0.2 = 100 1 + ROUT 438.305 k . 3.75 + 0.484 + 0.2
23
T8 8.4- The gate resistor RG in Fig.8.4 below is said to be bootstrapped by the action of the source follower. a. Assume that the MOSFET is operating with gm= 3.54 mS and ro can be neglected. Draw the small signal model and find the voltage gain AV, input resistance RIN and output resistance ROUT for the amplifier. b. What would RIN be if Av were exactly +1? a) Since the problem already V = 10 V DD Fig.8.4: Q provided us the gm, we do not need to 1 solve the D.C. bias problem, and can start C1= IDS with the remaining important part: vIN Simple small signal A.C. analysis: RG Passivate DC sources, consider only v 1 M R OUT relevant condensers, redraw the C2= D RL 2 k schematics for A.C. and replace the 100 k VSS= 10 V transistor with its small signal model:
24
T8 Fig.8.4-A: G D
vIN
vgs
gmvgs
S
RG R 1 M D 2 k
vOUT
RL 100 k The circuit can be re-drawn in a simpler and more convenient form: RG Fig.8.4-B: 1 M
For this latter circuit we can write: vIN = vgs + vOUT , and vIN
vOUT
v gs = RLD + g m vgs RG
vgs
vOUT gmvgs
RL | | RD=RLD 1.9608 k
25
T8 From the first eqn. we extract vgs and insert it into the second eqn.:
vIN vOUT vOUT = RLD + g m ( vIN vOUT ) RG RLD (1 + RG g m ) vOUT AV = = v IN RG + RLD (1 + RG g m )
1.96 (1 + 1000 3.54 ) AV = 0.8741 1000 + 1.96 (1 + 1000 3.54 ) v gs vin with iIN = iG = The input resistance is obviously RIN = iin RG
vin vin RG 1000 RIN = RG = RG = RIN = 7.943 M 1 AV 1 0.8741 vgs vin vOUT
26
T8 The last parameter we still need to calculate is ROUT. The modified circuit from which we need to calculate ROUT is: Fig.8.4-C: It is evident that RG 1 M
vgs
gmvgs
RD 2 k
iX vX
vX vX iX = + g m vgs RD RG
and that vgs= vX , hence
ROUT ROUT
b)
vX RG RD = = iX RG + RD + RG RD g m 1000 2 = 0.2475 k = 247.5 1000 + 2 + 1000 2 3.54

RG RIN = if AV =1 ! 1 AV
27
From the previous eqn. RIN =
Tutorial 9: A.C. circuits with MOSFETs & BJTs (3)
T9
9.1- What are the voltage gain, input resistance and output resistance for the amplifier in Fig.9.1? What is the maximum input signal for the amplifier? Use Kp= 200 A/V2 and VTP= 1V for your calculation. As usual, we must start first with: Solution: VSS= +15 V S1) D.C. analysis: We need first to RS calculate the D.C. quiescent point and be RI 68 k C = sure we are in saturation. 1 0.25 k VGS It is immediately visible that vIN VSS= RSIDS+VSG <=> VSG= VSS RSIDS <=> VGS= RSIDS VSS ,, and, if we assume ISD VSD Q1 is operating in saturation Kp Q1 2 C2= R RD 3 200 k 43 k VDD= 15 V Fig.9.1:
I DS =
(VGS VTP )
2
VGS = RS
Kp 2
(VGS VTP ) VSS

1
T9
2 VGS = 68 0.1 (VGS + 1) 15 6.8VGS + 12.6VGS 8.2 = 0 2
VGS 1 = 2.3632 V ; VGS 2 = 0.51 V

Since we have a PMOS, the first solution is obviously the only one with physical meaning (and for which clearly |VGS|>|VTP|). Then
I DS = I DS
Kp
2 = 0.185835 mA = 185.835 A
(VGS VTP ) I DS = 0.1 ( 2.3632 + 1)

2
It results that VSD= VSS+VDD (RD+RS)IDS => VSD= 30 (68+43)0.185 => VSD 9.37 V which means that |VDS|> |VGS||VTP|=1.632 V, hence Q1 is indeed operating in the saturation region. Now we can start S2) Simple small signal A.C. analysis:
2 I DS 2 0.185 gm = 0.273 mA gm = V 1.3632 VGS VTP
T9 Passivate D.C. sources, consider only relevant capacitors (in this case all of them have zero reactance), redraw the schematics for A.C.: RS 68 k RI 0.25 k Now we can replace the transistor with its equivalent small signal A.C. model: G D
vIN
Q1 R3| |RD= R3D 35.39 k Fig.9.1-A:
vgs
S RS 68 k Fig.9.1-B:
gmvgs vOUT
RI 0.25 k
R3D 35.39 k
vIN
which can be re-drawn more conveniently:

3
T9 Fig.9.1-C:
iI
vIN
RI= 0.25 k
iS
gmvgs vOUT
ROUT RD 43 k R3 RS 68 k 200 k
RIN1
RIN v gs
(No was given, and besides, IDS is very small => rO 1/IDS will be very large and thus can be neglected in the transistors equivalent small signal A.C. model). vOUT = gmvgsR3D and vgs= isRS. Also we can write that vIN= RIiI vgs, and iI= iS gmvgs => v IN
g m vgs R3 D RS vOUT with R3D= R3 | | RD <=> = AV = RI vgs g m vgs RI RS vgs RS vIN
v gs = RI g m vgs vgs RS
g m R3 D RS 0.273 35.39 68 AV = = 9.013 AV = RI + RS + g m RI RS 0.25 + 68 + 0.273 0.25 68

4
T9 The input resistance can be calculated as follows:
v IN RI v gs g m v gs RI RS vgs RS RIN 1 = = iI v gs g m v gs RS RS
RI + RS + g m RI RS 0.25 + 68 + 0.273 0.25 68 RIN 1 = = 3.726 k RIN 1 = 1 + g m RS 1 + 0.273 68 From previous Fig.9.1-C we notice that RIN1= RI+RIN => RIN= 3.476 k. The circuit necessary to calculate ROUT is: vX + g m v gs and iX = RD gmvgs Fig.9.1-D: iX gmvgs= vgs/(RI | | RS) <=> vX vgs[gm + 1/(RI | | RS)]= 0 => iS RI RD RS vgs=0 and hence vgs ROUT 0.25 k 68 k 43 k ROUT = RD= 43 k
5
T9 To calculate the maximum input voltage we remember from Tutorial 7 that the small-signal limit is:
v gs = 0.2 VGS VTP vgs = 0.2 ( 2.3632 + 1) = 0.27265 V

However, as we noticed in previous Fig.9.1-C, RIN1= RI+RIN =>
Rin Rin + RI vgs = vIN vIN = vgs Rin + RI Rin
3.476 + 0.25 vIN 0.27265 = 0.2923 V 3.476
T9 9.2- What are the midband voltage gain, input resistance and output resistance of the amplifier in Fig.9.2? Use = 100 and VA= 70V. VCC +15 V R7 R5 20 k R 3 R1 300 k 20 k Q2 C3= 300 k C5= R9 vOUT 100 k RS C = Q1 2 k 1 R6 vIN 180 k C4= R4 R8 R2 2 k 20 k 180 k R5 18 k Fig.9.2:
7
C2 =
Solution:
T9
S1) D.C. analysis: We need first to calculate the D.C. quiescent point and be sure we are in saturation. For each transistor the D.C. bias circuit is: We replace the RB1-RB2 group with a Thevenin VCC +15 V equivalent source (see again probl.6 in Tutorial 5): RB 2 VCC= +15 V RC IC Vth = VCC IC RB1 + RB 2 18 k RC RB1 20 k 300 k IB Q 180 Vth = 15 = 5.625 V I V 180 + 300 C Rth B Q1 Rth=R1 | | R2 => =>V RB2 VBE= th 180 300 180 k 0.7 V VBE= 0.7 V VE Rth = 180 + 300 = 112.5 k IE RE RE IE Vth= RthIB+VBE+REIE 20 k 20 k with IE= (+1)IB => Fig.9.2-A: Fig.9.2-B:
Vth VBE Vth VBE IB = IC = Rth + ( + 1) RE Rth + ( + 1) RE
T9
5.625 0.7 I C = 100 I C 0.231 mA 112.5 + 101 20 IC +1 101 IE = IE = IC = 0.231 = 0.23326 mA 100 and IB=IC/= 2.31 A; VE= REIE = 0.23120= 4.62 V => VB= VE+VBE 5.32 V and VC= VCC RCIC = 15200.231= 10.38 V => VCB= VCVB 5.06V, hence the C-B jct. is reverse biased, and consequently, each transistor is indeed in the active regime. Their Q-point is, therefore: IC 0.231 mA, and VCE 5.76 V.
T9 S2) Simple small signal A.C. analysis: Passivate D.C. sources, consider only relevant capacitors (in this case all of them have zero reactance), redraw the schematics for A.C.: R3 20 k RS 1 k RIN Q1 R4 2 k R56=R12 112.5 k R7 20 k Q2 ROUT
R9 100 k
vOUT
vIN
R12=R1| |R2 112.5 k Fig.9.2-C:
Now we can replace each transistor with its equivalent small signal A.C. model:
10
T9 RIN RS 2 k Fig.9.2-D: B1 R3 20 k C1 rO R7 20 k ROUT
vIN
vbe1
B2 v be2
r
R12=R1| |R2 112.5 k RS 2 k RIN E1 R4 2 k
r
gmvbe2
C2 vOUT rO R9 100 k
gmvbe1
R56=R12 E2 112.5 k
vbe1
which can be re-drawn more conveniently as: ROUT gmvbe1 ibe2 i4 rO iO1
vbe2 gmvbe2
vIN
R12 112.5 k
iin
r i
vin
be1
R7O= R9 rO| | R7 100 k
vOUT
Fig.9.2-E:
R356p=R56| |R3| |r R4 = 2 k 6.7691 k

11
T9 Instead of directly solving the circuit in Fig.9.2-E, we can further simplify it. In Problem 3 of the Tutorial #8, it was demonstrated that ro can be neglected when calculating any parameter except ROUT. Therefore, we can simplify our calculations here as well by adopting the same procedure and neglect rO of Q1. In such a case, the circuit can be re-drawn as: RIN RIN1 ROUT RS vbe1 Fig.9.2-F: gmvbe1 2 k gmvbe2 vOUT ibe2 vbe2 vIN r R356p R4 iin R7O= R9 i 4 R12 R | |R | | r 2 k 56 3 rO| |R7 100 k v in 112.5 k 6.7691 k
IC 100 mA gm = 38.467 I C = 8.884 r = = 11.256 k V kT / q g m 8.884 VA + VCE 70 +5.76 ro = = 328 k RL = R7 | | R9 | | rO 15.86 k IC 0.231 (16.67 k if we neglect rO of Q2 as well)
12
T9 Also, as in previous problems
vin ' = vIN
RIN RIN + RS
RIN (1) AV = AV ' RIN + RS
(1')
As noticed earlier, the whole amplifier consists of two identical stages, hence we can consider AV=AV1AV2. For the first stage vout1 = vin2 = vbe2= gmvbe1R356p (2), while for the second one it is evident that vout2 = vOUT= gmvbe2RL (3), and that ROUT= ro | | R7 = 18.85 k. The expression of vbe2 can be deduced starting from the relation vin= vbe1 + R4i4 (4), with i4 given by
vbe1 + g m vbe 2 (5). i4 = r
By inserting (4) into (3), we obtain:
R4 r vin ' = vbe1 + vbe1 + g m vbe1R4 vbe1 = vin ' (6), r r + ( + 1) R4

which we can substitute back in eqn.(2) to calculate AV1:

13
T9
AV 1 ' =
r + ( + 1) R4
g m R356 p r
8.884 6.7691 11.256 (8) AV 1 ' = 3.174 11.256 + 101 2
Since (3) can be re-written as vout2 = gmRLvbe2 = gmRLvin2 (3) => AV2= gmRL = 8.88415.86= 140.907. Consequently, AV=AV1AV2 =3.174 140.907 => AV= 447.238.
vin ' vin ' vin ' For the input resistance RIN = = = r and using again ibe1 vbe1 ibe1 r eqn.(6) it results that
RIN 1 = r + ( + 1) R4 (9) RIN 1 = 11.256 + 101 2 = 213.256 k
The circuit also shows that RIN= RIN1| |R12 => RIN 73.648 k. Finally, the complete total voltage gain is calculated using (1):
RIN 73.648 AV = AV ' = 447.238 = 435.41 RIN + RS 75.648

14
T9 IF so desired, we can repeat the calculations for greater accuracy by considering ro in the calculations. In this case, looking back again at Fig.9.2-E it can be seen that:
ibe 2
vbe 2 = = g m vbe1 iO1 (10), R356 p
and vbe2= rOiO1+R4i4 =>
vbe 2 R4 iO1 = i4 rO rO
(11). At the same time, ibe1= i4 + ibe2 <=>
R356 p vbe1 r vbe 2 vbe1 vbe 2 = i4 + i4 = r R356 p R356 p r
(12).
Inserting eqn.(12) in (11) one obtains
iO1 =
R356 p + R4 R356 p rO
R4 vbe 2 vbe1 (13), r rO

15
which we now insert back in eqn.(10), leading to

T9
R356 p + R4 vbe 2 R4 = g m vbe1 vbe 2 + vbe1 R356 p R356 p rO r rO vbe 2 = r ( rO + R4 + R356 p ) R356 p ( rO R4 ) vbe1 (14).
From Fig.9.2-E it can also be seen that vin= vbe1+R4i4 (4), and inserting here the relation for i4 given by previous eqn. (12), provides
vin ' = vbe1 + R4
R356 p vbe1 r vbe 2 R356 p r
r + R4 R4 vin ' = vbe1 vbe 2 (15), r R356 p

in which we can insert eqn.(14) obtained above =>
16
T9
r + R R r R ( ) R O 4 4 + 4 356 p vin ' = vbe1 vbe1 r R356 p r ( rO + R4 + R356 p ) vbe1 =
( r + R4 ) ( rO + R4 + R356 p ) + R4 ( rO R4 )
( r + R4 ) ( rO + R4 + R356 p ) + R4 ( rO R4 )
R356 p ( rO R4 )
r ( rO + R4 + R356 p )
vin ' (16).
Having obtained this relation between vin and vbe1, we can insert it back in eqn.(14) to obtain the relation between vin and vbe2:
vbe 2 =
vin ' (17),
which can be substituted in eqn.(3) to finally calculate the voltage gain:
g m RL R356 p r ( rO R4 ) vOUT AV ' = = vin ' ( r + R4 ) ( rO + R4 + R356 p ) + R4 ( rO R4 )
(18)
17
T9
8.884 15.86 6.7691 11.256 ( 32800 2 ) AV ' = (11.256 + 2 )( 328 + 2 + 6.7691) + 2 ( 32800 2 ) AV ' 446.497. In order to find out the total final voltage gain AV, we must first determine the input resistance RIN. vin ' vin ' For this, we can write RIN 1 = = r (19), and using (16)
R4 ( rO R4 ) it results that RIN 1 = r + R4 + rO + R4 + R356 p RIN 1 = 208.0363 k
ibe1
vbe1
(19)
Since RIN= RIN1| |R12 = 208.0363 | | 112.5 => RIN 73.0154 k. Finally, the complete total voltage gain is calculated using (1):
RIN 73.0154 AV = AV ' = 446.497 = 434.59 RIN + RS 75.0154
18
T9 9.3- Fig.9.3 shows a three-stage amplifier. Find the midband voltage gain, input resistance RIN and output resistance ROUT of this amplifier. What is the input signal range for this amplifier? Use = 100, VA= 70 V, Kn= 1 mA/V2, VTN =1 V and = 0.02 V1 for all BJT and n-MOS transistors. VCC= +15 V R5 RC2 Q3 R3 RC1 4.7 k 910 k R1 C6 = 18 k 160 k = C Q2 3 820 k C5 = vOUT R 6 RS C = RL 1 Q 1.2 M 1 R4 10 k RE3 250 43 k vIN 3 k R2 C4 = RE2 100 k 1.6 k = 100, VA= 70V; RE1 2, V K = 1 mA/V n TN =1 V C2 = 2 k Fig.9.3: and = 0.02 V1
19
Solution:
VCC= +15 V RC IB Q
VBE= 0.7 V
B1
T9
S1) D.C. analysis: We need first to calculate the D.C. quiescent point and be sure we are in the active regime and saturation, respectively. For each transistor the D.C. bias circuit is: Just as in previous Problem 9.2 we replace the R -R
B2
group with a Thevenin equivalent source:
IC
VCC= +15 V RC IC VC Q
Vth = VCC
RB1
RB 2 RB1 + RB 2
RB2
=> IE
Rth IB Vth
RE Fig.9.3-A:
VBE= 0.7 V VE RE I E Fig.9.3-B:
100 820 Rth1 = = 89.13 k 100 + 820

Vth1= Rth1IB1+VBE1+RE1IE1 with IE1= (+1)IB1 =>
100 Vth1 = 15 = 1.63 V 100 + 820 Rth1= RB1 | | RB2 =>
Vth1 VBE Vth1 VBE I B1 = I C1 = Rth1 + ( + 1) RE1 Rth1 + ( + 1) RE1
20
T9
1.63 0.7 I C1 = 100 I C1 0.3196 mA 89.13 + 101 2 IC +1 101 IE = I E1 = I C1 = 0.3196 = 0.32279 mA 100 and IB1=IC1/= 3.196 A; VE1= RE1IE1 = 0.322792= 0.64558 V => VB1= VE1+VBE 1.35 V and VC1= VCC RC1IC1 = 15180.3196= 9.25 V => VCB1= VC1VB1 7.9 V, hence the C-B jct. is reverse biased, and consequently, the Q1 transistor is indeed in the active regime. The Q-point of Q1, therefore, is: IC1 0.3196 mA, and VCE1
7.25V. All the calculations can then be repeated for Q2:
21
T9
Vth 2 43 160 43 = 15 3.18 V and Rth2= R3 | | R4 => Rth 2 = = 33.89 k 160 + 43 160 + 43 3.177 0.7 101 1.267 = 1.28 mA = 100 I C 2 1.267 mA I E 2 = 33.8916 + 101 1.6 100
IC 2
and IB2=IC2/= 12.672 A; VE2= RE2IE2 = 1.281.6= 2.048 V => VB2= VE2+VBE 2.75 V and VC2= VCC RC2IC2 = 154.71.267 9 V => VCB2= VC2VB2 6.3 V, hence the C-B jct. is reverse biased, and consequently, the Q2 transistor is indeed in the active regime. The Q-point of Q2, therefore, is: IC2 1.267 mA, and VCE2 6.3 V.
We need now to analyze the NMOS transistor:
22
T9 VCC= +15 V Q3 R5 910 k VDS IDS VG= VGS + RE3IDS (20), with VG = VCC
1200 = 8.53 V 1200 + 910 and VCC= VDS + RE3IDS (21). We assume that Q3 is in saturation =>
VG = 15 R6 R5 + R6
VG VGS R6 1.2 M RE3 3 k Fig.9.3-C:
I DS
Kn 2 = (VGS VTN ) 2
and combining it with (20) results in
Kn 1 2 2 VG = VGS + RE 3 (VGS VTN ) 8.53 = VGS + 3 (VGS 1) 2 2 2 4VGS 14.062 = 0 VGS 1 = 2.932 V ; VGS 2 = 1.6 V . 3VGS
Obviously, only the first solution is realistic and in accordance with the circuits details. Inserting the VGS1 value back in eqn. (20) provides IDS:
23
T9
VG VGS 8.53 2.932 I DS = VCC I DS = = 1.866 mA RE 3 3 and VDS= VCC RE3IDS = 1531.866 9.4 V VGS VTN = 1.932 V, hence Q3 is indeed in saturation. Thus the Q-point of Q3 is: IDS= 1.866 mA and VDS= 9.4 V. We can now move ahead with the A.C. analysis of the initial circuit shown in Fig.9.3. Clearly, it is composed of 3 cascaded one-transistor stages. However, the analysis of the overall circuit has to be done backwards, i.e. from the output towards the input, because the input resistance of each stage has to be considered when calculating the load at the output of the preceding stage. Consequently, we shall start our A.C. analysis with stage #3. Passivate D.C. sources, consider only relevant capacitors (in this case all of them have zero reactance), redraw the A.C. schematics of stage #3 from which we shall calculate ROUT and the gain & input resistance RIN3 of this stage:
24
T9 Fig.9.3-D: Fig.9.3-E: Q3
vin3
gm3vgs vgs
S RE3| |RL
D ro3 31.83 k
vin3
RG= R5| |R6
=>
vOUT
RG= R5| |R6
RE3 RL 3 k 250
vout3= vOUT
1 ro 3 =
+ VDS I DS
which can be redrawn as:
vin3
vgs
RG= R5| |R6
Fig.9.3-F: vout3
50 + 9.4 = 31.833 k ro 3 = 1.866 g m 3 = 2 K n I DS (1 + VDS ) = 2 11.866 (1 + 0.02 9.4 ) = 2.10565 mA

gm3vgs
RLS= RE3| | RL | | ro3
25
T9 RLS= RE3| |RL | | ro3= 0.2291 k; RG= R5| |R6 = 910 | | 1200 = 517.536 k. We can also write the following relations: vout3= gm3vgsRLS (22) vin3= vgs+vout3=> vgs= vin3 vout3 (23) From both (22) and (23) => vout3= gm3RLS (vin3 vout3) <=> vout3 = gm3RLSvin3 gm3RLSvout3 =>
vout 3 g m3 RLS 2.10565 0.2291 AV 3 = = = = 0.32542 vin 3 1 + g m3 RLS 1 + 2.10565 0.2291

iX
The circuit from which ROUT can be calculated is the following one: vgs3= vX and Fig.9.3-G: vgs3 rO3| |RE3
gm3vgs3
vX
vX g m3vgs 3 iX = RE 3 | | rO 3 1 iX = v X + g m3 RE 3 | | rO 3
26
T9
1 ROUT
iX 1 = = + g m 3 ROUT = v X RE 3 | | rO 3
1 1 + g m3 RE 3 | | rO 3
RE3 | | rO3= 3 | | 31.833 = 2.7416 k => ROUT = 1/(2.10565+0.3647)= =404.793 . Obviously, Rin3= RG= 417.536 k, and it will be necessary to consider it by adding it to the load of the preceding stage 2. We can now analyze in a similar manner the 2nd stage. Lets draw first the A.C. circuit: vout2 Q2 RIN3 RC2 vin2 417.536 k 4.7 k R34= R3| |R4 Now we can replace the transistor with Fig.9.3-H: its equivalent small signal A.C. model:
27
T9
vin2
R34= R3| |R4
B2
vbe2
E2
r 2
C2 vout2
gm2vbe2
RL2= rO2| |RC2| |RIN3
Fig.9.3-I: IC 2 100 mA 38.467 I C 2 = 48.9662 r 2 = = 2.0422 k gm2 = V kT / q g m 2 48.9662 VA + VCE 2 70 +7 ro 2 = = 60.77 k RL 2 = RC 2 | | RIN 3 | | rO 2 4.326 k 1.267 IC 2 vout2= gm2vbe2RL2 and vin2 = vbe2 => AV2 = gm2RL2 = 48.96624.326 => AV2 = 211.83 and Rin2= R34||r2= (160| |43)| |2.0422= 1.926 k Finally, the 1st stage can be analyzed as well. Its A.C. schematic and the subsequent circuit resulting after replacing the transistor with its equivalent small signal A.C. model are as follows:
28
T9 RS 10 k RIN Q1 RC1 18 k vout1 RIN2 1.926 k
vIN
Fig.9.3-J: RS 10 k
iin vin1 R12= R1| |R2

RIN R12= R1| |R2 vbe1
vIN
Fig.9.3-K:
gm2vbe2 v out1
iin vin1
r 1
RL1= rO1| |RC1| |RIN2
VA + VCE1 70 +8.6 ro1 = = 245.93 k RL1 = RC1 | | RIN 2 | | rO1 1.728 k 0.3196 I C1
29
I C1 100 mA 38.467 I C1 = 12.3517 r 1 = = 8.096 k g m1 = V kT / q g m1 12.3517
T9
RIN 1 vout1 vout1 RIN 1 RIN 1 = AV 1 = AV 1 vin1 = vIN RIN 1 + RS vIN vin1 RIN 1 + RS RIN 1 + RS
while vout1= gm1vbe1RL1 and since vin1 = vbe1 => AV1`= gm1RL1 => AV1 = 12.35171.728 => AV1 = 21.34 and RIN= Rin1= R12||r1= (100| |820)| |8.096= 7.422 k. Therefore, the overall gain is: AV= AV1AV2AV3= 21.34211.8350.32542 = 1471.079 =>
AV = AV
RIN 1 7.42185 = 1471.079 = 626.692 RIN 1 + RS 17.42185
The input signal range is limited by the small signal limit of the last stage. As this 3rd stage is MOS-based, the small signal condition is expressed as: vgs0.2(VGS VTN) <=> vgs0.2(2.932 1)= 0.3864 V. We also saw that vin3= vgs+vout3= AV3vin3 + vgs => vgs=(1AV3) vin3,
vIN RIN 1 and vin3 = vout2 = AV2AV1vin1 = AV 2 AV 1 RIN 1 + RS

30
T9
RIN 1 vin 0.2 (VGS VTN ) (1 AV 3 ) AV 2 AV 1 RIN 1 + RS vIN MAX vIN MAX 0.2 (VGS VTN )( RIN 1 + RS ) = (1 AV 3 ) AV 2 AV 1 RIN 1
0.2 ( 2.932 1) 17.42185 = 297.436 V (1 0.32542 ) 211.835 21.34 7.422
31
T9 9.4. Fig.9.4-A shows the C-E/C-B cascode circuit. It is used in high gain amplifiers and high output resistance current sources. Derive the expressions of r, gm, and ro of the single transistor equivalent hybrid- model of the cascode circuit (shown in Fig.9.4-B) in terms of the small signal B C parameters of transistors Q1 and Q2. Q1 Q2 vOUT <=> vbe' r r O
vin
Fig.9.4-A:
Fig.9.4-B:
gm'vbe
Q2
Solution:
In order to deduce the and gm parameters of the equivalent transistor we need to analyze the D.C. behaviour of the cascode circuit, as shown in Fig.9.4-C:
IC1=IE2 IB =IB1
B Q1
IC =IC2
C
IE1
Fig.9.4-C: E
IB2 IE
32
T9 For the circuit in Fig.9.4-A we can easily see that IC1 =1IB1 = IE2 (24), and
IC As we know that, by definition, g m = , hence, using in this relation VT I I C C 1 2 2 eqn. (28) it results that g m = = = g m1 g m1 VT 2 + 1 VT 2 + 1
At the same time, IC =IC2 , IE2=IC1 and I C = I E = I E ( 27 ) ,while +1 2 2 we can also write similarly that I C = I C 2 = IE2 = I C1 ( 28 ) . 2 + 1 2 + 1
IE2 IC = IC 2 = 2 2 + 1 2 1 I C = 1 = I B 2 + 1
( 25), and combining (24) & (25) =>
( 26 ) ,
IF 2 >> 1.
We can now proceed to find the small signal parameters of the equivalent transistors hybrid- circuit. For this we need to draw the A.C.
33
T9 cascode circuit after replacing the equivalent small signal circuits of each transistor: B vbe2 gm1vbe1 rO2 r2 C vin= vbe1 r r O1 gm2vbe2 <=> 1 Fig.9.4-D: vOUT E which can be redrawn as: gm2vbe2 vbe=vbe1 C B vbe2 r 1 rO1| |r2 rO2 After comparing Fig.s 9.4-B and 9.4-E it is evident that Fig.9.4-E: gm1vbe1 r= r1. E The only parameter we still need to find out is rO. How can we find it out? We know how to calculate the output resistance ROUT of a circuit. Can we use the same method to extract rO in this case? (In other words, is rO indeed the output resistance exhibited by a transistors small signal equivalent circuit?). Lets verify it by applying it for a simple transistor!
34
T9 B
gmvbe
C r O
iX vX
vbe
E Fig.9.4-F: B
vbe1
gm2vbe2 vbe2
Clearly vbe=0 => gmvbe=0 => ROUT = ro. Consequently, we can apply the same procedure to deduce ro from the previous circuit shown in Fig.9.4-E, which will be transformed as shown in Fig. 9.4-G below:
iX
C
r 1
E Fig.9.4-G:
rO1| |r2 rO2
vX
gm1vbe1
Here also vbe1=0 => gm1vbe1= 0 => the circuit simplifies as shown in Fig. 9.4-H:
gm2vbe2 vbe2
Fig.9.4-H:
RPO12= rO1| |r2
rO2
iX vX
35
v2
T9 As in the previous Tutorials, we can use 2 methods to calculate rO: with and without considering the (first) transistors output resistance ro1. i) ro1 is neglected In this case RPO12 = r2 hence vbe2 appears across r2 alone and we can write vX = v2 vbe2 (29), while
(30a), and v2 1 vbe 2 g m 2 + = vbe 2 r 2 ro 2 (30b) iX = r 2 2 + 1 (31) which we introduce back in (29), resulting in v2 = vbe 2 ro 2 r 2 ro 2 ( 2 + 1) v2 iX = g m 2 vbe 2 + ro 2
ro 2 ( 2 + 1) v X = vbe 2 1 + ROUT r 2 vbe 2 1 + r 2 vX = = ro = vbe 2 iX r 2
36
T9 rO= r2 + rO2(2+1) (32).
ii) ro1 is taken into consideration In this case vbe2 appears across RPO12= r2| |rO1, which means that eqn.(30b) must be modified accordingly (replace r2 with RPO12). However, eqn.s (29) and (30a) remain unchanged. Carrying out a similar reasoning as previously, from combining (30a) and the modified eqn.(30b) one obtains
ro1 ( 2 + 1) + r 2 ro1 + r 2 vbe 2 v2 = vbe 2 ro 2 (31') and iX = ro1r 2 ro1r 2
(32 ')
ro1 ( 2 + 1) + r 2 v X = vbe 2 1 + ro 2 (33') . Combining eqn.s (32) & ro1r 2 (33) gives
which can be obtained either directly applying Ohms law for RPO12, or by introducing eqn.(31) back in (30a). At the same time, introducing (31) in (29) results in
37
T9
ROUT
ro1r 2 + ro 2 ro1 ( 2 + 1) + r 2 ro 2 ro = ro1 + r 2
ro1 ( 2 + 1) + r 2 vbe 2 1 + ro 2 ro1r 2 vX = = ro = ro1 + r 2 iX vbe 2 ro1r 2
38
Author: Assoc. Prof. Poenar Daniel Puiu AddT10 Recapitulation:

vC1 RC IC1 Q1 IC2 Q2 I VEE Modes of operation: Output: Input: 1) Differential mode: vC1 vC2; A) Common mode: vB1= vB2; B) Differential mode: vB1 vB2; 2) Single-end: vC1 or vC2 b.1- Small signal; b.2- Large signal. RC VCC vC2 Differential Amplifiers Loads: Passive (resistors) or active (current mirrors);
vB1 (vin-diff /2)
Emitter current source: Passive (resistor) or active vB2 (current source/sink); (vin-diff /2)
Author: Assoc. Prof. Poenar Daniel Puiu AddT10 Recapitulation (continued):

iC Linear region I (small input signal)
Q1 Q2
0V
Differential RC IC1 E IC2
VCC RC vC2
vC1
Q1
Q2 vE = + =?
vB1 vB 2 VT
vin-diff = vB1 vB2 RE VEE
0 E=Virtual ground Small input signal <=> vbe<< VT <=> vin-diff << 2VT Two identical halves => simplify Large input signal => Q1,2 = ON/OFF analysis by considering only one => =>
=>

vC1 RC Q1 E
vin-diff = vB1 vB2
Common mode VCC RC IC1 Q1 E RE VEE IC2 Q2 vE = + =? RC vC2
RC VCC Q2 vC2
vC1 vCM
Differential mode
Q1
VCC RC vout
=>
DIFFERENTIAL vin-diff /2 HALF-CIRCUIT
=>
E= Two identical halves => simplify analysis by considering only one => =>

RC Q1 E 2RE VEE Q2 RC vC2 VCC
Common mode
vC1 vCM
vCM VCC 2RE VEE => vCM RC voutCM Q1 2RE VEE
Common-mode Half-circuit

Be careful and notice if the circuit has differential or single-ended output. The previous analysis and circuits considered a differential output. In such a case, the half circuit and its corresponding output voltage will be: RC voutTot vout1 Q1 Q2 RC VCC vinput= vB1 = vin-diff /2 Q1 RC voutput= vout1
vin
Clearly, vinput=vbe=vin-diff/2 and voutput= gmvbeRC => AVD= voutput/vinput= vout-diff/(vin-diff /2)= gmRC, or AVD= RC/re. It can be noticed that the gain in differential mode calculated using the half-circuit is identical with the total differential gain of the complete circuit !!
This is because voutput= voutTot=vC1 vC2=vout1 vout2, but we know that in differential mode vC2 = vC1 => Total differential gain is:
Author: Assoc. Prof. Poenar Daniel Puiu AddT10 Recapitulation (continued): vout Tot vC1 vC 2 2vC1 2vout1 vout1 AVD Tot = = = = = = AVD Half circuit vin vin vin vin vin 2
It can be easily realized thus that, for differential output, solving only the half-circuit will provide us exactly the same voltage gain as for the entire circuit, hence the practical importance of using the half-circuit. However, if the output of the entire circuit is single-ended, then obviously the output voltage will be only voutput= vC1 = vout1 => for the complete initial vout1 circuit we will now have: AVD Tot Single ended =
vin
whereas solving the half-circuit will obviously provide voutput Half circuit vout1 2vout1 AVD Half circuit Single ended = = = = 2 AVD Total Single ended vinput Half circuit vin vin 2
Author: Assoc. Prof. Poenar Daniel Puiu AddT10 Recapitulation (continued): Analysis of Op-Amp Problems: A) Input signals for differential & common-mode half-circuits: vin-diff = vD = vB1 vB2; vin-CM = vCM = (vB1+ vB2)/2; B) Calculate gains for differential output: AD, ACM and CMRR:
AD = vout diff vin diff , ACM = vout diff vin CM AD , CMRR = ACM
C) Differential output signal by superposition: vout = AD.vD+ ACM.vCM
Author: Assoc. Prof. Poenar Daniel Puiu AddT10

A more detailed representation is presented below. The following notes go beyond the simplified picture previously shown, and complete it. For a differential amplifier with two inputs and two outputs, the two-port representation used for single-transistor amplifiers is not applicable. Instead, a three port representation is needed, as shown below:
vin1 = vB1 vin2 = vB2
Differential Amplifier
vout1 vout2
As mentioned earlier, the two inputs vin1 and vin2 can be always decomposed into differential and common-mode components, vin-diff and vin-CM, vin-diff = vD = vB1 vB2; respectively, defined as:
vin-CM = vCM = (vB1+ vB2)/2;

meaning that
vin1 = vin-CM + vin-diff /2; vin2 = vin-CM vin-diff /2;
Author: Assoc. Prof. Poenar Daniel Puiu AddT10 vin-diff /2

The same relations apply to the input currents: iin1 iin 2 vin-diff /2 iin diff = ; vin1 2 vin-CM vin-CM vin2 iin1 + iin 2 iin CM = 0V 2 The input voltages and currents are related by the input impedances:
Rin diff =
vin diff iin diff

vinCM = 0
Rin CM
vin CM = iin CM
vindif = 0
As usually Rin-CM>> Rin-diff , the three-port input of the operational amplifier can be represented by the equivalent circuit shown in the next figure.

Rin-CM
2Rin-diff
vin-CM vin-diff iin2 vin2
iin-dif
vout-CM
Rout-CM RL-CM
Rin-CM
iin-CM
vout-diff iout2
2iout-CM vout2 R
out-diff
In the same manner it can be shown that the output voltages and currents can be decomposed into differential and common components and that two output impedances can be defined, one for each component. The outputs of the differential amplifier can be loaded either symmetrically or asymmetrically. Consequently, the differential and common output voltages can be related to the input voltages with the following more exact relations:
2RL-diff
vin-diff
vin1
vout-diff
vout1
RL-CM
iin1
iin-CM
iout1
Rout-diff
Author: Assoc. Prof. Poenar Daniel Puiu AddT10 vout-diff = ADD.vin-diff + ADC.vin-CM vout-CM = ACD.vin-diff + ACC.vin-CM
ADD = ACC vout diff vin diff
vinCM = 0
where
is the differential mode gain
vout CM = vin CM vout diff vin CM
is the common mode gain

vindif = 0
ADC =
vindif = 0
is the common-to-differential mode transfer gain
is the differential-to-common mode transfer gain vinCM = 0 Under conditions of ideal symmetry, both transfer gains should be =0.
ACD
vout CM = vin diff

Differential amplifiers are commonly used when a desired differential mode signal is superimposed on a large fluctuating common-mode signal. The next figure shows a possible application where the differential amplifier is used with a bridge circuit & an oscilloscope to measure a slight unbalance caused by a small change in resistance R. The oscilloscope and the power supply must have a common terminal. Thus, it is important that the oscilloscope responds only to the difference mode component input (vin1 vin2)/2, which can be in the range of mV or lower, and not to the CM component which can be in the range of V. vout1= vout-diff +vout-CM= vin-diff (ADD+ACD)+vin-CM(ACC+ADC) R vin1 R E
Differential Amplifier
vout1
RR (e.g.: temperature or pressure sensor, etc.)
vin2
Y GND X

Since the desired signal is usually the differential signal, the response to the CM signal produces an error at the output that is indistinguishable from the signal. Therefore, the minimization of both ACC and ADC are extremely important objectives in differential amplifiers design. The effect of finite transfer gains on the amplifier response can be described by the common-mode rejection ratio CMRR and the differentialmode rejection ratio DMRR:
CMRR=
ADD ADC
DMRR=
ACC ACD
IF the differential amplifier is loaded symmetrically, only the differential output voltage appears across the load, because vin CM vout diff = vout1 vout 2 = 2 vin diff ADD + vin CM ADC = 2 ADD vin diff + CMRR It can be clearly seen that higher the CMRR, the more independent vout-diff becomes from the effect of the CM input voltage.

However, for a single-ended load (load applied between one of the two outputs and GND), the output will be a function of both CM and differential input components, and vout = vout-diff +vout-CM , as it is also shown in the figure of the previous example with the oscilloscope. Consequently, in such cases it is necessary to have the CM input rejected as much as possible, i.e. one must have ADD>>ACC. The degree to which this requirement is met by a given differential amplifier is specified using the discrimination factor, defined as: A
F=
DD
ACC
Tutorial 11: Current Mirrors & Active Loads
T11
11.1- Fig.11.1.1 shows an input differential BJT amplifier with a single-ended output. (a) Derive the amplifiers voltage gain AV without the use of the small signal model in terms of gm and ro , given that the npn transistors Q1 and Q2 are identical and pnp transistors Q3 and Q4 are also identical. State your assumptions, if any. (b) Prove that the voltage gain is independent of the tail current 2I, given that the Early voltage of the pnp transistor is VAP and that of the npn is VAN. State your assumptions, if any. (c) If VT = 25 mV at room temperature, 2I = 100 A and VAP = VAN = 100 V, find the gain of the amplifier. If 2I = 200 A, what is the gain? State your assumptions, if any. (d) Fig.11.1.2 shows an input differential amplifier using MOS transistors. Compare the characteristic difference with the BJT-based implementation.
1
T11 Given that Kn= Kp= 40 mA/V2, N = P = 0.01 V1, with 2I = 100 A, find the voltage gain of the amplifier. If 2I = 200 A, what is the gain? State your assumptions, if any. Solution: VCC a) Assume that the of both the Q4 Q3 I+gm1vin/2 npn & pnp transistors are both vout very high such that the base I+gm1vin/2 current can be neglected. Then, Igm1vin/2 io=gm1vin IC1=IC2=IC3=IC4=I, while vin ic 4 = ic 3 = ic1 = g m1 vin/2 Q1 Q2 2 vin/2 vin vin ic 2 = g m 2 = g m1 2I 2 2 Fig.11.1.1: io = ic 4 ic 2 = g m1vin so that
vout
vout = g m1vin Ro where Ro = ro 2 | | ro 4 , hence Av = = g m1 ( ro 2 | | ro 4 ) vin
T11
ro 2 ro 4 Av = g m1 (1). ro 2 + ro 4
VA + VCE VA b) If we approximate ro = then (1) becomes IC IC VAN VAP ro 2 ro 4 I C1 I C 2 I C 4 = Av = g m1 and because I C1 = I C 2 = I C 3 = I C 4 = I ro 2 + ro 4 VT VAN VAP + IC 2 IC 4
VA 1 VAN VAP = Av = ( 2 ) if VA = VAN = VAP . VT VAN + VAP 2VT Thus, it can be concluded that, considering the same assumptions as at point (a), the voltage gain AV remains the same irrespective of the current I. VA 100 c) Applying eqn. (2) leads to: Av = = = 2000, i.e. 66 dB. 3 2VT 50 10
3
T11 Obviously, as was just stated previously, the voltage gain is independent on the magnitude of the current I, hence AV will not change its value if 2I changes from 100 to 200 A. d) A similar reasoning can be applied for the MOS-based circuit: VDD Av = g m 2 Ro = 2 K n I ( ro 2 | | ro 4 ) M M
3 4
I+gm1vin/2
I+gm1vin/2 Av = 2 K n I vout Igm1vin/2 M1 M2 vin/2 2I

= 2Kn I 2I = Kn
io=gm1vin
1 1 + ro 2 ro 4 If we approximate
(3)
1 rO =
+ VDS I DS
vin/2 Fig.11.1.2:
1 Av = 2 K n I N I 2 + P I 4
1 I DS
then (3) becomes

2I
with = N = P and I 2 = I 4 = I .
4
T11 It can be seen that, in contrast with the BJT-based differential amplifier which has a gain independent from the bias current I, the MOSFET differential amplifier exhibits a gain inversely proportional to the square root of the bias current in the transistor. With the given specific parameters, the value of AV for the MOS input differential amplifier results as: 40 Av = 100 = 2000 ( = 66 dB) for a current 2I = 100 A, and 0.1 AV= 1414.214 ( = 63 dB) for a current 2I = 200 A, respectively. The variation of the ideal gain AV with the bias current I for both the BJT- & MOS implementations is represented A Fig.11.1.3: V graphically in Fig.11.1.3. It can be seen BJT that the performance for the BJT is superior for most of the cases. However, MOSFET differential amplifiers offer MOS much higher input impedance and very 2I low input currents.
5
T11 11.2- What are the output currents and output resistances for the current sources in Fig. 11.2, if Kn = 25 A/V2, VTN= 0.75 V and = 0.015 V1 ? VDD IREF +12V +10V +8V 30 A I2 I3 I4 I1 M1 4:1 Fig.11.2: M2 10:1 M3 20:1 M4 40:1
2 I DS 1 60 Clearly, for M1 VDS 1 = VGS 1 = VTN + = 0.75 + = 1.5246 V , 25 4 W Kn and VGS1=VGS2=VGS3=VGS4=VGS. L 1

6
Solution:
T11 For all the transistors which share the same VGS we can write the following relations K W 2 W
(VGS VTN ) (1 + VDSk ) (1 + VDSk ) 2 L k Ik L k = = I1 W K n W 2 1 + VDS1 ) ( + 1 V V V ( ) ( ) GS TN DS 1 L 1 2 L 1

n
with k= 2, 3, 4; VDS1=VGS (because of the diode-connected transistor configuration), I1 = IREF , and the VDSk values are the bias voltages applied on the drains of the transistors Mk. Introducing the numerical values one W obtains: (1 + V )
DS 2 L 10 (1 + 0.015 10 ) 2 I REF = 30 A = 84.322 A For M2: I 2 = 4 (1 + 0.015 1.5246 ) W L (1 + VGS ) 1 1 1 10 V + + DS 2 0.015 = 909.217 k . Similarly, for M = and ro 2 = 3 I2 84.322 106
T11
W L (1 + VDS 3 ) 20 (1 + 0.015 8 ) 3 For M3: I3 = 30 A = 164.244 A I REF = 4 (1 + 0.015 1.5246 ) W + 1 V ( ) GS L 1
1 1 + + V 8 DS 3 0.015 = = 454.608 k = r and o3 I2 164.244 106

W L (1 + VDS 4 ) 40 (1 + 0.015 12 ) 4 For M4: I 4 = 30 A = 346.085 A I REF = 4 (1 + 0.015 1.5246 ) W L (1 + VGS ) 1
and ro 4
1 1 + VDS 4 0.015 + 12 = = 227.304 k = I2 346.085 106

8
T11 11.3- What are the output currents and output resistances for the current sources in Fig.11.3, if = 50 and VA= 50 V? VDD IREF +12V Fig.11.3: +10V +8V 100 A IC4 IC2 IC3 IC1
Solution:
Q1 A1=A
Q2 A2=2.5A
Q3 A3=5A
Q4 A4=10A
Clearly, for Q1 VBE1=VCE1 and VBE1=VBE2 = VBE3=VBE4 = VBE. Because of current mirroring, for all the transistors which share the same VBE we can write the following relation:
I Ck = I C1 Ak I S e A1 I S e
VBE VT
VBE VT
VCEk VCEk VCEk Ak 1 + 1 + Ak 1 + V V V A A A = I Ck = I C1 ( 4 ) VCE1 VCE1 VCE1 A A + + 1 1 1 1 1 + V V V A A A
T11 with k= 2, 3, 4. However, IREF IC1 because of the base currents that appear due to finite , so that IC1 IC2 IC3 IC4 + + + = I REF = IC1 + I B1 + I B2 + I B3 + I B4 = IC1 +
VCE 2 VCE 3 VCE 4 A 2 1 + A3 1 + A 4 1 + VA IC1 VA IC1 VA IC1 IC1 = IC1 + + + + VCE1 VCE1 VCE1 A1 1 + A1 1 + A1 1 + V V V A A A VCE 2 VCE 3 VCE 4 1 1 = IC1 1 + + A 2 1 + + A3 1 + + A 4 1 + V V V V A A A A1 1 + CE1 VA Introducing the numerical values one obtains:
10
T11
1 1 8 10 12 I REF =IC1 1 + + 2.5 1 + + 5 1 + + 10 1 + = 0.7 50 50 50 50 50 1+ 50 = IC1 1 + 0.02 + 0.019724 ( 3 + 5.8 + 12.4 ) = 1.438146 IC1 IC1 = 0.69534 I REF = 0.69534 100 A = 69.534 A
Using now eqn.(4) for each transistor Qk results in:
IC 2
VCE 2 10 A2 1 + 2.5 1 + VA 50 = 69.534 = 205.722 A I C1 = 0.7 VCE1 1+ A1 1 + 50 VA

VA + VCE2 60 ro2 = = = 291.656 k; 3 IC2 205.722 10
11
T11
VCE 3 8 A3 1 + 5 1 + VA 50 IC 3 = I C1 = 69.534 = 397.73 A 0.7 VCE1 1+ A1 1 + 50 VA VA + VCE3 58 ro3 = = = 145.828 k, and 3 IC2 397.73 10 VCE 4 12 A4 1 + 10 1 + V 50 A IC 4 = I C1 = 69.534 = 850.317 A 0.7 VCE1 1+ A1 1 + 50 VA VA + VCE4 62 = = 72.914 k. ro4 = 3 IC2 850.317 10 In conclusion, the accuracy of the current mirror depends on , VA, and the number of transistors connected to the same diode-connected transistor.
12
T11 11.4- (a) Derive the output resistance ROUT of the cascode current mirror in Fig.11.4. State your assumptions necessary in order to ensure that the circuit exhibits a large ROUT value. (b) What is the lowest voltage limit of VD3-min at the drain of M3 if all the transistors should V D3 VDD be in the saturation region? IREF ROUT (c) If IREF = 17.5 A , VDD = 5 V, I0 Kn = 75 A/V2, VTN= 0.75 V, and = 0.0125 V1, find: M3 M4 - the numerical value of VD3-min VG3 as in part (b), and - ROUT if the drain voltage of M3 is connected to VDD . M2 Solution: a) In the modified circuit that M1 VG2 is necessary to calculate ROUT, we assume Fig.11.4: that the IREF source offers an ideal infinite
13
T11 A.C. resistance and we also need to replace M1 and M4 with their equivalent circuits. Therefore, it is necessary to determine first the output resistance offered between G & S by the diode-connected transistors M1 and M4 using Fig.11.4-A, from which it can be easily deduced that vgs= vX vX iX 1 1 Fig.11.4-A: iX = = g m vX + and iX = g m v X + G D rO RO v X rO vX gmvgs rO rO 1 vgs RO = S 1 + rO g m g m ROUT Consequently, the initial circuit can be simplified as shown in Fig.11.4-B. Fig.11.4-B: However, since ig3=0 => vgs2=0 => ig3 M3 gm2vgs2=0 and G3GND => after replacing M3 as well with its equivalent small RO4 G2 gm2vgs2 signal circuit, the output resistance can be rO2 deduced from the further simplified RO1 vgs2 circuit shown in Fig.11.4-C:
14
T11 Fig.11.4-C: gm2vgs2 rO3 iX From this circuit we can see that vgs3= iXrO2 and v x + v gs 3 i X = g m 3 v gs 3 + vX rO 3 and after combining these two relations one ultimately obtains ROUT= rO2+rO3+gm3rO2rO3 rO3(1+gm3rO2) gm3rO2rO3.
vgs3
rO2
b) Assuming all the MOSFET transistors have identical W/L ratios and they operate in the saturation region, since they all have the same drain currents they will also exhibit identical VGS values:
VGSi
with i = 14. Hence the gate voltage of M3 and M4 is
2I REF = VGS = VT + = VT + V0 if we denote Kn
2I REF = V0 . Kn
VG3 = VG4 = VGS1 + VGS4

2I REF = 2VGS = 2VT + 2 = 2 ( VT + V0 ) Kn

15
T11 and the drain-to-source voltage of M2 is VDS2 = VG3 VGS3 = 2VGS VGS = VT + V0 . For M3 to remain in the saturation region the condition VDS3 VGS3 VT must be obeyed. Consequently, the lowest acceptable value of VDS3 is VDS3-min = VGS3 VT = V0 and, therefore, the minimum external bias voltage VD3 necessary to be applied at the drain of M3 which does NOT set M3 into the triode/linear operating region is VD3-min= VDS2 + VDS3-min = VT +V0 + V0 = VT +2V0 . c) Inserting the values in the relations previously deduced we obtain:
V0 = 2 I REF = Kn 2 17.5 = 0.68313 V 75
VGS = VT + V0 = 0.75 + 0.683313 = 1.43313 V
and therefore, the minimum external bias voltage VD3 necessary in this case is VD3-min= VDS2 + VDS3-min = VT +2V0 = 0.75 + 20.68313= 2.1163 V. If VD3=VDD, for the output resistance we need to calculate rO2,3 and gm3:
16
T11
1 ro 2 = + VDS 2 I D2 1 + 1.43313 = 0.0125 = 4.6533 M 6 17.5 10
VDS 3 = VD 3 VDS 2 = VDD VDS 2 1 ro 3 = + VDS 3 I D3 1 + 5 1.43313 = 0.0125 = 4.77525 M 6 17.5 10
g m3 = 2 K n I D3 (1 + VDS 3 ) = 2 75 106 17.5 106 1 + 0.0125 ( 5 1.43313) g m3 = 5.23645 105 = 5.23645 102 mA
Ro g m3 ro 2 ro3 = 5.23645 105 4.6533 106 4.77525 106 = 1.1636 G
)(
)(
17

Analogue Electronics Op-Amp Circuits Analysis

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Analogue Electronics Op-Amp Circuits Analysis

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Author: Assist. Prof.

Poenar Daniel Puiu

Analogue Electronics (E2002)

Author: Assist. Prof. Poenar Daniel Puiu Recapitulation:

Tutorial 2: Op-Amps (2)

R2 ( vOUT )1 = A vIN = v peak sin t = ( 10 ) 0.1sin t = 1 sin t [mV ] R1

R2 ( vOUT )2 = Anoninv vIO = 1 + vIO = 11[mV ] R1 2 vOUT = ( vOUT )i = 11 sin t [mV ]

The (qualitative) graphical representation of the output signal is:

Assist.Prof. Poenar Daniel Puiu

Assist.Prof. Poenar Daniel Puiu

Again, using the linear superposition principle we have:

R2 ( vOUT )1 = Anoninv VIO = 1 + VIO R1

Consider only I+ and passivate VIO and I:

R2 = 1 + VIO + R2 ( I I + ) and it was given R1

that IIO=0; since IIO= I+ I =0 => I+ = I => vOUT= 3VIO = 6 mV.

T2 R1 vS RS R2 vOUT a) The ideal gain is: Anoninv

Consider only I+ and passivate VIO and I:

R2 ( vOUT )1 = Anoninv VIO = 1 + VIO R1

c) When vS0, the total output becomes

Assist.Prof. Poenar Daniel Puiu

T2 d) Since the ideal gain is Anoninv

R2 = 1+ = 5 R2= 100 k, R1= 25 k. R1

( vOUT ) D.C . = Anoninv (VIO I + RS ) + R2 I

component of the previously deduced output voltage is:

AnoninvVIO + R2 I 5 2 mV + 100 k 0.12 A 22 RS = = = = 55 k Anoninv I + 5 0.08 A 0.4

(V/A = => V/mA =k => mV/A =k)

SR parameter is irrelevant to this calculation that deals with D.C. outputs.

R2 = 1 + VIO = 51 10 mV = 510 mV . Note that the R1

Assist.Prof. Poenar Daniel Puiu

R2 R4 R2 R4 = vS + 1 VIO R1R3 R1R3

Assist.Prof. Poenar Daniel Puiu

dvOUT dvOUT = 0.5 cos t max = 0.5 dt dt

0.5MAX = SR MAX = 2 SR = 2 10 rad

Assist.Prof. Poenar Daniel Puiu

f MAX 318 kHz

4VP 4VP SR 106 Ainv SR T Ainv f = = 500 kHz 2 T SR 4VP Ainv 4 10 50

T2 vOUT VP=0.5 V 0 0.5 s T/2 Time t

Assist.Prof. Poenar Daniel Puiu

500 k R2 vOUT 50 k R1 I+ RTH 50 I 500 k R2 vOUT

R2 = ( I + RTH ) 1 + + I R2 = 1 A 50 11 + 1 A 500 103 = R1

Assist.Prof. Poenar Daniel Puiu

Assist.Prof. Poenar Daniel Puiu

Tutorial 3: Op-Amps (3)

vOUT ACL DC 20 = =2 ACL ( 600 kHz ) = ( 600 kHz ) = vIN 10 10

R2 20 = 1+ =2 b) The closed-loop gain of the circuit is: ACL = 1 + R1 20

R1 = 0.5 (1). Also, since = R1 + R2

0.35 0.35 = = 6 = 0.35 s << t (2) BWCL 10

Assist.Prof. Poenar Daniel Puiu

Assist.Prof. Poenar Daniel Puiu

ACL AP SR (3) MAX

Assist.Prof. Poenar Daniel Puiu

SR ACL AP SR (3) ACL MAX AP

Assist.Prof. Poenar Daniel Puiu

Aplying it for v2 yields

SR 5 105 = = 28.57 5 MAX AP 3.5 10 0.05 SR 5 105 ACL 3 = = 25 5 MAX AP 2 10 0.1

while for v3 we obtain

Assist.Prof. Poenar Daniel Puiu

Assist.Prof. Poenar Daniel Puiu

Assist.Prof. Poenar Daniel Puiu

Assist.Prof. Poenar Daniel Puiu

Assist.Prof. Poenar Daniel Puiu

A( s ) vIN + vOUT = sRC vOUT [1 + A( s )] vOUT sRC [1 + A( s )] 1} = A( s ) { vIN

Assist.Prof. Poenar Daniel Puiu