ALGORITHM FOR ASYMMETRIC SOURCE CONFIGURATION IN A NEWLY CONSTRUCTED MULTISTRING MULTILEVEL INVERTER TOPOLOGY

Krishna Kumar Gupta*, Shailendra Jain

*Maulana Azad National Institute of Technology Bhopal, India, * kk_mact@rediffmail.com, sjain68@gmail.com

Keywords: Multilevel inverters, cascaded H-bridge topology, reduced device count, symmetric and asymmetric source configurations.

Abstract
This paper proposes an algorithm to configure asymmetric sources for a recently proposed topology for multilevel inverters. Since the topology proposed by Yi-Hung Liao et. al [8] is incapable of synthesising all additive and subtractive combinations of input DC levels (as happens in cascaded Hbridge inverter), various popular asymmetric configurations cannot be employed for it. The proposed algorithm is described in detail and it is shown that it helps to synthesise multilevel waveform with equal sized steps.

topology offers advantages such as improved output waveforms, smaller filter size, lower EMI and lesser total harmonic distortion (THD). However, in literature [8], the treatment of the aforesaid topology was limited to a five level output with symmetrical input DC sources. In this paper, a generalised structure of the topology is presented in Section 2. This section also discusses the concept of symmetric and asymmetric source configurations in MLIs. In Section 3 an algorithm is proposed for asymmetric source configuration for the proposed topology. Simulation results for the proposed algorithm are shown in Section 4. Conclusions are presented in Section 5.

2 Generalised Structure of Topology Proposed in [8]

As shown in Fig.1 (a), the topology in question contains six active switches and two isolated DC sources for a five level output. An alternative structure of this topology is shown in Fig.2. It can be noted that the consecutive sources are crossconnected i.e. the higher potential terminal of source Vs1 is connected to the lower potential terminal of the source Vs2 through a power switch. Similarly, the higher potential terminal of source Vs2 is connected to the lower potential terminal of source Vs1 through a power switch. A similar scheme of connections can be extended for increased number of input DC sources. For n number of DC sources, the generalised structure of the topology is shown in Fig. 3. It would need 2n + 2 power switches. For the same number of DC sources, a CHB topology would require 4 n power switches [9]. The DC sources Vsk (k = 1 to n) can be configured as symmetric or asymmetric. A brief description of source configuration is made below. 2.1 Source Configurations in MLIs The concept behind a multilevel waveform synthesis is to utilise multiple input DC sources. Multiple input DC sources can be obtained mainly in two ways: (i) using electrically isolated DC sources. (ii) using multiple capacitors in series so as to sub-divide the input voltage from a single DC source. The first approach leads to requirement of large number of sources. Also, equal load sharing among them is a desirable and challenging task. On the positive side, there are no voltage balancing problems. The second approach does not

1 Introduction
Multilevel voltage source inverters are considered costeffective and efficient solution especially for high power/medium voltage DC to AC conversion. A multilevel inverter (MLI) utilises multiple input DC sources to synthesise a staircase waveform. As a result of this approach, voltage stresses across the power switches are lower as compared to the output voltage level. Moreover, the stepped waveform exhibits a better harmonic profile as compared to a two level waveform produced by the conventional inverters. Other advantages of using MLIs are higher efficiency, reduced dv/dt stresses on the load and possibility of fault tolerant operation [1, 2]. An important limitation of MLIs is requirement of increased number of power semiconductor devices (and accompanying gate driver circuits) for increased number of output levels [3]. This makes the overall system expensive and complex. Therefore, practical implementation of MLIs demands reduction in number of switches and gate driver circuits. As a result, attempts have been made by researchers to propose newer topologies with reduction in device count [4-8]. Focus of work presented here is a recently proposed MLI topology for distributed energy resources (DERs) [8]. Yi Hung Liao et. al [8] have proposed a newly-constructed fivelevel multistring inverter topology for DERs. As shown in Fig.1 (a), the aforesaid topology requires only six active switches instead of the eight required in the conventional cascaded H-bridge (CHB) multilevel inverter (Fig.1 (b)). It was established in [8] that the newly-constructed inverter

need many DC sources but capacitor voltage balancing remains an important issue especially for increased number of levels in the output.

Vs1

Vs1

+ vo _ Vs2
Vs2

iL + vO

AC LOAD

_
Vs n-1

(a)

Vdc

Vs n

+ vo _

Fig.3. Generalised structure for the topology proposed in [8] (a) Symmetric Source Configuration: When all the input DC sources have equal values, the configuration is designated as a symmetric source configuration. That is, Vs1 = Vs2 = ... = Vsk = ... = VDC (1)

Vdc

(b) Fig.1. (a) Five level inverter as proposed in [8] (b) CHB topology for five level output

SU

S U

Based on the topology, such configuration may offer advantages like modularity and possibility of equal load sharing amongst the sources. However, for a given number of output levels, such configuration needs more power switches as compared to an asymmetric configuration.
iL +

1
Vs1

S1

S1'

AC LOAD

vN

_ 2
Vs2

SL

SL

Fig.2. Alternative form for the structure shown in Fig.1 (a) The topology discussed in this paper uses the first approach, namely, using multiple isolated input DC sources. Based on their values, the source configuration are categorised as:

(b) Asymmetric Source Configuration When two or more of the input DC sources have unequal values, the configuration is designated as an asymmetric source configuration. Such a configuration enables lesser number of power switches to be used for the same number of output levels as compared to a symmetric configuration. However, it may lead to loss of modularity (if any) in the structure. Also, it may not always be possible to achieve equal load sharing amongst the sources [10]. Some of popular asymmetric source configurations are [10,11]: (i) Binary configuration: It consists of DC sources having a geometric progression with a factor of 1/2 i.e.
1 2

2 3

==

( 1)

= 2

(2)

Binary configuration does not permit equal load sharing amongst the sources.
400

Output Voltage [V]

(ii) Trinary configuration: It consists of DC sources having a geometric progression with a factor of 1/3 i.e.
1 2

300 200 100 0 -100 -200 -300 -400 0.1 0.11 0.12 0.13 Time [sec] 0.14 0.15 0.16

2 3

==

( 1)

= 3

(3)

Trinary configuration does not permit equal load sharing amongst the sources. (iii) As proposed in [10]: In this configuration, one source has voltage VDC while all other sources have values 3VDC, that is, Vs1 = Vs2 =... = Vsk =...=Vsn-1= 3VDC; and Vsn = VDC (4)

Fig.5. Output voltage waveform for a two-cell CHB inverter with trinary configuration (Vs1 = 100 V and Vs2 = 300 V)

Ouput Voltage [V]

Such a configuration partially incorporates the advantages of trinary configuration along with the possibility of equal load sharing. (iv) As proposed in [11] : In this configuration, one source has voltage VDC while all other sources have values 2VDC, that is, Vs1 = Vs2 =... = Vsk =...=Vsn-1= 2VDC; and Vsn = VDC (5)

400 300 200 100 0 -100 -200 -300 -400 0.1 0.11 0.12 0.13 Time [Sec] 0.14 0.15 0.16

Such a configuration partially incorporates the advantages of binary configuration along with the possibility of equal load sharing. 3 Proposed Algorithm for Source Configuration As mentioned in the previous section, using an asymmetric configuration leads to further reduction in number of switches in a given topology with separate DC sources. However, for the proposed topology, the asymmetric configurations discussed in previous section cannot be implemented satisfactorily. For example, if the multistring topology is simulated using a trinary source configuration with Vs1 = 100 V and Vs2 = 300V, all expected nine levels (-400V to 400V, in steps of 100V each) are not synthesised. For a nine-level inverter, carrier and reference signals are shown in Fig 4. Such a configuration in CHB would synthesise nine levels shown in Fig 5. However the multistring topology synthesises seven levels with unequal step-sizes as shown in the simulated waveform in Fig. 6.
4

Fig.6. Output voltage waveform for the multistring inverter with trinary configuration (Vs1 = 100 V and Vs2 = 300 V) Similarly, if the multistring topology is implemented using trinary configuration with three sources, the source values would be: Vs1 = 100 V, Vs2 = 300V and Vs3= 900V. Such a configurations offers possibility of twenty-seven levels (1300V to 1300 V in steps of 100V each) which is achieved with the CHB topology. However, the multistring topology generates only fifteen levels viz. 0, 100, 300, 400, 800, 900, 1200 and 1300 V. The aforesaid discussion indicates that the commonly used asymmetric configurations cannot be implemented for the multistring topology. The reason is that it does not synthesise all additive and subtractive combinations of the input DC levels. This can be inferred from Table 1. There are some voltage levels which are skipped. Therefore, an appropriate algorithm for asymmetric source configuration is required which can synthesise maximum number of steps with equal step size.

Reference and Carrier Waveforms

3 2 1 0 -1 -2 -3 -4 0.1 0.105 0.11 0.115 0.12 Time [sec] 0.125 0.13 0.135 0.14

In order to obtain a multilevel waveform with equal step-size, the aforesaid topology needs to use a natural number sequence of sources i.e. VDC , 2VDC , 3 VDC , .... , nVDC. Moreover, placing the sources at the correct positions is equally important. It is determined that the position of sources has to be as shown in Table 2, shown for up to ten DC sources.

Fig.4. Reference and carrier waveforms for a 9-level inverter

Number of Sources

Source Designation

Possible Voltage Levels

1 2

Vs1 Vs1, Vs2

Vs1, Vs2, Vs3

0 (Vs1) 0 Vs1 Vs2 (Vs1 - Vs2) (Vs1 + Vs2) 0 Vs1 Vs2 Vs3 (Vs1 + Vs2) (Vs1 Vs2) (Vs1 + Vs3) (Vs1 Vs3) (Vs2 + Vs3) (Vs2 Vs3) (Vs1 + Vs2 + Vs3) (Vs1 + Vs2 Vs3) (Vs1 Vs2 + Vs3) (Vs1 Vs2 Vs3)

Presence of Voltage Level in the Multistring Topology Present Present Present Present Present Missing Present Present Present Present Present Present Missing Missing Present Present Missing Present Missing Missing Missing

Total number of possible combinations 3 9

Total number of possibilities offered by the Multistring Topology 3 7

27

15

Table 1. Additive and subtractive combinations of input values and their presence/absence in the multistring topology

Number of Sources 1 2 3 4 5 6 7 8 9 10

Source Designation and their Values Vs1 VDC VDC VDC VDC VDC VDC VDC VDC VDC VDC Vs2 2VDC 3VDC 3VDC 3VDC 3VDC 3VDC 3VDC 3VDC 3VDC Vs3 Vs4 Vs5 Vs6 Vs7 Vs8 Vs9 Vs10

2VDC 4VDC 5VDC 5VDC 5VDC 5VDC 5VDC 5VDC

2VDC 4VDC 6VDC 7VDC 7VDC 7VDC 7VDC

2VDC 4VDC 6VDC 8VDC 9VDC 9VDC

2VDC 4VDC 6VDC 8VDC 10VDC

2VDC 4VDC 6VDC 8VDC

2VDC 4VDC 6VDC

2VDC 4VDC

2VDC

Table 2 Proposed placement of voltage sources in the proposed topology for up to ten number of input sources

Accordingly, the proposed algorithm for asymmetric source configuration in the multistring structure is: (i) For even number of sources: Vsj = (2j - 1) VDC, for 1 j (n/2), = 2(n +1 j) VDC, for [( n + 2 )/2] j n (ii) For odd number of sources:
io(t) + _

(6)

Vs1 = 100V

Vsj = =

(2j - 1) VDC, for 1 j [(n + 1)/2], 2(n +1- j) VDC, for [(n + 3)/2] j n
Vs2 = 300V

(7)
+ _

4 Simulation Results and Comparison with Symmetric Configuration

In order to substantiate the algorithm proposed in the previous section, some simulation studies are carried out using MATLAB/Simulink. (i) Simulation Study I Two sources with Vs1 = 100V and Vs2 = 200V are used for the multistring structure and it is expected that it can synthesise seven levels in equal steps of 100V. Simulation is carried out with these values and the results are shown in Fig.7. The results indicate that a seven level waveform is obtained with a peak value of 300V and in equal steps of 100V.

Vs3 = 400V

Vs4 = 200V

Fig. 8 Multistring topology with four asymmetric sources

1000

300 200
Ouput voltage [V] Ouput Voltage [V]

500

100 0 -100 -200 -300 0.1 0.11 0.12 0.13 Time [sec] 0.14 0.15 0.16

-500

-1000 0.1 0.11 0.12 0.13 Time [sec] 0.14 0.15 0.16

Fig.9. Voltage waveform for Simulation Study II

Fig.7. Voltage waveform for Simulation Study I (ii) Simulation Study II Another inverter is simulated based on the multistring topology with the following source values: Vs1 = 100V, Vs2 = 300V, Vs3 = 400V and Vs4 = 200V as shown in Fig. 8. The output waveform is expected to consist of twenty-one levels with an amplitude 1000V and in equal steps of 100V. The simulated voltage waveform is shown in Fig.9. It is seen that the output waveform achieves amplitude of 1000V in equal steps of 100V.

It can also be noted that for a seven level output, the topology would require eight switches with symmetric source configuration and six switches with the proposed algorithm for asymmetric configuration. Also, for a twenty-one level output, the topology would need twenty-two switches with symmetric source configuration and ten switches with asymmetric source configuration as proposed in the paper. Thus, asymmetric source configuration would further reduce the device count. A general comparison between number of switches and number of voltage levels produced by the multistring topology for the symmetric and the proposed asymmetric configurations are shown in Fig.10.

+ +

_ _

vo(t)

AC Load

100

80

Number of Levels in Output Waveform

With proposed asymmetric configuration

60

40

With symmetric configuration

20

10 12 14 16 18 20 Number of Power Switches Fig 10. Number of power switches versus number of levels synthesized in the multistring topology with symmetric source configuration and with proposed configuration
[5] Ceglia G., Guzman V., Sanchez C., Ibanez F., Walter J., Gimenez M.I.: A New Simplified Multilevel Inverter Topology for DC to AC Conversion. IEEE Transactions on Power Electronics, , vol.21, no.5, pp.1311-1319, Sept. 2006. [6] Babaei E.: A Cascade Multilevel Converter Topology With Reduced Number of Switches. IEEE Transactions on Power Electronics, vol.23, no.6, pp.2657-2664, Nov. 2008. [7] Hinago, Y. and Koizumi, H., A single -phase multilevel inverter using switched series/parallel DC voltage sources, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 26432650, Aug. 2010. [8] Yi-Hung Liao and Ching-Ming Lai, Newly-constructed simplified single-phase multistring multilevel inverter topology for distributed energy resources, IEEE Trans. Pow. Electron., vol. 26, no. 9, pp. 23862392, Sep. 2011. [9] Gupta, K.K. and Jain, S., Theoretical analysis and experimental validation of a novel multilevel inverter topology for renewable energy interfacing applications , J. Renewable Sustainable Energy (AIP), 4, 013113 (2012), DOI:10.1063/1.3683515 [10] Laali S., Abbaszadeh K., Lesani H.: A new algorithm to determine the magnitudes of dc voltage sources in asymmetric cascaded multilevel converters capable of using charge balance control methods. Electrical Machines and Systems (ICEMS), 2010 International Conference on , vol., no., pp.56-61, 10-13 Oct. 2010. [11] Babaei E., Hosseini S.H.: Charge balance control methods for asymmetrical cascade multilevel converters. Electrical Machines and Systems, 2007. ICEMS. International Conference on , vol., no., pp.74-79, 8-11 Oct. 2007.

0 4

5 Conclusion
This paper presents a newly formed algorithm for asymmetric source configuration in a recently proposed multistring topology by Yi-Hung Liao et. al [8]. A generalized structure of the multistring topology is formulated. It is shown that the popular asymmetric configurations are not employable for the multistring topology since it does not synthesize all additive and subtractive combinations of the input DC values. The proposed algorithm is shown to satisfactorily synthesize all voltage levels with equal sized steps. It is shown that the proposed algorithm significantly reduces the number of power switches (and associated gate driver circuits).

References
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