Advanced Techniques For Digital Receivers

National Workshop on Recent Trends in RF and Microwave Techniques and Measurements
Nivin R Sci./Eng. SD Radio Frequency Systems Division Vikram Sarabhai Space Centre Indian Space Research Organisation
Introduction Communication Receivers Digital Receiver Block Diagram Digital Down Conversion (DDC) Direct Digital Synthesis (DDS) Intermediate Frequency (IF) Sampling Over Sampling using - ADCs Digital Radio Frequency Memories Under Sampling Digital Receivers Direct Conversion Receiver Conclusion
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Advanced Techniques for Digital Receivers
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1. 2. 3. 4. 5. 6.
Crystal video Instantaneous frequency measurement Super heterodyne Homodyne Channelized Compressive (microscan)
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A receiver is a device that collects propagating RF signals using an antenna and then distributes the signal to special conditioning circuits in order to isolate and measure a particular parameter of interest. The receiver processing requirements for various signals of interest depend on the receiver applications and the information required.
RF Amplifier
Mixer
Filter
IF Amplifier
Demodulator Audio Amplifier
Local Oscillator
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1. 2. 3. 4. 5.
Selectivity: The ability to isolate a particular signal Instantaneous bandwidth Frequency resolution Sensitivity: Ability to detect a weak signal Dynamic Range: Ratio of largest to smallest signal power that may be processed
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Advancements in ADC and the increase in digital signal processing speed. The input is down converted into an IF, which is then digitized with high-speed ADCs with large number of quantization levels. Digital Signal Processing is used to demodulate the signal. More robust because there is no temperature drifting, gain variation, or dc level shifting as in analog circuits. circuits.
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The critical building block of any digital receiver is the Analog to Digital Conversion (ADC) process. In order to convert signals in a wideband receiver, the ADC must operate at a very high sampling speed. To digitize signals with less quantization errors, the ADC must also have a large number of bits. It is difficult to achieve both goals in an ADC at the same time. High speed ADC outputs must be processed by highspeed digital circuits. Parallel processing may solve the speed problem. Design receivers with only RF amplifiers and band pass filters between the antenna and the ADC.
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Fixed relative to the sample frequency, and will not change with time or temperature. Coefficients for a digital filter-identical filter-implement the same length filter with the same coefficients. Identical filters are particularly useful in quadrature sampling systems. The use of Field Programmable Gate Arrays (FPGAs) means that while developing your system if, for example, the filter characteristics are not quite right, all that is required is to reconfigure the FPGA with a different filter. Dedicated hardware would most likely require component changes.
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Antenna RF
Pre Amplifier Down Converter
IF Data
ADC DSP/FPGA
Local Oscillator
Reference Oscillator Frequency Synthesizer
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The output of the preamplifier stage must be down converted to a frequency compatible with the ADC technology.
How many stages of down conversion should be employed in order to obtain the IF signal appropriate for digitization?
A single stage is preferable since image rejection is easier, filtering requirements are lower, and circuit design is less complex. The drawback is that the total gain requirement must be divided between only two gain stages (one at RF and the other at the output IF frequency), thus running the risk of amplifier instability. A second problem with single down conversion is that if the large LO signal is parasitically coupled into the input path, it will swamp the received signal. A two-stage down conversion design spreads the gain over three amplification stages and the LO is more effectively isolated from the received signal. Three stages of down conversion would require more filtering in the signal path, resulting in unnecessarily complex design.
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Translation of the down converted IF signal to the in-phase and quadrature components of the signal envelope is known as base band processing.
Base band Sampling Block Diagram f0 IF AGC 0 f0 Q LPF ADC LPF I ADC DSP/ FPGA
Analog Coherent Detector

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90 IF f0 Advanced Techniques for Digital Receivers 11/40
IF sampling, sometimes referred to as direct analog to digital conversion , is another method of sampling that digitizes the I and Q samples directly.
AGC Filter
IF BPF
AGC AMP
Sample & Hold
ADC
DSP/ FPGA
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Can yield an improvement in overall SNR by eliminating the analog coherent detector stage. Since the I and Q samples are generated from the same circuitry, there are no phase and gain imbalances between them. Only one ADC is required and it must sample at greater than twice the Nyquist rate. The aperture time of the sampling process must be small with respect to the period of the IF frequency. The sample rate must be high enough so that there is no significant delay between I and Q. At the ADC output, an FIR filter is used to interpolate I or Q samples to obtain time aligned I,Q pairs at the output data rate. The accuracy of the estimated I or Q samples is determined by the complexity and the coefficients of the FIR filter.
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A fundamental part of many communications systems is Digital Down Conversion (DDC). It is a technique that takes a band limited high sample rate digitized signal, mixes the signal to a lower frequency and reduces the sample rate while retaining all the information. Digital receivers often have fast ADC converters to digitize the band limited RF or IF signal generating high data rates; but in many cases, the signal of interest represents a small proportion of that bandwidth. To extract the band of interest at this high sample rate would require a prohibitively large filter. A DDC allows the frequency band of interest to be moved down the spectrum so the sample rate can be reduced, filter requirements and further processing on the signal of interest become more easily realizable.
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The output from the Digital Down converter has retained all the information in our frequency band of interest but has moved it down to base band and so allowed the sample frequency to be greatly reduced. This has the advantage of simplifying any further processing on the data, together with the gains of possibly time shared functions within the FPGA due to the lower clock frequency, so allowing more processing to be fitted into the FPGA. The lower effective clock frequency will reduce the power requirement for the FPGA.
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Digital stability not affected by temperature or manufacturing processes. With a DDC, if the system operates at all, it works perfectly theres never any tuning or component tolerance to worry about. Controllability all aspects of the DDC are controlled from software. The local oscillator can change frequency very rapidly indeed in many cases a frequency change can take place on the next sample. Additionally, that frequency hop can be large there is no settling time for the oscillator. Size - A single ADC can feed many DDCs, a boon for multi-carrier applications. A single DDC can be implemented in part of an FPGA device, so multiple channels can be implemented or additional circuitry could also be added.
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ADC speeds are limited - It is not possible today to digitise high-frequency carriers directly. There are techniques to extend the range of ADCs, but often it is simpler to use analog circuits to bring the carrier down to an IF that digital circuits can then manage. ADC dynamic range is limited - In many communications systems, the signals amplitude can vary greatly. Fast ADCs often only have 12 bits of resolution giving an absolute maximum dynamic range of 72dB. It is often better to use analog circuits in conjunction with the ADC to implement AGC functions to ensure that this range is best used.
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Sampling of a signal at the Nyquist rate (sampling rate equal to twice the bandwidth of interest) has the advantage of a low sampling rate. Disadvantages include the need for high-accuracy analog anti aliasing circuits to filter the signal before sampling. The filter circuits serve to attenuate the high-frequency noise and out-of-band components that alias into the signal band (anti aliasing filter). These antialiasing filters are vulnerable to noise and interference that corrupt the signal of interest. Also, fine-line VLSI technology is better suited to fast digital architectures rather than precise analog architectures, making the filter fabrication process difficult.
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Digital Radio Frequency Memories (DRFMs) are devices which use high-speed sampling and fast digital memory for storing and replicating radiating signals. They provide the ability to capture radiated emissions and generate precise, coherent replicas, making them important in applications such as signal jamming, deception of covert communications, SIGINT operations, decoys, radar transmitters, simulations and test equipments.
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Analog Filters
Band Pass Filter
Low Pass Filter
AD C
High Speed Dual Ported Memory
DAC
Low Pass Filter
Band Pass Filter
LO
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A DRFM can be quite useful in any application where radiated signals of interest are being collected, routed, and/or generated. Some applications include 1. Radar signal reception, storage and analysis for ELINT applications (frequency measurements). 2. Deception of covert communications (e.g., spread spectrum frequency hoppers, PSK, FSK). 3. SIGINT operations 4. Decoy/SAR/ISAR target image synthesis 5. Radar transmitter
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An exciting application for digital receivers undersampling, sampling, sampling, or
new wideband is called
harmonic bandpass Super-
Nyquist Sampling.
The concept of discrete time and amplitude sampling of an analog signal is shown in the Figure.
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Shannon: An Analog Signal with a Bandwidth of fa Must be Sampled at a Rate of fs>2fa in Order to Avoid the Loss of Information. The signal bandwidth may extend from DC to fa (Baseband Sampling) or from f1 to f2, where fa = f2 - f1 (Undersampling, Bandpass Sampling, Harmonic Sampling, Super-Nyquist) Nyquist: Nyquist: If fs<2fa, then a Phenomena Called Aliasing Will Occur. Aliasing is used to advantage in undersampling applications.
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In a receiver which uses direct IF-todigital techniques (often called undersampling, harmonic, bandpass, or IF sampling), the IF signal is applied directly to a wide bandwidth ADC. The ADC sampling rate is chosen to be at least 2f. The process of sampling the IF frequency at the proper rate causes one of the aliased components of f to appear in the dc to fs/2 Nyquist bandwidth of the ADC output. DSP techniques can now be used to process the digital base band signal.
This approach eliminates the detector and its associated noise and distortion. There is also more flexibility in the DSP because the ADC sampling rate can be shifted to tune the exact position of the f signal within the baseband. The obvious problem with this approach is that the ADC must now be able to accurately digitize signals which are well outside the dc to fs/2 Nyquist bandwidth which most ADCs were designed to handle. Special techniques are available, however, which can extend the dynamic range of ADCs to include IF frequencies.
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In broadband receiver applications, one ADC digitizes multiple channels in the receive path. Individual channel selection and filtering is done in the digital domain. Narrowband channel characteristics such as bandwidth, passband ripple, and adjacent channel rejection can be controlled with changes to digital parameters (i.e. filter coefficients). Such flexibility is not possible when narrowband analog filters are in the receive path.
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ADCs are generally designed to process signals up to Nyquist (fs/2) with a reasonable amount of dynamic performance. However, even though the input bandwidth of a sampling ADC is usually much greater than its maximum sampling rate, the SFDR and effective bit (ENOB) performance usually decreases dramatically for full scale input signals much above fs/2. This implies that the selection criteria for ADCs used in undersampling applications is SFDR or ENOB at the IF frequency, rather than sampling rate.
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In the development of classical ADC quantization noise theory, the assumption is usually made that the quantization error signal is uncorrelated with the ADC input signal. If this is true, then the quantization noise appears as random noise spread uniformly over the Nyquist bandwidth, dc to fs/2, and it has an rms value equal to q/12. If, however, the input signal is locked to an non-prime integer sub multiple of fs, the quantization noise will no longer appear as uniformly distributed random noise, but instead will appear as harmonics of the fundamental input sinewave. This is especially true if the input is an exact even sub multiple of fs.
The bandpass sigma-delta architecture offers interesting possibilities in digital receiver area. Traditional sigma-delta ADCs contain integrators, which are lowpass filters. They have passbands which extend from DC, and the quantization noise is pushed up into the higher frequencies. At present, all commercially available sigma-delta ADCs are of this type (although some which are intended for use in audio or telecommunications contain bandpass filters to eliminate any DC response).
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In the future, it may be possible to have such bandpass sigmadelta ADCs with userprogrammable digital filter coefficients, so that the passband of a receiver could be modified during operation in response to the characteristics of the signal (and the interference!) being received. Such a function is very attractive, but difficult to implement, since it would involve loading, and storing, several hundreds or even thousands of 16-22 bit filter coefficients, and would considerably increase the size, and cost, of the converter. A feature which could be added comparatively easily to a sigmadelta ADC is a more complex digital filter with separate reference (I) and quadrature (Q) outputs. Such a feature would be most valuable in many types of radio receivers. Technology exists today which should allow the bandpass sigma-delta architecture to achieve 16-bit resolution, SFDR of 70 to 80dBc, and an effective throughput rate of 10 to 20MSPS (input sampling rate = 100MSPS, corresponding to an oversampling ratio of 5 to 10). This would allow 40MHz IF with a 2MHz bandwidth to be digitized directly.
Superconductor analog-to-digital converters (ADCs) and ultra fast digital circuitry enable processing of microwave signals entirely in the digital domain. A wide variety of continuous-time band pass delta-sigma modulators using Josephson junction comparators exist. Featuring sampling frequencies up to 30 GHz, single-chip digital receivers have been demonstrated by connecting a rapid single flux quantum (RSFQ) digital circuitry with these ADCs. These receiver chips, cooled to 4 K by cryogen free refrigerators, have been used with room-temperature digital processors to demonstrate reception of microwave signals for X Band satellite communications and Link-16 data links. To date, the highest frequency of direct digitization is 21 GHz for satellite communication.
The goal of modern radio frequency (RF) receiver systems is to operate simultaneously in multiple frequency bands and maximize spectrum utilization while supporting diverse modalities, e.g. voice, data, video, and particularly in case of military systems, detection and ranging, and electronic countermeasures. With the advent of software and cognitive radio concepts, there is a growing desire to bring the flexibility and fidelity of digital processing to the RF domain. This, however, requires direct digitization of the received RF signal. Radio frequency receivers at the higher end of the spectrum have always had one or more analog down converters; until recently, no analog-to-digital converter (ADC) was capable of directly converting microwave signals. A digital-RF receiver, featuring direct digitization followed by subsequent digital processing, circumvents all the limitations of an analog RF receiver front-end, enables scalability, agility, rapid reconfigurability, and supports advanced waveforms, such as those with fast frequency hopping.
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One of the primary advantages of digital processing lies in the ability to produce multiple copies without loss of power or fidelity. In a digital-RF receiver, multiple, independent chains of digital signal processing elements, performing a variety of functions such as down-conversion, filtering, and demodulation, follow a fast ADC. Multi-band digital-RF architecture uniquely incorporates RF switching and distribution in the digital domain, providing programmable connectivity between a set of ADCs and a set of digital processors. Although this digital-RF architecture and all its elements are technology-independent, superconductor integrated circuit (IC) technology with Niobium (Nb) Josephson junctions (JJs), currently offer the best solution.
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Superconductor ICs combine high-linearity, wideband ADCs and ultra fast digital logic, called Rapid Single Flux Quantum (RSFQ). A family of superconductor digital-RF receiver (called ADR) chips, comprising an ADC and a digital channelizer circuit, performing digital downconversion and filtering, have been demonstrated. A digital-RF receiver system, comprising a cryo cooled ADR chip, was demonstrated for the reception of live satellite communication signals in the 7.25-7.75 GHz range.
Superconductor ADCs combine comparators with ultra-fast switching speed and natural quantization of magnetic flux to enable fast and accurate data conversion. There are various types of superconductor ADCs, including low pass phase modulation-demodulation (PMD) and wideband flash ADCs, for different applications. Most suited for maximizing signal-to-noise ratio (SNR) in a microwave band is a band pass delta-sigma (BP) modulator. An ideal over sampled delta-sigma modulator of order n, using an m-bit quantizer sampled at fclk, produces a signal-to-noise dynamic range given by
3 2n + 1 2 SNR = 2 n (2m 1) R 2 n +1 2
R = f clk / 2f
Where
is the over sampling ratio.
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The modular design methodology ensures that within its input-output and heat load capacity, the system can be reconfigured to perform a different function by changing the chip module and by reprogramming FPGA-based digital signal processors. The latest (third) generation system (ADR-005), hosting a 55 mm2 7.5-GHz bandpass ADC chip and an FPGA channelizer, successfully repeated the over-the-air SATCOM demonstration performed previously using a 1cm2 single-chip bandpass digital receiver with an on-chip superconductor channelizer. This system ran error-free for over 12 hours with and without a low-noise amplifier.
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Implementation using digital building blocks more towards RF side. IF sampling is considered as a reasonably viable solution. Evolution of high speed ADCs enhance digitization of the input RF itself without down conversion. Oversampling techniques Undersampling Digital Receivers
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National Workshop on Recent Trends in RF and Microwave Techniques and Measurements

July 20, 2012

July 20, 2012