Contents of various files used in physical design flow with inputs/outputs:

1) Logical synthesis (fix time): a. Inputs: i. Verilog netlist (.v) ii. Libraries or library volcano 1. .lib It contains logical and timing related information for cells like setup/hold, PVT conditions, power templates, Wire load models, Cell area and input pin capacitance. 2. .tf/.lef It describes the units, drawing patterns, layers, design rules, vias, parasitic resistance and capacitance of the manufacturing process.We can provide this library at physical synthesis (floorplan) part of the flow also, it is not mandatory to provide during logical synthesis. iii. .sdc its a constraint file and it contains clock information, setup/hold margins, latency/uncertainty margins, false path, multicycle path, input/output delay. b. Outputs: i. Technology mapped synthesized gate level netlist (.v) ii. Design database (.volcano) iii. Timing reports iv. Constraints.tcl file 2) Floorplanning (fix plan): a. Inputs: i. Design database from fix time (.volcano) ii. Physical library (.lef) 1. Manufacturing grid 2. Routing grid 3. Routing layers information (min/max width, spacing) 4. Via definition 5. Antenna definition 6. Metal layer slotting rules iii. Floorplan data (.fp file) 1. Total Utilization 2. Aspect ratio or core width/height 3. Pin locations b. Outputs: i. Verilog netlist (.v) ii. Macro placement .tcl file iii. Design database (.volcano) iv. Area report , model report

3) Powerplanning (fix power): a. Inputs: i. Design database from floorplan stage (.volcano) ii. Power structures information (.def) 1. Core power ring 2. Power mesh 3. Power rail 4. Macro ring (Optional) iii. Total power consumption and power supply for chip b. Outputs: i. Verilog netlist (.v) ii. Design database with power structures (.volcano) iii. DRC report, area report 4) Placement (fix cell): a. Inputs: i. Design database from powerplan stage (.volcano) ii. Placement constraints for timing (Optional) b. Outputs: i. Verilog netlist with legalized cells (.v) ii. Design database (.volcano) iii. Timing reports , area report 5) Clock Tree Synthesis (fix clock): a. Inputs: i. Design database from placement stage (.volcano) ii. More clock constraints if any (optional) iii. Skew/Latency targets iv. Type of buffers/inverters used in CTS (Optional) b. Outputs: i. Design database (.volcano) ii. Clock timing reports (skew, latency, setup/hold etc) iii. Area/model reports 6) Routing (fix wire): a. Inputs: i. Design database from CTS stage (.volcano) ii. Shielding rules if any (Optional) b. Outputs: i. Design database (.volcano) ii. Timing reports , area reports, DRC reports iii. Layout (.gds) file