M Tech (Electronics) Specialization: VLSI and Embedded Systems (w.e.f.

2011-12) Structure Semester I

Sr. No. 1. 2. 3. 4. 5. Course Code OEC I Core I Core II Core III DEC-I Course Name L 3 3 3 3 3 Teaching Scheme T -----Credits P ------

Image Processing & Analysis PLDs and HDL CMOS VLSI Design Embedded Processors A. Advanced Computer Architecture B. Communication Networks Course Seminar LLC PG Laboratory I Total

3 3 3 3 3

6. 7. 8.

LC LLC LC

---15

-----

2 -6 8

1 1 3 20 Credits

Semester II
Sr. No. 9. 10. Course Code OEC II DEC-II Course Name Teaching Scheme L T P 3 --3 ---

11. 12. 13. 14. 15.

Core IV PSEC I PSEC II MLC LC

Artificial Intelligence A. High Performance Networks B. Source and Channel Coding Techniques Embedded Software and RTOS A. Memory Technologies B. Reconfigurable Computing A. Advanced Embedded Architecture B. System-on-Chip (SoC) Intellectual Property Rights PG Laboratory II Total

3 3

3 3 3 1 -16

-------

----8 8

3 3 3 1 4 20

OEC- Institute level Open Elective Course Core- Departments Core Course DEC- Department Elective Course PSEC- Program Specific Elective Course LLC- Liberal Learning (Self learning) Course MLC- Mandatory Learning Course LC- Laboratory Course

Semester-III
Sr. No. 1 2 3 Course Code MLC MLC Project Course Name Teaching Scheme L T P 2 --2 --Total ---Credits

Environmental Studies Constitution of India Project Stage I

2 2 16 20

Semester-IV
Sr. No. 1 Course Code Project Course Name Teaching Scheme L T P ------Credits

Project Stage II Total

20 20

OEC-I Image Processing and Analysis Teaching Sche me Lectures : 3 hrs/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50. Syllabus Contents: Image perception, monochrome and color vision models, Image sampling and quantization Two dimensional orthogonal transforms - DFT, FFT, WHT, Haar transform, KLT, DCT Image enhancement - Filters in spatial and frequency domains, histogram-based processing, homomorphic filtering Image restoration - PSF, de-convolution, restoration using inverse filtering, Wiener filtering, maximum entropy-based methods. Color Image processing color models, color transformation, smoothing, sharpening, color segmentation Morphological Image processing dilation and erosion, basic morphological algorithms Image Segmentation point, line and edge detection, edge linking and boundary detection, thresholding, region based Segmentation Image attribute representation and description - boundary descriptors, regional descriptors Object Recognition patterns and pattern classes, recognition based on decision theoretic and structural methods References : Gonzalez and Woods, Digital Image Processing, Pearson Education. Woods and Eddins, Digital Image Processing using Matlab, Gonzalez, Pearson Education. Milan Sonka, Vaclav Hlavac,Roger Bole, Image processing , Analysis and Machine Vision, ITP Chanda D. Majumdar, Digital Image Processing and Analysis, P HI. Pratt W.K, Digital Image Processing, John Wiley & Sons

Core-I PLDs and HDL Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Computing requirements, Area, Technology scaling, Instructions, Custom Computing Machine, Overview, Comparison of Computing Machines. Interconnects, Requirements, Delays in VLSI Structures; Partitioning and Placement, Routing; Computing Elements, LUTs, LUT Mapping, ALU and CLBs, Retiming, Fine- grained & Coarse-grained structures; Multicontext; Comparison of different architectures viz. PDSPs, RALU, VLIW, Vector Processors, Memories, Arrays for fast computations, CPLDs, FPGAs, Multicontext, Partial Reconfigurable Devices; TSFPGA, DPGA, Matrix; Best suitable approach for RD; Case study. Control Logic, Binding Time and Programming Styles, Overheads, Data Density, Data BW, Function density, Function diversity, Interconnect methods, Best suitable methods for RD; Contexts, Context switching; Area calculations for PE; Efficiency, ISP, Hot Reconfiguration; Case study. Architectures for existing multi FPGA systems, Modeling combinational and sequential circuits, Design entry by verilog/ VHDL /FSM / SYSTEM C, Hardware modeling with Verilog / VHDL, different verilog /VHDL constructs, and Logic Synthesis, Simulation ,Verification of complex logic design model

References : Andre Dehon, Reconfigurable Architectures for General Purpose Computing, PHI High Performance Computing Architectures (HPCA) Society papers. Christophe Bobda, Introduction to Reconfigurable Computing, Springer Publication. Maya Gokhale, Paul Ghaham, Reconfigurable Computing, Springer Publication

Core-II CMOS VLSI Design Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: MOS Switch, MOS Diode/ Active Resistor, Current Sinks & Sources, Current Mirror, Current & Voltage Reference, Band gap References. Inverters, Differential Amplifiers, Cascode Amplifiers, Current Amplifiers, Output Amplifiers, High Gain Amplifier Architectures. Buffered Opamp, High Speed/Frequency Opamps, Differential Output Opamps, Micro power Op amps, Low Noise Opamp. Low Voltage Opamp, Macro models for Opamps. Sequential Ckts. Design of FSM, Moore & Mealy machines, Metastability, Solutions to metastability, Synchronization methods, VHDL codes for complex sequential machines, Hazards, Types of hazards, Method to eliminate hazards, case studies. CMOS parasitic, Technology scaling, Lambda parameter, Design calculations for different logic ckts, Calculations for Area on chip, Power dissipation, PDP, Transmission gate, Domino logic, NORA logic, CMOS layout techniques, Transient response, Advance trends of elements & Alloys for ultra fast logic clock, VLSI: NMOS, CMOS and BiCMOS logic gates, realization of Boolean functions using CMOS gates, Gate delay and transient response, W/L and power considerations, subsystem design and layout, ultra fast VLSI circuits and systems with GaAs system. CMOS processing. Layout Fabrication. Threshold voltage adjustment. CMOS analog circuit introduction: Analog integrated circuit design, symbology and terminology, Analog signal processing, Analog VLSI mix signal design concept, MOS. diode and active resistors. Circuit synthesis and modelling.

References : Douglas Holberg, CMOS Analog circuit design, Oxford Publication. Rabey, Chandrakasan, Digital IC Design. Artech House Publications Ken Martin Digital Integrated Circuit Design Oxford Press 2000 Pucknell and Kamran Basic VLSI Design EEE PHI 3 rd Edition Allen and Holberg CMOS Analog Circuit Design. Oxford Pub. (2nd Edn.)

Core-III Embe dded Processors Teaching Sche me Lectures : 3 hrs/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Embedded Systems, Introduction, Design Metrics, Processor Technology, IC Technology, Design Technology, Design Productivity Gap, Custom Single purpose Processor Design, RT level design, FSMD, Datapaths, Optimization, Instruction set simulators for simple processors, State Machine and Concurrent process models, HCFSM, PSM, Architectural Features Of ARM: Processor modes, Register organization, Exceptions and its handling, Memory, Memory- mapped I/Os, ARM and THUMB instruction sets, Addressing modes, DSP extensions, ARM sample codes, ARM7/9 Core: H/W architecture, Timing diagrams for Memory access, Co-processor interface, Debug support, Scan chains, Embedded Real Time ICE, Hardware and software breakpoints, Buses: AMBA, ASB, APB, Case study of Intel XSCALE architecture or Samsung ARM implementations, Development tool like Compilers, Debuggers, IDE etc., DSP Architecture: MAC, Modified bus structures and Memory access schemes, Multiple access Memory , Multi-ported memory, VLIW architecture, Pipelining, Special addressing modes, On chip peripherals, TMS320C67XX 32 bit floating point DSP Processor: Introduction, features, Applications, Block diagram, Internal architecture, CPU & data paths, Functional units, Addressing modes, Memory architecture, External memory accesses, Pipeline operation, Peripherals, Assembly la nguage programming. Hardware tools: DSP (DSK s-DSP starter kit) and other DSP boards Software tools: Assembly language tools, DSP simulator, C compiler and C source debugger, Code composer studio, Simulators, Works with a DSK References : Sloss Andrew N, Symes Dominic, Wright Chris, ARM System Developer's Guide: Designing and Optimizing , Morgan Kaufman Publication. B. Venkataramani, M Bhaskar, Digital signal processors, TMH Steve furber, ARM System-on-Chip Architecture, Pearson Education Frank Vahid and Tony Givargis, Embedded System Design, Wiely Technical references on www.arm.com Raj Kamal, Embedded System Design, TMH Technical reference manuals from TI.

DEC-I Advanced Computer Architecture

Teaching Sche me Lectures : 3 hrs/week

Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Overview of Parallel Processing and Pipelining Processing Architectural Classification, Applications of parallel processing, Instruction level Parallelism and Thread Level Parallelism, Explicitly Parallel Instruction Computing (EPIC) Architecture, Case study of Intel Itanium Processor(IA64), Performance analysis. Pipeline Architecture Principles and implementation of Pipelining, Classification of pipelining processors, General pipelining reservation table, Design aspect of Arithmetic and Instruction pipelining, Pipelining hazards and resolving techniques, Data buffering techniques, Job sequencing and Collision, Advanced pipelining techniques, loop unrolling techniques, out of order execution, software scheduling, trace scheduling, Predicated execution, Speculative loading, Register Stack Engine, Software pipelining, VLIW (Very Long Instruction Word) processor, Case study: Superscalar Architecture- Pentium, Ultra SPARC Vector and Array Processor Basic vector architecture, Issues in Vector Processing, Vector performance modeling, vectorizers and optimizers, Case study: Cray Arch. SIMD Computer Organization Masking and Data network mechanism, Inter PE Communication, Interconnection networks of SIMD, Static Vs Dynamic network, cube hyper cube and Mesh Interconnection network. Parallel Algorithms for Array Processors: Matrix Multiplication. Sorting, FFT Multiprocessor Architecture Loosely and Tightly coupled multiprocessors, Processor characteristics of multiprocessors, Inter Processor communication network, Time shared bus, Crossbar switch, Multiport Memory Model, Memory contention and arbitration techniques, Cache coherency and bus snooping, Massively Parallel Processors (MPP), COWs and NOWs Cluster and Network of Work Stations), Chip Multiprocessing (CMP), Case Study of IBM Power4 Processor, Inter Processor Communication and Synchronization Multithreaded Architecture Multithreaded processors, Latency hiding techniques, Principles of multithreading, Issues and solutions, Parallel Programming Techniques: Message passing program development, Synchronous and asynchronous message passing, Message pass ing parallel programming, Shared Memory Programming, Data Parallel Programming

Parallel Software Issues Parallel algorithms for multiprocessors, classification of parallel algorithms, performance of parallel algorithms, Operating systems for multiprocessors systems, Message passing libraries for parallel programming interface, PVM (in distributed memory system), Message Passing Interfaces (MPI), PThreds (in shared memory system), Parallel Programming Languages : Fortan 90, Occam, C-Linda, CCC etc., Issues towards cluster computing. Introduction to Neuro Computing and Grid Computing References : Kai Hwang, Faye A. Briggs, Computer Architecture and Parallel Processing McGrawhill international Edition Kai Hwang, Advanced Computer Architecture, Tata McGrawhill Edition V.Rajaraman, L Sivaram Murthy, Parallel Computers, PHI. William Stallings, Computer Organization and Architecture, Designing for performance Prentice Hall, Sixth edition Kai Hwang, Scalable Parallel Computing Harrold Stone, High performance computer Architecture Richard Y. Kain , Advanced Computer Architecture

DEC-I Communication Networks

Teaching Sche me Lectures : 3 hrs/week

Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Network Design Issues: Scope, Manageability, node placement, Link topology, Routing Protocol selection. Network Performance Issues: Network Terminology, centralized and distributed approaches for networks. Networks performance analysis, Traffic classes, Traffic Control. Queuing Theory, Poissons Model. Protocol Study: Intra and Inter Autonomous system routing protocols, ATM, 802.11, Bluetooth, SNMP, IPV6, Socket Programming, standard application layer Protocols, performance Analysis of the protocols (Mathematical approach). Network Troubleshooting, Network Security: Cryptography, Authentication, Firewalls, and Security, on emails, Network management Security. Network Applications: Wireless Networking connecting components & transmission techniques, LAN, WAN, INTRANET, INTERNET, Case studies, and voice over IP, Video conferencing, Digital Library. Network systems design using Network Processors: Network processor technology and architecture. Study of network processors like Intels IXP 1200 network processors family.

References : Aaron Kershenbaum- Telecommunication Network Design Algorithms, McGraw Hill, international Editions 1993. Vijay Ahuja - Communications Network Design and Analysis of Computer Communication Networks, McGraw Hill, International Editions. Douglas E. Comer- Internetworking with TCP/IP. Douglas E. Comer- Network Systems Design using Network Processors, (Pearson Education.).

OEC-II Artificial Intelligence Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Introduction-Definition, What is A.I.? Foundation of A.I., A.I. App lications, A.I. Futures of A.I. Production System Heuristic search techniques- Heuristic search, Hill Climbing, Best first search, mean and end analysis, Constraint Satisfaction, A* and AO* Algorithm. Game Playing- Minmax search procedure, Alpha beta cutoffs Logic Programming Introduction to logic, Logic Programming, Forward and Backward reasoning, Forward and backward chaining rules Knowledge Representation Basic of Knowledge representation Paradigrams, Prepositional Logic, Inference Rules in Prepositional Logic, Knowledge representation using Predicate logic: Predicate Calculus, Predicate and arguments, Resolution, Natural Dedication Knowledge representation using non monotonic logic: TMS (Truth Maintenance system), Statistical and probabilistic reasoning ,fuzzy logic, structure knowledge representation , semantic net , Frames, Script Advance AI Topics: Natural Language Processing, Introduction, Steps in NLP Perception, Action, Robot Architecture Introduction to neural networks and perception. Neural net Architecture and applications Expert System- Utilization and functionality, architecture of expert system, knowledge representation, two case studies on expert systems. References : Eiaine Rich and Kerin Knight: Artificial Intelligence Eugene, Charniak, Drew Mcdermott: Introduction to artificial intelligence. Kishen Mehrotra , Sanjay Rawika , K Mohan : Artificial Neural Network. Herbert A Simon,The Sciences of the Artificial, MITPRESS, 3 rd Edition (2nd Printing), 1995. Ivan Bratko: Prolog Programming For Artificial Intelligence, 2 nd Edition Addison Wesley ,1990 Stuart Russell & peter Nerving: Artificial Intelligence : A Modern Approach, Prentice Hall ,2nd Edition

DEC-II High Performance Networks Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Types of Networks, Network design issues, Data in support of network design. Network design tools, protocols and architecture. VoIP system architecture, protocol hierarchy, Structure of a voice endpoint, Protocols for the transport of voice media over IP networks. Providing IP quality of service for voice, signaling protocols for VoIP, PSTN gateways, VoIP applications. Introduction, challenges, SCSI protocols and architecture: RAID, Backup and mirroring, Fiber channel attached storage. Network attached storage including NFS, CIFS and DAFS, Management of network storage architectures. New storage protocols, architectures and enabling technologies. Introduction to CDMA and spread spectrum system, CDMA standards, system architectures of wireless communication systems, physical, network and data link layer of CDMA, wireless LAN standards: IEEE 802.11b, ARPA. Overview of Information Theory. Lossless Compression: Run-Length Encoding, Facsimile compression, String- matching Algorithms. Lossy Compression: DCT, Wavelet compression. A model for internet security, security attacks, services, internet standards & RFCs, Cryptography, Conventional encryption, principles and algorithms, cipher-block, modes of operation, location of encryption devices , key distribution ,Public key cryptography principles and algorithms, RSA algorithm.

References : Kershenbaum A., Telecommunications Network Design Algorithms, Tata McGraw Hill. Ramaswami R., Shivrajan K, Optical Networks, Morgan Kaufmann. Douskalis B., IP Telephony: The Integration of Robust VoIP Services, Pearson Ed. Asia. Warland J., Varaiya P., High- Performance Communication Networks, Morgan Kaufmann, 1996. Stallings W., High-Speed Networks: TCP/IP and ATM Design Principles, Prentice Hall, 1998. Garg V., Smolk K., Vilkes J.,Applications of CDMA in wire less communication. William Stalling : Network security, essentials- Pearson education Asia publication.

DEC-II Source and Channel Coding Techniques Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Information and Source Coding for discrete sources: Mathematical models for Information, A Logarithmic Measure of Information: Average and Mutual Information, Entropy, Coding for Discrete Sources-Coding for Discrete Memoryless Sources, Discrete Stationary Sources, Shanon-Fano & Huffman algorithms, Arithmetic coding, transform based lossy coding, DCT, Quantization, JPEG standard and its modes, Color image coding, B/W and color Television standards, Video compression, motion estimation and compensation, block matching algorithms and criteria, MPEG standard-1, 2, 4, Audio coding, psychoacoustic models, ADPCM , MPEG-Audio, Dolby Audio, Channel coding, Channel models, Channel capacity, Linear block codes, Error correction and detection capability, Usefulness of the standard array, Cyclic codes, Block codes examples such as Hamming codes Convolutional codes, Convolutional encoding and decoding algorithms such as Viterbi, Sequential and feedback, RS codes and turbo codes References : Bhaskaran, Image and Video Compression standards and Algorithms, Kluwer Academic press Bernard Sklar, Digital Communication: Fundamentals and Applications, Pearson Education Asia. Simon Haykins, Digital Communication, edition II, Wiley. B.P.Lathi, Modern Digital and Analog Communication Systems, edition III, Oxford press Gulati, Television Engineering, PHI

Core-IV Embedded Software and RTOS Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: RTOS Concepts: Foreground and background systems, Critical section, Shared Resources, Tasks, Multitasking, Context Switching, Kernels, Pre-emptive and non pre-emptive Schedulers, Static and Dynamic Priorities, Priority Inversion, Mutual exclusion, Synchronization , Inter task communication mechanisms, Interrupts: Latency, Response and recovery, Clock Tick, Memory Requirements. Structure of COS-II - Kernel Structure: Tasks, Task States, TCB, Ready List, Task Scheduling, Task Level Context Switching, Locking and unlocking of scheduler, Idle Task, Statistics Task, Interrupts, Clock Tick, Initialization, Starting the OS, Task Managemen, Time Management, Event Control Blocks Synchronization in COS-II - Semaphore Management, Mutual Exclusion Semaphores, Event Flag Management Communication in COS-II - Message Mailbox Management, Message Queue Management Memory management, MCB, Porting of COS-II: Development Tools, Directories and Files, Configuration and testing of Port. Real Time Application using COS-II References : Jean Labrosse, MicroC/OS-II The Real Time Kernel, CMP Books , 2nd Edition David E. Simon, An Embedded Software Primer, Pearson Education Raj Kamal, Embedded Systems Architecture: Programming and Design, TMH

PSEC-I Memory Technologies Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Static Random Access Memories (SRAMs), SRAM Cell Structures, MOS SRAM Architecture, MOS SRAM Cell and Peripheral Circuit, Bipolar SRAM, SOl, Advanced SRAM Architectures, Application Specific SRAMs; DRAMs, MOS DRAM Cell, BiCMOS DRAM, Error Failures in DRAM, Advanced DRAM Design and Architecture, Application Specific DRAM, High Density ROMs, PROMs, Bipolar & CMOS PROM, EEPROMs, Floating Gate EPROM Cell, OTP EPROM, EEPROMs, Nonvolatile SRAM, Flash Memories. RAM Fault Modeling, Electrical Testing, Pseudo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing. General Reliability Issues, RAM Failure Modes and Mechanism, Nonvolatile Memory, Reliability Modeling and Failure Rate Pred iction, Reliability Screening and Qualification. Radiation Effects, SEP, Radiation Hardening Techniques. Process and Design Issues, Radiation Hardened Memory Characteristics, Radiation Hardness Assurance and Testing, Ferroelectric Random Access Memories (FRAMs), Gallium Arsenide (GaAs) FRAMs, Analog Memories, Magneto Resistive Random Access Memories (MRAMs), Experimental Memory Devices. Memory Hybrids (2D & 3D), Memory Stacks, Memory Testing and Reliability Issues, Memory Cards, High Density Memory Packaging, Future Directions, Introduction to digital tablet PC, LCD, DVD player etc. References : Ashok K.Sharma, " Semiconductor Memories Technology, Testing and Reliability ",Prentice- Hall of India Private Limited, 1997. Wen C. Lin, Handbook of Digital System Design, CRC Press.

PSEC-I Reconfigurable Computing Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: Computing requirements, Area, Technology scaling, Instructions, Custom Computing Machine, Overview, Comparison of Computing Machines. Interconnects, Requirements, Delays in VLSI Structures; Partitioning and Placement, Routing; Computing Elements, LUTs, LUT Mapping, ALU and CLBs, Retiming , Fine- grained & Coarse-grained structures; Multicontext; Comparison of different architectures viz. PDSPs, RALU, VLIW, Vector Processors, Memories, Arrays for fast computations, CPLDs, FPGAs, Multicontext, Partial Reconfigurable Devices; TSFPGA, DPGA, Mattrix; Best suitable approach for RD; Case study. Control Logic, Binding Time and Programming Styles, Overheads, Data Density, Data BW, Function density, Function diversity, Interconnect methods, Best suitable methods for RD; Contexts, Context switching; Area calculations for PE; Efficiency, ISP, Hot Reconfiguration; Case study. Architectures for existing multi FPGA systems, Compilation Techniques for mapping applications described in a HDL to reconfigurable hardware, Study of existing reconfigurable computing systems to identify existing system limitations and to highlight opportunities for research; Software challenges in System on chip; Testability challenges; Case studies. Modelling , Temporal portioning algorithms, Online temporal placement, Device space management, Direct communication, Third party communication, Bus based communication, Ckt switching, Network on chip, Dynamic network on chip, Partial reconfigurable design.

References : Andre Dehon, Reconfigurable Architectures for General Purpose Computing Christophe Bobda, Introduction to Reconfigurable Computing, Springer Publication. Maya Gokhale, Paul Ghaham, Reconfigurable Computing, Springer Publication. IEEE Journal papers on Reconfigurable Architectures. High Performance Computing Architectures (HPCA) Society papers.

PSEC-II Advanced Embedded Architecture Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: IA32 and IA64 Overview: Atom processor: Addressing modes: real, big-real, protected, paging, SMM, 64-bit extensions; Registers, Memory accesses and the memory map, Instruction set, Segmentation, Task switching, Paging, Hyperthreading, Caches and TLB, Execution pipeline, x86 legacy features, Interrupts, PIC and APIC, Software optimization, VT overview Front Side Bus (FSB) architecture : Transactions and packets on the bus, Signal groups, Phases on the bus, Locking transactions, Cache snooping, I/O transactions, Address alignment, Power management features Platform overvie w: Chipset overview, PCI configuration setup, logical PCI bus 0, DDR2, SPD and BIOS, Boot- up sequence, BIOS responsibilities, BIOS configuration, ACPI overview Powe r management: Frequency changes, Sleep states, traditional c states plus c4, c4e, c6, Thermal monitoring, L2 cache power down, Platform power consumption Embedded Software Development Suite: Case Studies:

References : Lori M. Matassa and Max Domeika, Break away with Intel Atom Processors A Guide to Architecture Migration, Intel Press Tom Shanley, X86 Instruction set Architecture, Mindshare Press Intel 64 and IA- 32 Architectures Software Developers Manual, Volume 1: Basic Architecture.

PSEC-II Systems on Chip

Teaching Sche me Lectures : 3 hrs/week Tutorials : 1 hr/week

Examination Scheme Mid-Sem 30, Assignments, Quiz -20 End-Sem Exam- 50.

Syllabus Contents: IC Technology, Economics, CMOS Technology overview, Power consumption, Hierarchical design, Design Abstraction, EDA tools. MOSFET model, parasitics, latch up, advanced transistor structures; Wire parasitics; Design rules, Scalable design rules, process parameters; stick diagrams, Layout design tools; Layout synthesis, layout analysis. CMOS gate delays, transmission time, speed power product, low power gates; Delay by RC trees, cross talk, RLC delay, cell based layout, Logic & interconnect design, delay modeling, wire sizing; Power optimization, Switch logic networks. Pipelining, Data paths, Adders, ALUs, Multipliers, High density memories; Metastability, Multiphase clocking; Power optimization, Design validation, Sequential testing; Architecture for low power. Floor planning methods, global routing, switch box routing, clock distribution; off chip connections, packages, I/O architectures, pad design. Complete chip design including architecture, logic and layout for Kitchen timer chip OR Microwave oven chip References: Wayne Wolf, Modern VLSI Design, Pearson Education. Kamaran Eshraghian, Principles of CMOS VLSI Design, Pearson Education Rabey, Chandrakasan, Digital IC Design, Preason Publication