ARM Processor

Instruction SET
and
Programming
Dr. C.H. Vithalani
E.C. Department,
Government Engineering College,
Rajkot
Programming
ARM Instruction Set
ARM instruction set
Data processing
instructions
Data transfer
instructions
Block transfer
instructions
Software interrupt
instructions
Block transfer
instructions
Multiply instructions
Branching instructions
ARM Instruction Set
ARM architecture is such that 32-bit ARM
instruction set & 16 bit Thumb instruction both
can be used.
Various addressing modes are as follow:
1. Register addressing 1. Register addressing
2. I mmediate addressing
3. I ndirect base and indexed addressing
Register Addressing Modes
All the operands are within the register itself.
Example:
MOV R1,R2 R2R1
MVN R1,R2 R2R1 (Complement of R2)
(Logic operation NOT and MOV combined in MVN) (Logic operation NOT and MOV combined in MVN)
ADD R1,R2,R3 R1=R2+R3
SUB R5,R4,R7 R5=R4-R7
SUB R4,R5,R7,LSR R2
(Logical right shift R7 by the number in the bottom
byte of R2, subtract result from R5, and put the
answer into R4)
Immediate Addressing Mode
Second source operand is immediate operand
MOV R0,# 0 R0=0
ADD r6,r7,# 6 R6=R7+6
CMP R7,# 1000 Compare content of R7 with 1000
MOV R1,# 0x17 Hexadecimal value 17h in R1 MOV R1,# 0x17 Hexadecimal value 17h in R1
MOV R2,# 17 Decimal value 17 in R2
MOV R1,R1,LSL # 2
R1 shifted left by 2 bit position and saved back in
R1 (R1=R1* 4)
Indirect Base and Indexed addressing
Major mode for load/ store architecture as direct
absolute addressing not available
LDR R1,[ R2] ; Load R1 from memory address
pointed by R2 R1* R2 pointed by R2 R1* R2
LDR R1,[ R2,-R3] ; Load R1 from memory address
pointed by (R2-R3)
R1* (R2-R3)
LDR R1,[ R2,# 8] ; R1* (R2+8)
Indirect Base and Indexed addressing
STR [ R5,# &0C] ,R4
Store Register R4 to the memory address pointed
by R5+12
I ndirect addressing mode by index plus offset with
post auto indexing post auto indexing
For example: LDR R1,[ R2] ,# 8
I n this instruction R1 is loaded from memory
location pointed by R2 and after loading offset of
8 is added into R2. This is called auto post
indexing
Indirect addressing by index plus
offset with pre auto indexing
LDR R4,[ R3,# 8] !
Load R4 from memory address pointed by R3
after adding offset 8 into R3. after adding offset 8 into R3.
I f R3=0000 0000 0000 0010 then R4 will be
loaded from the location (R3+8) = 0000 0000
0000 1010 in case of pre-auto indexing. I n case of
post indexing R4 will be loaded from 0000 0000
0000 0010 and then R3 becomes 0000 0000 0000
1010
Arithmetic Instructions
Operations such as addition, subtraction and
multiplication are available in direct and modified
form.
ADD Rd,Rn,<Oprnd> Exa: ADD R1,R2,# 55
Above instruction adds Rn to <Oprnd> and store
result in Rd. (R1=R2+55) result in Rd. (R1=R2+55)
ADDS Rd,Rn,<Oprnd> Exa: ADDS R1,R2,# 55
Same as ADD but ADDS has additional effect of
testing the result stored in Rd and setting four
condition codes in CPSR.
Arithmetic Instructions
ADC Rd,Rn,<oprnd> Exa: ADC R4,R5,R6
ADC includes carry during addition process. I n
above example R4=R5+R6+Carry. C
SUB Rd,Rn,<oprnd> Exa: SUB R2,R2,R5
R2=R2-R5 R2=R2-R5
SUBS Rd,Rn,<oprnd> Exa: SUBS R2,R2,R5
R2=R2-R5 CPSR is affected by result in R2
RSB (Reverse subtraction)
RSB Rd,Rn,<oprnd> Exa: RSB R2,R2,R5
R2=R5-R2
RSBS (Reverse subtraction with CPSR affected)
Arithmetic Instructions
SBC (Consider carry during subtraction)
SBC Rd,Rn,<oprnd> Exa: SBC R1,R2,R3
R1=R2-R3-NOT(carry)
SBCS (Same as SBC but CPSR is affected by result
in destination) in destination)
RSC Rd,Rn,<oprnd> Exa: RSC R1,R2,R3
R1=R3-R2-NOT(carry)
RSCS (Same as RSC but CPSR is affected by
result)
Instructions
MUL R1,R2,R3; R1:=R2*R3
MOV R2,R0, LSL #3 ; Shift R0 left by 3 R2
(R2=R0*8)
ADD R9,R5,R5,LSL #2 ; R9=R5*4+R5
(R9=5*R5)
SUB R10,R9,R8,LSR#4 ; R10=R9-R8/16 SUB R10,R9,R8,LSR#4 ; R10=R9-R8/16
MLA R1,R2,R3,R4 ; R1=(R2*R3)+R4
(Multiply and accumulate useful for convolution in
signal processing applications)
MOV R12,R4,ROR R3 ; R12=R4 rotated right by
value of R3
Load and store instructions
Transfers data between memory and processor
registers
Single Register transfer: Data type supported are
32 bit signed or unsigned, 16 bit and 8 bit
(Word, Half-word or Byte) (Word, Half-word or Byte)
Multiple Register transfer: Transfer multiple
registers between memory and processor in single
instruction
Swap: swap content of memory with content of
processor registers.
Load and store Instructions
Load/store instructions are basically data transfer
instructions from processor memory to registers and vice-
varsa
Can be used to load PC
(if target address is beyond branch instruction range) (if target address is beyond branch instruction range)
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRSH Load Signed Half Word STRSH Store Signed Half Word
LDRB Load Byte STRB Store Byte
LDRSB Load Signed Byte STRSB Store Signed Byte
Instructions
LDRH R1,[ R2,-R3] !
Load R1 from the contents of the half word
address contained in R2-R3 (both of which are
registers) and write back address to R2
STRH R3,[ R4,# 14]
Store the halfword in R3 at R14+14 but Store the halfword in R3 at R14+14 but
don't write back.
LDRSB R8,[ R2] ,# -223
Load R8 with the sign extended contents of the
byte address contained in R2 and write back
R2-223 to R2.
Data Transfer Instructions
Offset
Addressing
LDR: Load in register a word (32 bit)
LDR R0,[R1,#4] R0[R1+4]
LDR R0,[R1,R2] R0[R1+R2]
LDR R0,[R1,R2,LSL #2] R0[R1+R2*4]
Data Transfer Instructions
LDR R0,[R1,#4]! R0[R1+4] & R1=R1+4
Pre-Index
Addressing
LDR R0,[R1,#4]! R0[R1+4] & R1=R1+4
LDR R0,[R1,R2]! R0[R1+R2] & R1=R1+R2
LDR R0,[R1,R2,LSL #2]! R0[R1+R2*4] &
R1=R1+R2*4
Data Transfer Instructions
LDR R0,[R1],#4 R0[R1] & R1=R1+4
Post-Index
Addressing
LDR R0,[R1],#4 R0[R1] & R1=R1+4
LDR R0,[R1],R2 R0[R1] & R1=R1+R2
LDR R0,[R1],R2,LSL #2 R0[R1] & R1=R1+R2*4
LDRB: Load a byte
LDRH: Load half word (16 Bit)
Data Transfer Instructions
STR: Store a word in register
STRB: Store a Byte in register
STRH: Store a Half word (16 bit) in register
Examples: STR R0,#10101010 Examples: STR R0,#10101010
STR R0,[R1] R0[R1]
Store word from register R0 to location
specified by R1.
STRH R3,[ R1,# 10] R3[ R1+10]
Store the halfword in R3 at [ R1+10]
Data Transfer Instructions
STR R1,[R2,R3] R1[R2+R3]
Store content of R1 at memory location pointed by
R2+R3
STR R1,[R2,R3]! R1[R2+R3] and R2=R2+R3
Store content of R1 at memory location pointed by Store content of R1 at memory location pointed by
R2+R3 and R2 becomes R2=R2+R3.
STR R1,[R2],R3 R1[R2] and R2=R2+R3
Store content of R1 at memory location pointed by
R2 and R2 becomes R2=R2+R3.
Block Transfer Instructions
Load/Store Multiple
instructions (LDM/STM)
Whole register bank or a
subset copied to memory or
R0
R1
R2
M
i
M
i+1
M
i+2
M
i+14
LDM
restored with single instruction
It may increase interrupt
latency because this
instruction usually not
interrupted
R14
R15
M
i+14
M
i+15
STM
Example: block transfer
LDMIA R0!, {R1-R3}
The register R0 specifies base address of the
memory from where registers R1,R2 and R3 will be
loaded.
IA: Increment after R0 will be incremented
automatically after each transfer: R0=R0+4N
Similarly IB: Increment before, DA: Decrement after
DB: Decrement Before options are also possible.
Swap Instruction
Exchanges a word between
registers
Two cycles but
single atomic action
R0
R1
R2
R7
single atomic action
Support for RT semaphores
R7
R8
R15
Logical Instructions
Bitwise logical operations (like ANR, OR, Ex-OR, Bit
clear) on two source registers is performed and result is
stored in destination register.
Example: BIC R0,R1,R2
R2 contains binary pattern where every binary 1 in R2
clears a corresponding bit location in the register R1. clears a corresponding bit location in the register R1.
Useful in manipulating status flag and interrupt mask.
For example
R1: 1011 0111 0111 1111 1011 0000 1111 1010
R2: 0111 1111 0000 0000 1010 0000 0000 1111
R0: 1000 0000 0111 1111 0001 0000 1111 0000
Compare Instructions
COMP R0,R5
Flags set as a result of R0-R5
Consider the instructions:
CMP R1,#0 ; Compare R1 with 0.
BNE LOOP ; Branch if not equal
The first instruction compares R1 with 0. The second The first instruction compares R1 with 0. The second
instruction is branch instruction, program will jump to
location specified by label LOOP if R1 is not equal to 0.
TEQ R1,R2
Flags set as a result of R1 Ex-OR R2
TST R2,R3
Flags set as a result of R2 & R3
Modifying the Status Registers
Only indirectly
MSR moves contents
from CPSR/SPSR
to selected GPR
R0
R1
R7
MRS
to selected GPR
MRS moves contents
from selected GPR
to CPSR/SPSR
Only in privileged
modes
R7
R8
R14
R15
CPSR
SPSR
MSR
Shift operations by barrel shifter
Destination CF 0
LSL : Logical Left Shift
Multiplication by a power of 2
MSB moves to carry flag and 0
inserted at LSB
EXAMPLES
MOV R0,R1,LSL #2
MOV R0,R1,LSL R2
LSB moves to carry flag and 0
Destination CF ...0
LSR : Logical Shift Right
Division by a power of 2
LSB moves to carry flag and 0
inserted at MSB
EXAMPLES
MOV R0,R1,LSR #2
MOV R0,R1,LSR R2
The Barrel Shifter
Destination CF
ASR: Arithmetic Right Shift
Division by a power of 2,
preserving the sign bit
ROR: Rotate Right
Maintains MSB so that useful to
maintain sign of value
EXAMPLES
MOV R0,R1,ASR #2
MOV R0,R1,ASR R2
LSB moves to carry as well as to
Destination CF
Bit rotate with wrap around
from LSB to MSB
Destination
RRX: Rotate Right Extended
Single bit rotate with wrap around
from CF to MSB
CF
LSB moves to carry as well as to
MSB
EXAMPLES
MOV R0,R1,ROR #2
MOV R0,R1,ROR R2
Supports 1 bit shift LSB to carry
and carry to MSB
EXAMPLE
MOV R0,R1,RRX
Register, optionally with shift operation
Shift value can be either be:
5 bit unsigned integer
Specified in bottom byte of
another register.
Used for multiplication by constant
Operand
1
Barrel
Shifter
Operand
2
Barrel Shifter: Second Operand
Immediate value
8 bit number, with a range of 0-255.
Rotated right through even
number of positions
Allows increased range of 32-bit
constants to be loaded directly into
registers
Result
ALU
Multiply Instructions
I nteger multiplication (32-bit result)
Long integer multiplication (64-bit result)
Built in Multiply Accumulate Unit (MAC)
Multiply and accumulate instructions add
product to running total
Multiply Instructions
I nstructions:
MUL Multiply 32- bit result
MULA Multiply accumulate 32- bit result
UMULL Unsigned multiply 64- bit result
UMLAL Unsigned multiply accumulate 64- bit result
SMULL Signed multiply 64- bit result
SMLAL Signed multiply accumulate 64- bit result
Compare and Test Instructions
Comparison instructions are used to compare and test the
content of register with a given 32 bit value.
The CPSR is always affected but no register is changed
The first operand is register Rd and second operand can be
immediate constant or register with additional shifts or
rotations rotations
TST and TEQ performs Boolean evaluation with AND and
Ex-ORoperations
CMP Rd,<Oprnd2> Update CPSR after Rd - <Oprnd2>
TST Rd,<Oprnd2> Update CPSR after Rd AND <Oprnd2>
TEQ Rd,<Oprnd2> Update CPSR after Rd EOR <Oprnd2>
Branching Instructions
Branching instructions are used to transfer control
conditionally anywhere in the memory which changes
sequential flow of instructions. Broadly there are two
types of branching instructions:
Branch (B): Jumps forwards/backwards up to 32 MB
The notation is B{cond}, Where cond is conditional
codes used for conditional branch. codes used for conditional branch.
For example: BNE LOOP : If this instruction is given after
CMP R1,#0, then program will jump to location specified
by LOOP label if R1 is not equal to zero.
Branch link (BL): Same as B + saves next instruction
i.e. (PC+4) in Link Register (R14)
BL is suitable for function call/return. When subroutine
finished it can return to main program by copying content
from Link register R14.
Conditional Execution
Condition codes specifies which bits in the CPSR need to
be tested.
Conditional codes used with branch instruction B is given
in following table:
EQ equal MI negative HI
unsigned
higher
GT
signed greater
than
positive or unsigned signed less
NE not equal PL
positive or
zero
LS
unsigned
lower or same
LE
signed less
than or equal
CS
unsigned
higher or
same
VS overflow GE
signed greater
than or equal
AL always
CC
unsigned
lower
VC no overflow LT
signed less
than
NV
special
purpose
Possible branching instructions using conditional
codes are BEQ, BMI , BNE, BAL etc.
Example: Conditional Execution
MOVCS R0,R1
This instruction will move value of register
R1 to register R0 only if carry flag is set.
MOVEQ R0,R1
This instruction will move value of register
R1 to register R0 only if zero flag is set.
BCC label
This instruction takes branch to label if
carry flag is cleared
Example: Conditional Execution
ADDEQ R0,R1,R2
Instruction executed only if zero flag is set
R0=R1+R2 only if zero flag is set.
Advantage of conditional execution Advantage of conditional execution
instruction:
Conditional instructions reduces number
of branches and number of pipeline
flushes
Increases code density
Branching Instructions
Two types of branch instructions: B & BL
B: Ordinary branch instruction
BL: Branch and link instruction
BL Perform branch operation and save
address following the branch (return
address) in the link register R14.
BL <Name of subroutine>
Branching Instructions
Branch and Exchange (BX)
This instruction is only executed if the
condition is true.
This instruction performs a branch by
copying the contents of a general register,
Rn, into the program counter (PC)
Branching Instructions
Branch exchange (BX) and
Branch link exchange (BLX):
same as B/BL +
exchange instruction set (ARM THUMB) exchange instruction set (ARM THUMB)
To return from subroutine to the main
program there is no RET instruction but
MOV PC,R14 can be used to return
Example: Conditional Execution
Consider that value loaded in R1=55 and R2=66
CMP R1,R2
BEQ <label> : Branch not taken because (R1-R2) = 0
BNE <label> : Branch taken because R1 = R2
BGE <lable> : Branch not taken because R1<R2
BLT <label> : Branch taken because R1<R2
BMI <label> : Branch taken because result minus (R1-R2)
Example: conditional execution
Consider following instructions:
MOVS R0,R1
MOVEQS R0,R2
MOVEQ R0,R3
Explanation:
The first instruction moves content of register R1 into R0
and change N and Z flag depending on value stored in
R0.
and change N and Z flag depending on value stored in
R0.
Second instruction will transfer R2 to R0 only if zero flag
is set. That means if during first instruction R1=0, second
instruction will execute. If second instruction is executed it
will change N and Z flag depending on value stored in R2.
Third instruction transfer register R3 to R0 only if zero flag
is set. That means R2=0 during second instruction. Thus,
third instruction will be executed only of R1 and R2 both
were 0.
Program: To add elements of array
_start:
MOV R1,#3 ;total 3 elements in array
LDR R2,=vect ;Assign address of vector
MOV R0,#0 ; Reset R0 to store result
Loop: LDR R3,[R2] ; R3=vect[i]
ADD R0,R0,R3 ; R0=R0+vect[i] ADD R0,R0,R3 ; R0=R0+vect[i]
ADD R2,R2,#4 ; R2 moves to next element
SUB R1,R1,#1 ; Decrement counter
CMP R1,#0 ; See whether R1=0 or not
BNE Loop
.data
vect: .word 1,5,10,15
.end
Software Interrupt
SWI instruction
Forces CPU into supervisor mode
Usage: SWI # n
Maximum 2 Maximum 2
24 24
calls calls
Suitable for running privileged code and Suitable for running privileged code and
making OS calls making OS calls
Cond Opcode Ordinal
31 28 27 24 23 0
Thumb Instruction Set
Compressed form of ARM
I nstructions stored as 16-bit,
Decompressed into ARM instructions and
Executed
Lower performance (ARM 40% faster)
Higher density (THUMB saves 30% space)
Optimal
interworking (combining two sets)
compiler supported
THUMB Instruction Set
More traditional:
No condition codes
Two-address data processing instructions
Access to R0 R8 restricted to
MOV, ADD, CMP
PUSH/POP for stack manipulation
Descending stack (SP hardwired to R13)
THUMB Instruction Set
No MSR and MRS,
must change to ARM to modify CPSR
(change using BX or BLX)
ARM entered automatically after RESET ARM entered automatically after RESET
or entering exception mode
Maximum 255 SWI calls
Exercise
Visit website: www.arm.com for latest
updates
Find out what is CAN and utilization of
CAN. CAN.
List ARM based microcontrollers
What are the features of ARM based
Phillips microcontroller LPC-2129 and LPC-
2294?
Thank you .