You are on page 1of 33

2/6/2012

I HC QUC GIA TP.H CH MINH TRNG I HC BCH KHOA


KHOA IN-IN T
B MN K THUT IN T

Embedded System Design


Chapter 2: Microcontroller
1. PIC16 Series 1.1 Introduction to PICs 1.2 PIC16F84 1.3 PIC16F87x 2. ARM Cortex-M Series 2.1 Introduction to ARM Cortex 2.2 ARM Cortex-M3
1

1.1 Introduction to PIC microcontroller


PIC is a family of modified Harvard architecture microcontrollers made by Microchip Technology The PIC1650 was originally developed by General Instruments The name PIC initially referred to "Peripheral Interface Controller"

B mn K Thut in T - HBK

2/6/2012

Why is PIC popular?


PICs are popular with developers due to
low cost wide availability large user base extensive collection of application notes availability of low cost or free development tools serial programming capability
PIC18F4XK20 Starter Kit 128x64 Organic LED Display (SPI) 32.768 kHz External Oscillator (Timer1) Analog input filtering and gain control into RE1 PWM output filtering from RC2 4 push buttons for user interfacing

B mn K Thut in T - HBK

PIC microcontroller
Comparison of PIC families

Complete portfolio: 6 to 100 pins, 384B to 512KB of program memory, up to 80MHz Upward compatible architectures to preserve investment in code development Pin compatibility in multiple packages facilitates drop-in replacement Range of memory technologies: Self Programming Flash, OTP, ROM Easy Migration across 8, 16, and 32-bit families

B mn K Thut in T - HBK

2/6/2012

PIC Microcontroller

B mn K Thut in T - HBK

Some members of PIC16 Series

B mn K Thut in T - HBK

2/6/2012

Some members of PIC16 Series

B mn K Thut in T - HBK

PIC speed
Can use crystal, clock oscillator, or even an RC circuit Some PICs have a built-in 4MHz RC clock, not very accurate, but requires no external components Instruction speed = clock speed
12C50x 12C67x 16Cxxx 17C4x/17C7xxx 18Cxxx 4MHz 10MHz 20MHz 33MHz 40MHz

B mn K Thut in T - HBK

2/6/2012

PIC Clock

Three ways to provide the clock signal to a PIC

B mn K Thut in T - HBK

PICs program memory


PICs have two difference types of program storage:
EPROM (Erasable Programmable ROM)
need high voltage from programmer to program (~13V) need windowed chips and UV light to erase PIC examples: any C part 12C50x, 17C7xx,

FLASH
rewriteable much faster to develop on PIC examples: any F part 16F84, 16F87x, 18Fxxx
B mn K Thut in T - HBK
10

2/6/2012

PIC16 Series

http://tme.com.vn
B mn K Thut in T - HBK
11

1.2 The Microchip PIC16F84


The Microchip PIC16F84 is a low-cost, single-chip, 8-bit microcontroller.
Only 35 single word instructions All instructions single-cycle except for program branches which are two-cycle Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle 1024 words of program memory 68 bytes of Data RAM 64 bytes of Data EEPROM 14-bit wide instruction words 8-bit wide data bytes

B mn K Thut in T - HBK

12

2/6/2012

The PIC 16F84A pin connection diagram

B mn K Thut in T - HBK

13

PIC16C8X PINOUT DESCRIPTION

B mn K Thut in T - HBK

14

2/6/2012

PIC16C8X PINOUT DESCRIPTION ..

B mn K Thut in T - HBK

15

Architecture of the PIC16F84


Buses: Communication lines for transferring data within the processor. Oscillator: Used to drive the microprocessor, clocking data and instructions in the processor. Timing: The PIC has an internal divide by 4 whereby 4 oscillator pulses form one clock pulse. This makes instruction times easy to calculate.
Most instructions (except calls and returns and other instructions involving jumps and branches) take one clock cycle, so with a 4MHz oscillator (divided by 4), instructions take 1s.
B mn K Thut in T - HBK
16

2/6/2012

Architecture of the PIC16F84

B mn K Thut in T - HBK

17

W Register

B mn K Thut in T - HBK

18

2/6/2012

The 16F84A Status register

B mn K Thut in T - HBK

19

The PIC16F84 Status register

B mn K Thut in T - HBK

20

10

2/6/2012

16F84A memory features

B mn K Thut in T - HBK

21

PIC16F84 Memory
There are two memory blocks in the PIC16C84; program memory and data memory. Each block has its own bus, so that access to each can occur during the same clock cycle. The data memory can be further broken down into general purpose memory and special purpose registers

B mn K Thut in T - HBK

22

11

2/6/2012

PIC16F84 Program Memory


Pointed to by reset vector

Pointed to by interrupt vector

0x00 0x01 0x02 0x03 0x04

0x3FF

B mn K Thut in T - HBK

23

PIC16F84 Data Memory


0x00 0x01 0x02 0x03 0x04 Ind. address. TMR0 PCL STATUS FSR PORTA data PORTB data

Special-purpose registers
Indirect pointer PORT A PORT B Not used

(This is a simplified memory map that excludes bank1. Study the memory banks in the Microchip data sheets).

0x05 0x06 0x07

0x08 EEPROM prog. 0x09 0x0A 0x0B 0x0C PCLATH INTCON .. .. .. .. .. Program counter Interrupt control
\: \ | | / / General-purpose file registers.

B mn K Thut in T - HBK

24

12

2/6/2012

PIC16F84 Register-Mapped I/O


PORTA and PORTB can be programmed as an input or an output. PORTA is 5 bits wide and PORTB is 8 bits wide. (Bit 4 of port A can be used for an
external timer input.) PORTA has pins/bits labelled RA4:RA0 PORTB has pins/bits labelled RB7:RB0
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 EEPROM prog. 0x09 0x0A 0x0B 0x0C PCLATH INTCON .. .. .. .. .. Program counter Interrupt control
\: \ | | / / General-purpose file registers.

Ind. address. TMR0 PCL STATUS FSR PORTA data PORTB data

Special-purpose registers
Indirect pointer PORT A PORT B Not used

Referencing bits . Bits are numbered 7-0 from left to right, i.e., msb-lsb. One of the most common programming errors is incorrect specification of bit numbers.

B mn K Thut in T - HBK

25

PIC16F84A CONFIGURATION WORD


bit 13-4 CP: Code Protection bit

1 = Code protection disabled 0 = All program memory is code protected

bit 3

PWRTE: Power-up Timer Enable bit

1 = Power-up Timer is disabled 0 = Power-up Timer is enabled

bit 2

WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0

FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator (Resistor/capacitor) 10 = HS oscillator (High Speed Crystal/Resonator) 01 = XT oscillator (Crystal/Resonator) 00 = LP oscillator (Low Power Crystal)
26

B mn K Thut in T - HBK

13

2/6/2012

OPTION REGISTER (ADDRESS 81h)


bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit


1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit


1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 2-0 PS2:PS0: Prescaler Rate Select bits

bit 4 T0SE: TMR0 Source Edge Select bit


1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit


1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

B mn K Thut in T - HBK

27

DIRECT/INDIRECT ADDRESSING

B mn K Thut in T - HBK

28

14

2/6/2012

DIRECT/INDIRECT ADDRESSING
A simple program to clear RAM locations 20h-2Fh using indirect addressing
movlw movwf NEXT clrf incf btfss goto CONTINUE : 0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue

An effective 9-bit address is obtained by concatenating the 8bit FSR register and the IRP bit (STATUS<7>) However, IRP is not used in the PIC16F84A.
B mn K Thut in T - HBK
29

EEPROM Data Memory


EEPROM data memory
readable and writable during normal operation indirectly addressed through the Special Function Register (SFR)

SRFs are:
EECON1 EECON2 EEDATA EEADR
B mn K Thut in T - HBK
30

15

2/6/2012

EECON1 Register (Adr. 88h)


bit 7-5 Unimplemented: Read as '0' bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) 0 = The write operation completed 1 = Allows write cycles 0 = Inhibits write to the EEPROM 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the EEPROM is complete 1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read 31

bit 3 WRERR: EEPROM Error Flag bit


bit 2 WREN: EEPROM Write Enable bit


bit 1 WR: Write Control bit


bit 0 RD: Read Control bit


B mn K Thut in T - HBK

Reading The EEPROM Data Memory


Reading the EEPROM data memory
write the address to the EEADR register set control bit RD the data us available, in the next cycle, in the EEDATA register
BCF STATUS, RP0 MOVLW CONFIG_ADDR MOVWF EEADR BSF STATUS, RP0 BSF EECON1, RD BCF STATUS, RP0 MOVF EEDATA, W ; Bank 0 ; ; Address to read ; Bank 1 ; EE Read ; Bank 0 ; W = EEDATA

B mn K Thut in T - HBK

32

16

2/6/2012

Writing to the EEPROM Data Memory


Writing to the EEPROM data memory
write the address to the EEADR register and data to the EEDATA register follow a specific sequence to initiate the write for each byte
BSF STATUS, RP0 BCF INTCON, GIE BSF EECON1, WREN MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1,WR BSF INTCON, GIE ; Bank 1 ; Disable INTs. ; Enable Write ; ; Write 55h ; ; Write AAh ; Set WR bit ; begin write ; Enable INTs.

Requirement

B mn K Thut in T - HBK

33

I/O Port
PORT A:
5-bit wide, bi-direction port Corresponding data direction register is TRISA (TRISB bit = 1: input; TRISB bit = 0: output) On a Power-on Reset, PORTA pins are configured as inputs and read as 0

PORT B:
8-bit wide, bi-direction port Corresponding data direction register is TRISB RB7:RB4, have an interrupt-on-change feature
B mn K Thut in T - HBK
34

17

2/6/2012

I/O Port
Initializing Port A
BCF STATUS, RP0 ; CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0x0F ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA4 as output ; TRISA<7:5> are always ; read as 0.
B mn K Thut in T - HBK

Initializing Port B
BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

35

Assignments
What are 8-bit and 16-bit families of PIC microcontrollers? What is maximum frequency of clock input for the PIC16F84A? How many word of program memory are physically implemented in PIC16F84A? 4. What is the maximum memory space the PIC16F84A can address? 5. What is the address of the PORT A? 6. What is the address of the Status Register? 7. How to set all bits of Port A as outputs? 8. How many program calls and interrupts can the stack handle? 9. How many bytes are there for EEPROM of the PIC16F84A? 10. Show how to read the EEPROM data memory for PIC16F84A? 11. Show how to write the EEPROM data memory for PIC16F84A? 12. Show how to perform write verification for PIC16F84A? 1. 2. 3.

B mn K Thut in T - HBK

36

18

2/6/2012

Assignments
1. Design a PIC16F84 schematic in which
Port A is input, connected with 4 buttons Port B is output, connected with 4 LEDs

Write a program to control 4 LEDs by 4 buttons 2. Design a PIC16F84 schematic in which


PIC16F84 interfaces with ADC0808 and 4-digit 7-segment LED through Port B RA0 and RA1 are to select digits of 7-segment LED RA2 is to control START signal of ADC0808 RA3 is to control OE signal of ADC0808

B mn K Thut in T - HBK

37

1.3 The PIC16F87x


PIC16F873/ 874/ 876/ 877
35 single word instructions Operating speed
DC 20MHz clock input DC 200ns instruction cycle

Timer: timer0/timer1/timer2 2 Capturer, Compare, PWM modules 10-bit multi-channel ADC SSP with SPI and I2C USART

B mn K Thut in T - HBK

38

19

2/6/2012

1.3 The PIC16F87x

B mn K Thut in T - HBK

39

PIC16F87x

Block diagram

B mn K Thut in T - HBK

40

20

2/6/2012

The program memory map and stack


PIC16F877/876 PIC16F874/873

B mn K Thut in T - HBK

41

Data memory Organization


Data memory:
partitioned into multiple banks which contain the General Registers and the Special Function Register Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits

Each bank extends up to 7Fh (128 bytes).


The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers

B mn K Thut in T - HBK

42

21

2/6/2012

General Purpose Register File (1)

B mn K Thut in T - HBK

43

General Purpose Register File (2)

B mn K Thut in T - HBK

44

22

2/6/2012

Special Function Registers (1)

Reference: 16F87X datasheet


B mn K Thut in T - HBK
45

Special Function Registers (2)

B mn K Thut in T - HBK

46

23

2/6/2012

PCL and PCLATH


The program counter (PC) is 13bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of Loading of PC in different situations: the PC will be cleared.

how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH)
47

B mn K Thut in T - HBK

Stack
The PIC16F87X family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

B mn K Thut in T - HBK

48

24

2/6/2012

Program Memory Paging (1)


All PIC16F87X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction
B mn K Thut in T - HBK
49

Program Memory Paging (2)


Example:
call of a subroutine in page 1 from page 0 assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : ORG 0x900 SUB1_P1 : : RETURN ;called subroutine page 1 (800h-FFFh) ;return to Call subroutine ;in page 0 (000h-7FFh)

;Select page 1 (800h-FFFh) ;Call subroutine in page 1 (800h-FFFh) ;page 1 (800h-FFFh)

B mn K Thut in T - HBK

50

25

2/6/2012

Indirect Addressing (1)


Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0) will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8bit FSR register and the IRP bit (STATUS<7>),

B mn K Thut in T - HBK

51

Indirect Addressing (2)

B mn K Thut in T - HBK

52

26

2/6/2012

Indirect Addressing (3)


A simple program to clear RAM locations 20h-2Fh using indirect addressing
MOVLW 0x20 MOVWF FSR NEXT CLRF INDF FSR,F BTFSS FSR,4 GOTO NEXT CONTINUE : ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue

B mn K Thut in T - HBK

53

IO Ports
Port A Support Width Direction Direction register Buffer
16F87X 6-bit

Port B
16F87X 8-bit

Port C
16F87X 8-bit

Port D
PIC16F874 /877 8-bit

Port E
PIC16F874 /877 3-bit

Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional TRISA TTL buffer / Schmitt trigger TRISB TTL buffer / Schmitt trigger TRISC Schmitt trigger TRISD Schmitt trigger TRISE Schmitt trigger Analog input

Multiplexed Analog input with

Serial USART, PWM, Parallel slave Programming I2C, SPI port

B mn K Thut in T - HBK

54

27

2/6/2012

Port A Functions

B mn K Thut in T - HBK

55

Port B Functions

B mn K Thut in T - HBK

56

28

2/6/2012

Port C Functions

B mn K Thut in T - HBK

57

Port D Functions

B mn K Thut in T - HBK

58

29

2/6/2012

Port E Functions

B mn K Thut in T - HBK

59

Initializing IO Ports
Example: initializing Port A
BCF BCF CLRF STATUS, RP0 STATUS, RP1 PORTA ; ; Bank0 ; Initialize PORTA by ; clearing output ; data latches ; Select Bank 1 ; Configure all pins ; as digital inputs ; Value used to ; initialize data ; direction ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6>are always ; read as 0.
60

BSF MOVLW MOVWF MOVLW

STATUS, RP0 0x06 ADCON1 0xCF

MOVWF TRISA

B mn K Thut in T - HBK

30

2/6/2012

PIC16CXXX Instruction Set (1)

B mn K Thut in T - HBK

61

PIC16CXXX Instruction Set (2)

B mn K Thut in T - HBK

62

31

2/6/2012

Class Assignment
1. What are main differences between PIC16F84 and PIC16F87x? 2. What is the capacity of the FLASH memory of PIC16F877? 3. How many IO ports of PIC16F873 are there? 4. What are multiplexed with PORTC ? 5. How to initialize Port C as output of PIC16F877? 6. What is the address of TRISB? 7. Is PCLATCH affected by PUSH and POP operation?

B mn K Thut in T - HBK

63

PIC Applications
LED Flasher
Loop: bsf call bcf call goto PORTB, 0 Delay_500ms PORTB, 0 Delay_500ms Loop

B mn K Thut in T - HBK

64

32

2/6/2012

PIC Applications
Button Read
Movlw movwf bsf Loop: btfsc goto goto Light: bsf goto No_light: bcf goto PORTB,0 Loop PORTB,0 Loop PORTD, 2 light No_light 0 TRISD, f TRISD, 2

B mn K Thut in T - HBK

65

33

You might also like