LCL 171

ulglLal ClrculLs

rof. Mark C. lausL

Maseeh College of Lnglneerlng
and CompuLer Sclence
LecLure 13
- 1oplcs
- LaLches
- lllp llops
- AlgorlLhmlc SLaLe Machlnes
2
osslble SLaLes for LlghL SwlLch
3
S-8 LaLch
S R Q
+
0 0 Q
0 1 0
1 0 1
1 1 0
S-R latch is reset dominant
4
AlLernauve nomenclaLure
Present State Next State
Output Symbol Output Symbol
Q Q
Q Q(t+1)
Qt Q(t+1)
Qn Q(n+1)
Q0 Q
Y Y
+
y Y
3
S-8 LaLch SLaLes
S-R latch is
reset dominant
6
CharacLerlsuc Lquauons
7
resenL SLaLe/nexL SLaLe 1able
(S/nS)
8
1lmlng ulagram
9
8aces
Critical Race
Non-critical Race
10
MeLasLable SLaLe
An often overlooked condition in which the output can remain
in an illegal (even oscillating) state for an indeterminant period
of time.

Metastability can be caused by a runt pulse (a positive or
negative pulse which never achieves either a value of a 1 or 0).
This can occur when two inputs to a gate change near
simultaneously (see hazards earlier).

Metastability can also when two inputs to a latch change near
simultaneously.

Condition also arises when synchronizing with external events
(e.g. asynchronous inputs to synchronous finite state machines).
11
SLaLe ulagrams
S R Q
+
0 0 Q
0 1 0
1 0 1
1 1 0
S R Q Q
+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
12
AlgorlLhmlc SLaLe Machlnes
(ASM)
13
Clock (CsclllaLor) ClrculL
- S/nS 1able
- k-map
- SLaLe ulagram
- uelay Model
14
Clock Waveforms
- uelay
- 8uers
- Addluonal (malnLaln odd number) lnverLers
- 8C clrculL
- CrysLal CsclllaLor
13
CaLed Sequenual ClrculLs
- Addluon of conLrol lnpuL
- CaLed LaLch (Level AcuvaLed)
- Ldge-1rlggered lllp llop
- ulse 1rlggered lllp llop
16
CaLed S8 LaLch
17
CaLed S8 LaLch uslng nAnus
18
CaLed u LaLch
D Q
+
0 0
1 1
19
CaLed u LaLch 1lmlng
20
use as SLorage LlemenLs
21
lllp llop ClrculLs
Pulse Narrowing Circuit
22
Ldge-1rlggered u lllp llop
23
Manual 8eseL of u lllp llop
24
74LS74A
23
!k lllp llops
J K Q
+
Comment

0 0 Q No change
0 1 0 Reset
1 0 1 Set
1 1 Q Toggle
26
1 lllp llops
J = K=T Q
+
Comment

0 0 0 Q No change
0 1
1 0
1 1 1 Q Toggle
27
SLaLe ulagrams for 8lnary up CounLers
28
4-8lL 8lnary up CounLer
29
CounLer 1lmlng ulagram
30
SLaLe Machlnes
- SLaLe 1ransluon ulagrams
- nexL SLaLe 1ables
- Mealy and Moore Machlnes
- Mealy: CuLpuL loglc uses currenL sLaLe and lnpuLs
- Moore: CuLpuL loglc uses only currenL sLaLe
- Cne PoL vs. Lncoded SLaLe Machlnes
31
1-blrd Lall-llghLs example
32
SLaLe
dlagram
Inputs:"
LEFT, RIGHT, HAZ"
"
Outputs:"
Six lamps"
(function of state only)"
33
Lncoded or Cne-PoL?
- Lncoded
- 8 sLaLes
- 2
3
= 8
- need 3 lp ops
- need Lo deLermlne sLaLe asslgnmenL
- Cne-hoL
- uedlcaLe a lp op per sLaLe
- need 8 lp ops
34
lmplemenLauon
(Lncoded, Moore Machlne)
Next
State
Logic
Output
Logic
Inputs
Outputs
Current State
33
CuLpuL loglc
LC = L3 + L83
L8 = L2 + L3 + L83
LA = L1 + L2 + L3 + L83
8A = 81 + 82 + 83 + L83
88 = 82 + 83 + L83
8C = 83 + L83
36
LC = C2'!C1!C0' + C2!C1'!C0'
L8 = C2'!C1!C0 + C2'!C1!C0' + C2!C1'!C0'
LA = C2'!C1'!C0 + C2'!C1!C0 + C2'!C1!C0' + C2!C1'!C0'
8A = C2!C1'!C0 + C2!C1!C0 + C2!C1!C0' + C2!C1'!C0'
88 = C2!C1!C0 + C2!C1!C0' + C2!C1'!C0'
8C = C2!C1!C0' + C2!C1'!C0'
C2
C1
C0
nexL SLaLe Loglc
- SLaLe Lransluon Lable for encoded sLaLes
- nexL sLep depends on lmplemenLauon cholce
- SynLheslze or SLrucLural wlLh cholce of lls
37
1ransluon Lquauons
38
C2* = C2'! C1' ! C0' ! (PAZ + LLl1 ! 8lCP1)
+ C2' ! C1' ! C0' ! (8lCP1 ! PAZ' ! LLl1')
+ C2' ! C1' ! C0 ! (PAZ)
+ C2' ! C1 ! C0 ! (PAZ)
+ C2 ! C1' ! C0 ! (PAZ')
+ C2 ! C1' ! C0 ! (PAZ)
+ C2 ! C1 ! C0 ! (PAZ')
+ C2 ! C1 ! C0 ! (PAZ)
C2* = C2'! C1' ! C0' ! (PAZ + 8lCP1)
+ C2' ! C0' ! PAZ
+ C2' ! C0
1ransluon Lquauons
39
C1* = C2' ! C1' ! C0 ! (PAZ')
+ C2' ! C1 ! C0 ! (PAZ')
+ C2 ! C1' ! C0 ! (PAZ')
+ C2 ! C1 ! C0 ! (PAZ')
C1* = C0 ! PAZ'
1ransluon Lquauons
40
C0* = C2' ! C1' ! C0' ! (LLl1 ! PAZ' ! 8lCP1')
+ C2' ! C1' ! C0 ! (8lCP1 ! PAZ' ! LLl1')
+ C2' ! C1' ! C0 ! (PAZ')
+ C2 ! C1' ! C0 ! (PAZ')
C0* = C2'! C1' ! C0' ! (LLl1 " 8lCP1)
lmplemenLauon
(Lncoded, Moore Machlne)
Next
State
Logic
Output
Logic
Inputs
Outputs
Current State
41
WhaL should Lhe clock's perlod be?
Pow lasL Can Lhe Clock 8e?
42
Comblnauonal
Loglc
Clock
u1
C
u2
ll L
pd
Comblnauonal L
pd
ll L
seLup
ll 1 ll 2
Clock Skew
43
Clock
u1
C
u2
ll L
pd
Comblnauonal L
pd
ll L
seLup
Lven wlLh careful rouung, clock wlll noL arrlve
aL all lls aL Lhe same ume. 1hls skew ln clock
arrlval ume aecLs max clock raLe.

Clock Skew

Clock erlod
mln
= ll L
pd
+ ll L
seLup
+ C L
pd
+ L
skew
44
Cne-PoL
43
luLL* = luLL ! (PAZ + LLl1 + 8lCP1)' + L3 + 83 + L83

L1* = luLL ! LLl1 ! PAZ' ! 8lCP1'

81* = luLL ! 8lCP1 ! PAZ' ! LLl1'

L2* = L1 ! PAZ'

82* = 81 ! PAZ'

L3* = L2 ! PAZ'

83* = 82 ! PAZ'

L83* = luLL ! (PAZ + LLl1 ! 8lCP1) + (L1 + L2 + 81 + 82) ! PAZ
8euer Sull - 8ehavloral verllog
46
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'54'''','-./010000002'
'*54''','-./100000006'
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Lxample: 1ramc LlghL ConLroller
47
n
S
L W
Sensors ln road deLecL approachlng car on nS and LW
roads, generaung lnpuL slgnals nScar and LWcar
respecuvely.
LlghLs are conLrolled by ouLpuLs nSllLe and LWllLe.
1ramc llghLs should change only lf Lhere ls a car
approachlng from Lhe oLher dlrecuon. CLherwlse Lhe
llghLs should remaln unchanged.
nScar
LWcar
Clock
1ramc
LlghL
ConLroller
nSllLe
LWllLe
r
Lxample: 1ramc LlghL ConLroller
48
r
SLaLe asslgnmenL
nSgreen = 0
LWgreen = 1
Lxample: Serlal Llne Code ConverLer
49
8lLln
8lLClock
Clock
Clear
n8Z Lo
ManchesLer
Lncoder
8lLCuL
S0
0
S1
0
S3
1
S2
1
0
0 0
1
1 1
f
lSM Clock
= 2 x f
8lLClock
n8Z Lo ManchesLer (Moore lSM)
30
S0
0
S1
0
S3
1
S2
1
0
0 0
1
1 1
0ns 50ns 100ns 150ns 200ns 250ns 300ns
TestBench.BitOut
TestBench.Clear
TestBench.BitClock
TestBench.FSMClock
TestBench.BitIn
8lslng edge of 8lLClock colncldes wlLh rlslng edge of
lSM clock.
8lLln changes aL falllng edge of 8lLClock
use falllng edge of lSM clock for synchronlzauon (wlll
be aL mldpolnL of blL ume) so no danger of sampllng
8lLClock whlle lL's changlng
31
//
// Moore FSM for serial line conversion: NRZ to Manchester encoding
//

module NRZtoManchester(Clock, Clear, BitIn, BitOut);
input Clock, Clear, BitIn;
output BitOut;
reg BitOut;

// define states using same names and state assignments as state diagram and table
// Using one-hot method, we have one bit per state

parameter
S0 = 4'b0001,
S1 = 4'b0010,
S2 = 4'b0100,
S3 = 4'b1000;
reg [3:0] State, NextState;


// Update state or reset on every - clock edge

always @(negedge Clock)
begin
if (Clear)
begin
State <= S0;
$display("Reset: S0");
end
else
begin
State <= NextState;
$display("State: %d",State);
end
end
32
// Outputs depend only upon state (Moore machine)

always @(State)
begin
case (State)
S0: BitOut = 1'b0;
S1: BitOut = 1'b0;
S2: BitOut = 1'b1;
S3: BitOut = 1'b1;
endcase
end

// Next state generation logic

always @(State or BitIn)
begin
case (State)
S0: if (BitIn)
NextState = S3;
else
NextState = S1;
S1: if (BitIn)
$display("S1 Error!");
else
NextState = S2;
S2: if (BitIn)
NextState = S3;
else
NextState = S1;
S3: if (BitIn)
NextState = S0;
else
$display("S3 Error!");
endcase
end
endmodule
Alrplane Landlng Cear Lxample
33
Lever
Cearup
Alrplane
Landlng
Cear
ConLrol
valve
CnCround
Cearuown
ump
8edLLu
CreenLLu
Lever
CperaLed by plloL Lo conLrol landlng gear
(0:down 1:up)
CnCround
Sensor 1 when plane on ground
Cearup
Sensor 1 when landlng gear fully up
Cearuown
Sensor 1 when landlng gear fully down
valve
ConLrols posluon of valve (0:lowerlng 1:ralslng)
ump
AcuvaLes hydraullc pump
8edLLu
lndlcaLes landlng gear ln mouon
CreenLLu
lndlcaLes landlng gear down
uo noL reLracL landlng gear lf plane on ground
8espond Lo changes ln lever posluon
(ln case plane sLarLed wlLh lever ln up posluon)
lane should be alrborne Lwo seconds before
reLracung gear

1ypes of lSMs
33
state feedback
inputs
outputs reg
combinational
logic for
next state logic for
outputs
inputs outputs
state feedback
reg
combinational
logic for
next state
logic for
outputs
inputs outputs
state feedback
reg
combinational
logic for
next state
logic for
outputs
Moore
Mealy
Synchronous Mealy
vendlng Machlne Lxample
- 1aken from kaLz & 8orrlello,
ConLemporary Loglc ueslgn"
36
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
37
Vending
Machine
FSM
N
D
Reset
Clock
Open
Coin
Sensor
Release
Mechanism
Lxample: vendlng machlne
- 8elease lLem aer 13 cenLs are deposlLed
- Slngle coln sloL for dlmes, nlckels
- no change
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
38
Lxample: vendlng machlne
- SulLable absLracL represenLauon
- LabulaLe Lyplcal lnpuL sequences:
- 3 nlckels
- nlckel, dlme
- dlme, nlckel
- Lwo dlmes
- draw sLaLe dlagram:
- lnpuLs: n, u, reseL
- ouLpuL: open chuLe
- assumpuons:
- assume n and u asserLed
for one cycle
- each sLaLe has a self loop
for n = u = 0 (no coln)
S0
Reset
S2
D
S6
[open]
D
S4
[open]
D
S1
N
S3
N
S5
[open]
N
S8
[open]
D
S7
[open]
N
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
39
Lxample: vendlng machlne
- Mlnlmlze number of sLaLes - reuse sLaLes whenever posslble
symbolic state table
present inputs next output
state D N state open
0 0 0 0 0
0 1 5 0
1 0 10 0
1 1
5 0 0 5 0
0 1 10 0
1 0 15 0
1 1
10 0 0 10 0
0 1 15 0
1 0 15 0
1 1
15 15 1
0
Reset
5
N
N
N + D
10
D
15
[open]
D
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
60
present state inputs next state output
Q1 Q0 D N D1 D0 open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1
1 1 1 1 1

Lxample: vendlng machlne
- unlquely encode sLaLes
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
61
D1 = Q1 + D + Q0 N
D0 = Q0 N + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
Lxample: Moore lmplemenLauon
- Mapplng Lo loglc
0 0 1 1
0 1 1 1
X X 1 X
1 1 1 1
Q1
D1
Q0
N
D
0 1 1 0
1 0 1 1
X X 1 X
0 1 1 1
Q1
D0
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1
Open
Q0
N
D
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
62
present state inputs next state output
Q3 Q2 Q1 Q0 D N D3 D2 D1 D0 open
0 0 0 1 0 0 0 0 0 1 0
0 1 0 0 1 0 0
1 0 0 1 0 0 0
1 1 - - - - -
0 0 1 0 0 0 0 0 1 0 0
0 1 0 1 0 0 0
1 0 1 0 0 0 0
1 1 - - - - -
0 1 0 0 0 0 0 1 0 0 0
0 1 1 0 0 0 0
1 0 1 0 0 0 0
1 1 - - - - -
1 0 0 0 - - 1 0 0 0 1
D0 = Q0 D N
D1 = Q0 N + Q1 D N
D2 = Q0 D + Q1 N + Q2 D N
D3 = Q1 D + Q2 D + Q2 N + Q3
OPEN = Q3
Lxample: vendlng machlne
- Cne-hoL encodlng
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
63
Mealy and Moore sLaLe dlagrams
- Moore machlne
- ouLpuLs assoclaLed wlLh sLaLe
0
[0]
10
[0]
5
[0]
15
[1]
N D + Reset
D
D
N
N+D
N
N D
Reset
N D
N D
Reset
0
10
5
15
(N D + Reset)/0
D/0
D/1
N/0
N+D/1
N/0
N D/0
Reset/1
N D/0
N D/0
Reset/0
! Mealy machine
" outputs associated with
transitions
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
64
Lxample: Mealy lmplemenLauon
0
10
5
15
Reset/0
D/0
D/1
N/0
N+D/1
N/0
N D/0
Reset/1
N D/0
N D/0
Reset/0
present state inputs next state output
Q1 Q0 D N D1 D0 open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 1
1 1
1 0 0 0 1 0 0
0 1 1 1 1
1 0 1 1 1
1 1
1 1 1 1 1

D0 = Q0N + Q0N + Q1N + Q1D
D1 = Q1 + D + Q0N
OPEN = Q1Q0 + Q1N + Q1D + Q0D
0 0 1 0
0 0 1 1
X X 1 X
0 1 1 1
Q1
Open
Q0
N
D
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
63
Lxample: Mealy lmplemenLauon
D0 = Q0N + Q0N + Q1N + Q1D
D1 = Q1 + D + Q0N
OPEN = Q1Q0 + Q1N + Q1D + Q0D


make sure OPEN is 0 when reset
by adding AND gate
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
66
Moore Lo synchronous Mealy
- CLn = C1C0 creaLes a comblnauonal delay aer C1 and C0 change ln
Moore lmplemenLauon
- 1hls can be correcLed by reumlng, l.e., move lp-ops and loglc Lhrough each
oLher Lo lmprove delay
- CLn.d = (C1 + u + C0n)(C0'n + C0n' + C1n + C1u)
= C1C0n' + C1n + C1u + C0'nu + C0n'u
- lmplemenLauon now looks llke a synchronous Mealy machlne
- lL ls common for programmable devlces Lo have ll aL end of loglc
vll - llnlLe SLaLe
Machlnes
CopyrlghL 2004, CaeLano 8orrlello
and 8andy P. kaLz
67
Mealy Lo synchronous Mealy
- CLn.d = C1C0 + C1n + C1u + C0u
- CLn.d = (C1 + u + C0n)(C0'n + C0n' + C1n + C1u)
= C1C0n' + C1n + C1u + C0'nu + C0n'u
0 0 1 0
0 0 1 1
1 0 1 1
0 1 1 1
Q1
Open.d
Q0
N
D
0 0 1 0
0 0 1 1
X X 1 X
0 1 1 1
Q1
Open.d
Q0
N
D