Physical Design with SOC Encounter v7.

1 (Created on 19-Apr-2010)

1. Add I/O Pads to your schematics. (Please refer to the corresponding notes). 2. Go to icfb windows -> Tools -> Verilog Integration -> NC-verilog to open Virtuoso Schematic Composer Analysis Environment for NC-Verilog Integration window. 3. When the NC-Verilog is opened, select Browse to choose your design, then press Initial Design and Generate Netlist. 4. The netlist is generated in the XXX_run1/ihnl/cdsYY/netlist directory, where XXX is your design name and YY is a number depends on your hierarchy level. 5. Create a folder named encounter and create a folder named verilog and another named work_fe under the encounter folder. Copy all the files named netlist under cdsxx into that verilog directory. 6. Add the Corner Pad to the top level verilog file(e.g. cds12.v), just before the statement endmodule.

7. To run the Clock Tree Synthesis in SOC Encounter, we need to integrate those cdsxx files into single verilog code by cascading them together first. For example, create a new file topout.v, copy the content of cds0/netlist to topout.v, and then cds1 and so on. For Encounter 9.1, please open topout.v and replace all cds_globals.gnd_ with gnd and cds_globals.vdd_ with vdd. 8. When the file topout.v is ready, in the unix console, type uniquifyNetlist top <top_cell_name> <output_netlist_name> <input_netlist_name>, for the case used
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in this tutorial, top cell name is FIR_filter, so the command is uniquifyNetlist top FIR_filter topout_new.v topout.v.

9. After the topout_new.v is generated successfully, type encounter in the console to launch SOC Encounter. 10. Download the LEF files and the TLF files from the courses website. Put all these files into the encounter directory. 11. In the main window, click Design -> Import Design. Then the following window appears. Add the .v file (i.e. topout_new.v in this tutorial) in Verilog Netlist. Then add the Common Timing Libraries and LEF files in the way similar to the screen dump below. Please be aware that these files must be added in the EXACT SAME order as shown in the screen dump below. Or error will occur.

12. Then go to Advanced panel. In the Power Session, make the same configuration as shown below. Then click Save to save the configuration. Then click OK to import your design.

13. After importing your design, you can click Design -> Save Design As -> SoCE to save you design into .enc file format. You should perform this action regularly during the whole process. To load your design, click Design -> Restore Design -> SoCE and select the .enc file that you saved previously. 14. Click Design -> Save -> I/O File to save you I/O file.

15. Open the IO file that you have just saved using text editor like emacs or pico. Then make the following modification:
Before
(bottomleft (inst name="C1" ) (inst name="C2" ) (inst name="C3" ) (inst name="C4" ) )

After: (bottomleft (inst name="C1" ) ) (bottomright

(inst name="C2" ) ) (topleft (inst name="C3" ) ) (topright (inst name="C4" ) )

Save the IO file and return back to Encounter. 16. Click Design -> Import Design and add the IO file that you have just modified. Then click Save to save the configuration. Then click OK.

17. Click Load -> I/O file to load the modified I/O file. Then save your design and

restore it again to make the modification effective. 18. Click Floorplan -> Specify Floorplan. Set Ratio (H/W) to 1 and Core Utilization to 0.7. Then the Core to XX values are all set to 400. Then click OK.

19. Click Floorplan -> Connect Global Nets. Then make configuration in the way

specified in the following table and screen dump. Click Apply and then click Close after configuration.

20. Click Power -> Power Planning -> Add Rings. Type gnd! Vdd! In the Net(s) line.

Set ring width to 15, spacing to 2, offset to 15. Click OK.

21. Click Power -> Power Planning -> Add Stripes. Type gnd! Vdd! In the Net(s) line. Set width to 15, spacing to 2. Since in this project 1 pair of supply stripes should be enough, therefore you should set the value of X from left and X from right to make these 2 stripes in the middle of the core. Then Click OK. Remember to save your design regularly.

22. Place the endcap cells: click Place->Filler->Add End Cap. Use Select to select ENDCAPL as Pre Cap Cell and ENDCAPR as Post Cap Cell. Leave others as default and click OK. 23. Click Place -> Standard Cells. Then click Mode button. Then enable Run Timing Driven Placement. Click OK twice to run the cell placement.

24. Clock Tree Synthesis (CTS): select Clock -> Design Clock. Use topview.ctstch as the

Clock Specification Files and press OK. You can download topview.ctstch on the web page. In this file, you need to modify the line AutoCTSRootPin, default is instance name I1/Y, you can find the instance name of your design from schematic CLK signal pin. For example, if your CLK pad instance name is I123, then update the line to AutoCTSRootPin I123/Y. Then Click OK to run the CTS. It may take more than 10 minutes to complete CTS.

25. Place the core filler cells: Click Place->Filler->Add Filler. Select FILL1, FILL2, FILL5, FILL10, FILL25 as Cell Name(s). Leave other settings as default and press OK. 26. Click Route -> Special Route. Use default setting. Click OK. Some warnings may appear. Just ignore it for this project. 27. Click Route -> Nanoroute -> Route. Enable Timing Driven. Click OK to run NanaRoute. It may take several hours to complete. You are recommended to save
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your design and then restart Encounter after this step. Otherwise you may not be able to proceed to next step. 28. Click Timing -> Analysis Condition -> Specify RC Extraction Mode. Set mode to Detail. Then Click OK. After that click Timing -> Extract RC. Unselect all options and click OK. 29. Click Timing -> Calculate Delay. Unselect Ideal Clock. Then click OK. SDF will be generated and it will be used in Post-layout simulation. 30. Generate the GDS file: click Design->Save->GDS. Use topview.gds as the output stream file name, leave others as default and click OK.

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