OPA

627

OPA627 OPA637

OPA

627

Precision High-Speed Difet OPERATIONAL AMPLIFIERS

FEATURES
q VERY LOW NOISE: 4.5nV/Hz at 10kHz q FAST SETTLING TIME: OPA627550ns to 0.01% OPA637450ns to 0.01% q LOW VOS: 100V max q LOW DRIFT: 0.8V/C max q LOW IB: 5pA max q OPA627: Unity-Gain Stable q OPA637: Stable in Gain 5

APPLICATIONS
q PRECISION INSTRUMENTATION q FAST DATA ACQUISITION q DAC OUTPUT AMPLIFIER q OPTOELECTRONICS q SONAR, ULTRASOUND q HIGH-IMPEDANCE SENSOR AMPS q HIGH-PERFORMANCE AUDIO CIRCUITRY q ACTIVE FILTERS High frequency complementary transistors allow increased circuit bandwidth, attaining dynamic performance not possible with previous precision FET op amps. The OPA627 is unity-gain stable. The OPA637 is stable in gains equal to or greater than five.

DESCRIPTION
The OPA627 and OPA637 Difet operational amplifiers provide a new level of performance in a precision FET op amp. When compared to the popular OPA111 op amp, the OPA627/637 has lower noise, lower offset voltage, and much higher speed. It is useful in a broad range of precision and high speed analog circuitry. The OPA627/637 is fabricated on a high-speed, dielectrically-isolated complementary NPN/PNP process. It operates over a wide range of power supply voltage 4.5V to 18V. Laser-trimmed Difet input circuitry provides high accuracy and low-noise performance comparable with the best bipolar-input op amps.
Trim 1

Difet fabrication achieves extremely low input bias currents without compromising input voltage noise performance. Low input bias current is maintained over a wide input common-mode voltage range with unique cascode circuitry.
The OPA627/637 is available in plastic DIP, SOIC and metal TO-99 packages. Industrial and military temperature range models are available.
7 +VS 5

Trim

Output 6 +In 3 In 2

Difet , Burr-Brown Corp.

VS 4

International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

1989 Burr-Brown Corporation

PDS-998H

Printed in U.S.A. March, 1998

SBOS165

SPECIFICATIONS
ELECTRICAL
At TA = +25C, and VS = 15V, unless otherwise noted. OPA627BM, BP, SM OPA637BM, BP, SM PARAMETER OFFSET VOLTAGE (1) Input Offset Voltage AP, BP, AU Grades Average Drift AP, BP, AU Grades Power Supply Rejection INPUT BIAS CURRENT (2) Input Bias Current Over Specified Temperature SM Grade Over Common-Mode Voltage Input Offset Current Over Specified Temperature SM Grade NOISE Input Voltage Noise Noise Density: f = 10Hz f = 100Hz f = 1kHz f = 10kHz Voltage Noise, BW = 0.1Hz to 10Hz Input Bias Current Noise Noise Density, f = 100Hz Current Noise, BW = 0.1Hz to 10Hz INPUT IMPEDANCE Differential Common-Mode INPUT VOLTAGE RANGE Common-Mode Input Range Over Specified Temperature Common-Mode Rejection OPEN-LOOP GAIN Open-Loop Voltage Gain Over Specified Temperature SM Grade FREQUENCY RESPONSE Slew Rate: OPA627 OPA637 Settling Time: OPA627 0.01% 0.1% OPA637 0.01% 0.1% Gain-Bandwidth Product: OPA627 OPA637 Total Harmonic Distortion + Noise POWER SUPPLY Specified Operating Voltage Operating Voltage Range Current OUTPUT Voltage Output Over Specified Temperature Current Output Short-Circuit Current Output Impedance, Open-Loop TEMPERATURE RANGE Specification: AP, BP, AM, BM, AU SM Storage: AM, BM, SM AP, BP, AU J-A: AM, BM, SM AP, BP AU RL = 1k VO = 10V 1MHz 25 55 60 40 200 100 160 11 10.5 106 112 106 100 40 100 CONDITIONS MIN TYP 40 100 0.4 0.8 120 1 MAX 100 250 0.8 2 100 5 1 50 5 1 50 OPA627AM, AP, AU OPA637AM, AP, AU MIN TYP 130 280 1.2 2.5 116 2 MAX 250 500 2 UNITS V V V/ C V/ C dB pA nA nA pA pA nA nA

VS = 4.5 to 18V VCM = 0V VCM = 0V VCM = 0V VCM = 10V VCM = 0V VCM = 0V

106

10 2

1 0.5

2 1

10 2

15 8 5.2 4.5 0.6 1.6 30 1013 || 8 1013 || 7 11.5 11 116 120 117 114 55 135 550 450 450 300 16 80 0.00003 15 7 12.3 11.5 45 +70/55 55

40 20 8 6 1.6 2.5 60

20 10 5.6 4.8 0.8 2.5 48 * * * * 100 106 100 * * 110 116 110

nV/Hz nV/Hz nV/Hz nV/Hz Vp-p fA/Hz fAp-p || pF || pF V V dB dB dB dB V/s V/s ns ns ns ns MHz MHz % V V mA

VCM = 10.5V VO = 10V, RL = 1k VO = 10V, RL = 1k VO = 10V, RL = 1k G G G G G G 1, 10V Step 4, 10V Step 1, 10V Step 1, 10V Step 4, 10V Step 4, 10V Step G=1 G = 10 G = +1, f = 1kHz = = = = = =

* *

* * * * * * * * * *

4.5

18 7.5

* * * * * * * * *

* *

11.5 11 35

100

V mA mA C C C C C/W C/W C/W

+85 +125 +150 +125

* * * * *

* * *

* Specifications same as B grade. NOTES: (1) Offset voltage measured fully warmed-up. (2) High-speed test at TJ = +25C. See Typical Performance Curves for warmed-up performance. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

OPA627, 637

PIN CONFIGURATIONS
Top View DIP/SOIC

ABSOLUTE MAXIMUM RATINGS(1)

Supply Voltage .................................................................................. 18V Input Voltage Range .............................................. +VS + 2V to VS 2V Differential Input Range ....................................................... Total VS + 4V Power Dissipation ........................................................................ 1000mW Operating Temperature M Package .................................................................. 55C to +125C P, U Package ............................................................. 40C to +125C Storage Temperature M Package .................................................................. 65C to +150C P, U Package ............................................................. 40C to +125C Junction Temperature M Package .................................................................................. +175C P, U Package ............................................................................. +150C Lead Temperature (soldering, 10s) ............................................... +300C SOlC (soldering, 3s) ................................................................... +260C NOTE: (1) Stresses above these ratings may cause permanent damage.

Offset Trim In +In VS

1 2 3 4

8 7 6 5

No Internal Connection +VS Output Offset Trim

Top View

No Internal Connection 8 Offset Trim 1 7 +VS

TO-99

PACKAGE/ORDERING INFORMATION
PRODUCT OPA627AP OPA627BP OPA627AU OPA627AM OPA627BM OPA627SM OPA637AP OPA637BP OPA637AU OPA637AM OPA637BM OPA637SM PACKAGE Plastic DIP Plastic DIP SOIC TO-99 Metal TO-99 Metal TO-99 Metal Plastic DIP Plastic DIP SOIC TO-99 Metal TO-99 Metal TO-99 Metal PACKAGE DRAWING NUMBER(1) 006 006 182 001 001 001 006 006 182 001 001 001 TEMPERATURE RANGE 25C to +85C 25C to +85C 25C to +85C 25C to +85C 25C to +85C 55C to +125C 25C to +85C 25C to +85C 25C to +85C 25C to +85C 25C to +85C 55C to +125C

In

Output

3 +In 4 VS Case connected to VS.

5 Offset Trim

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

OPA627, 637

TYPICAL PERFORMANCE CURVES

At TA = +25 C, and VS = 15V, unless otherwise noted.

INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k 100

TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH p-p

Voltage Noise (nV/ Hz)

Input Voltage Noise (V)

10

100

Noise Bandwidth: 0.1Hz to indicated frequency.

10

0.1

RMS

1 1 10 100 1k 10k 100k 1M 10M Frequency (Hz)

0.01 1 10 100 1k 10k 100k 1M 10M Bandwidth (Hz)

VOLTAGE NOISE vs SOURCE RESISTANCE 1k

OPEN-LOOP GAIN vs FREQUENCY 140 120

Voltage Gain (dB)

Voltage Noise (nV/ Hz)

100

RS

100 80 60 40 20 OPA627

OPA637

OPA627 + Resistor 10

Comparison with OPA27 Bipolar Op Amp + Resistor Spot Noise at 10kHz 1M 10M 100M

Resistor Noise Only 1 100 1k 10k 100k Source Resistance ( )

0 20 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz)

OPA627 GAIN/PHASE vs FREQUENCY 30 90

OPA637 GAIN/PHASE vs FREQUENCY

30

90

Phase (Degrees)

10 Gain 0

75 Phase Margin

Phase 150

Phase 10 Gain 150

180

180

10 1 10 Frequency (MHz)

210 100

10 1 10 Frequency (MHz) 100

210

OPA627, 637

Phase (Degrees)

20
Gain (dB)

120

20
Gain (dB)

120

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25C, and VS = 15V, unless otherwise noted.

OPEN-LOOP GAIN vs TEMPERATURE 125

100

OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY

120
Voltage Gain (dB)

Output Resistance ()

80

60

115

40

110

20

105 75

50

25

25

50

75

100

125

20

200

2k

20k

200k

2M

20M

Temperature (C)

Frequency (Hz)

COMMON-MODE REJECTION vs FREQUENCY 140

COMMON-MODE REJECTION vs INPUT COMMON MODE VOLTAGE 130

Common-Mode Rejection Ratio (dB)

120 100 80 60 40 20 0 1 10 100 1k 10k OPA627

OPA637

Common-Mode Rejection (dB)

120

110

100

90

100k

1M

10M

80 15

10

10

15

Frequency (Hz)

Common-Mode Voltage (V)

POWER-SUPPLY REJECTION vs FREQUENCY 140

Power-Supply Rejection (dB)
125

POWER-SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE

120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz)

105 75 50

PSR

VS PSRR 627 and 637

CMR and PSR (dB)

120

115

CMR

+VS PSRR 627 637

110

25

25

50

75

100

125

Temperature (C)

OPA627, 637

TYPICAL PERFORMANCE CURVES

At TA = +25 C, and VS = 15V, unless otherwise noted.

(CONT)

SUPPLY CURRENT vs TEMPERATURE 8

100

OUTPUT CURRENT LIMIT vs TEMPERATURE

80
Supply Current (mA)

+IL at VO = 0V +IL at VO = +10V

Output Current (mA)

7.5

60

40 IL at VO = 0V 20 IL at VO = 10V

6.5

6 75 50 25 0 25 50 75 100 125 Temperature (C)

0 75 50 25 0 25 50 75 100 125 Temperature (C)

OPA627 GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE 24 60 120

OPA637 GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE 160 Slew Rate

Gain-Bandwidth (MHz)

Gain-Bandwidth (MHz)

Slew Rate 16 55

Slew Rate (V/s)

80 GBW 60

120

12

GBW

100

8 75

50 50 25 0 25 50 75 100 125 Temperature (C)

40 75 50 25 0 25 50 75 100 125 Temperature (C)

80

OPA627 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.1

VI G = +1 + VO = 10V 600 VI G = +10 + 100pF 549 VO = 10V 5k 600

OPA637 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1

VI G = +10 + VO = 10V
5k 600 G = +50

VI

VO = 10V
5k 600

0.01

100pF

0.1
549

100pF
102

100pF

THD+N (%)

0.001

Measurement BW: 80kHz G = +10

THD+N (%)

0.01 G = +50 Measurement BW: 80kHz 0.001

0.0001 G = +1 0.00001 20 100 1k Frequency (Hz) 10k 20k

0.0001 20 100 1k Frequency (Hz)

G = +10 10k 20k

OPA627, 637

Slew Rate (V/s)

20

100

140

TYPICAL PERFORMANCE CURVES

At TA = +25C, and VS = 15V, unless otherwise noted.

(CONT)

INPUT BIAS AND OFFSET CURRENT vs JUNCTION TEMPERATURE 10k

20

INPUT BIAS CURRENT vs POWER SUPPLY VOLTAGE NOTE: Measured fully warmed-up. 15 TO-99 10 Plastic DIP, SOIC

100

IB IOS

10

Input Bias Current (pA)

1k Input Current (pA)

TO-99 with 0807HS Heat Sink

0.1 50 25 0 25 50 75 100 125 150 Junction Temperature (C)

10

12

14

16

18

Supply Voltage (VS)

INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE 1.2

Input Bias Current Multiplier
Offset Voltage Change (V)

INPUT OFFSET VOLTAGE WARM-UP vs TIME 50

1.1

Beyond Linear Common-Mode Range

25

0.9

Beyond Linear Common-Mode Range

25

0.8 15 10 5 0 5 Common-Mode Voltage (V) 10 15

50 0 1 2 3 4 5 6 Time From Power Turn-On (Min)

MAX OUTPUT VOLTAGE vs FREQUENCY 30

SETTLING TIME vs CLOSED-LOOP GAIN 100

Output Voltage (Vp-p)

Error Band: 0.01%

Settling Time (s)

20

10 OPA627

OPA637 10 OPA627

OPA637

0 100k 1M Frequency (Hz) 10M 100M

0.1 1 10 100 1000 Closed-Loop Gain (V/V)

OPA627, 637

TYPICAL PERFORMANCE CURVES

At TA = +25 C, and VS = 15V, unless otherwise noted.

(CONT)

SETTLING TIME vs ERROR BAND 1500 RI

SETTLING TIME vs LOAD CAPACITANCE 3

CF +5V RF 2k 5V
+

Settling Time (ns)

1000

Settling Time (s)

OPA627 RI 2k RF 2k CF 6pF

OPA637 500 2k 4pF

Error Band: 0.01%

OPA637 G = 4

500 OPA637 G = 4 0 0.001

OPA627 G = 1

OPA627 G = 1

0 0.01 0.1 Error Band (%) 1 10 0 150 200 300 400 500 Load Capacitance (pF)

APPLICATIONS INFORMATION
The OPA627 is unity-gain stable. The OPA637 may be used to achieve higher speed and bandwidth in circuits with noise gain greater than five. Noise gain refers to the closed-loop gain of a circuit as if the non-inverting op amp input were being driven. For example, the OPA637 may be used in a non-inverting amplifier with gain greater than five, or an inverting amplifier of gain greater than four. When choosing between the OPA627 or OPA637, it is important to consider the high frequency noise gain of your circuit configuration. Circuits with a feedback capacitor (Figure 1) place the op amp in unity noise-gain at high frequency. These applications must use the OPA627 for proper stability. An exception is the circuit in Figure 2, where a small feedback capacitance is used to compensate for the input capacitance at the op amps inverting input. In this case, the closed-loop noise gain remains constant with frequency, so if the closed-loop gain is equal to five or greater, the OPA637 may be used.
+ OPA627 Buffer RI

RF < 4RI + Non-Inverting Amp G<5 OPA627

RF < 4R + OPA627 RI + OPA627

Bandwidth Limiting

Inverting Amp G < |4|

OPA627

OPA627

Integrator

Filter

FIGURE 1. Circuits with Noise Gain Less than Five Require the OPA627 for Proper Stability.

OPA627, 637

OFFSET VOLTAGE ADJUSTMENT The OPA627/637 is laser-trimmed for low offset voltage and drift, so many circuits will not require external adjustment. Figure 3 shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system (such as in later amplification stages or in an A/D converter) because this could introduce excessive temperature drift. Generally, the offset drift will change by approximately 4V/C for 1mV of change in the offset voltage due to an offset adjustment (as shown on Figure 3).

amp contributes little additional noise. Below 1k, op amp noise dominates over the resistor noise, but compares favorably with precision bipolar op amps. CIRCUIT LAYOUT As with any high speed, wide bandwidth circuit, careful layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitanceespecially at the input pins and feedback circuitry. The case (TO-99 metal package only) is internally connected to the negative power supply as it is with most common op amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages has no internal connection. Power supply connections should be bypassed with good high frequency capacitors positioned close to the op amp pins. In most cases 0.1F ceramic capacitors are adequate. The OPA627/637 is capable of high output current (in excess of 45mA). Applications with low impedance loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger bypass capacitors such as 1F solid tantalum capacitors may improve dynamic performance in these applications.

C2

C1 +

R2

OPA637 C1 = CIN + CSTRAY C2 = R1 C1 R2

R1

FIGURE 2. Circuits with Noise Gain Equal to or Greater than Five May Use the OPA637. NOISE PERFORMANCE Some bipolar op amps may provide lower voltage noise performance, but both voltage noise and bias current noise contribute to the total noise of a system. The OPA627/637 is unique in providing very low voltage noise and very low current noise. This provides optimum noise performance over a wide range of sources, including reactive source impedances. This can be seen in the performance curve showing the noise of a source resistor combined with the noise of an OPA627. Above a 2k source resistance, the op

+VS 100k 7 1 2 3 + 4 VS 5 6 OPA627/637 10mV Typical Trim Range 10k to 1M Potentiometer (100k preferred)

FIGURE 3. Optional Offset Voltage Trim Circuit.

Non-inverting

Buffer

2 3

2 6 Out In 3

6 OPA627

Out

In

OPA627

Inverting In 2 3 OPA627

TO-99 Bottom View

3 Out 2

4 5 6 7 1 8 No Internal Connection

Board Layout for Input Guarding: Guard top and bottom of board. Alternateuse Teflon standoff for sensitive input pins. Teflon E.I. du Pont de Nemours & Co.

To Guard Drive

FIGURE 4. Connection of Input Guard for Lowest IB.

OPA627, 637

INPUT BIAS CURRENT Difet fabrication of the OPA627/637 provides very low input bias current. Since the gate current of a FET doubles approximately every 10C, to achieve lowest input bias current, the die temperature should be kept as low as possible. The high speed and therefore higher quiescent current of the OPA627/637 can lead to higher chip temperature. A simple press-on heat sink such as the Burr-Brown model 807HS (TO-99 metal package) can reduce chip temperature by approximately 15C, lowering the IB to one-third its warmed-up value. The 807HS heat sink can also reduce lowfrequency voltage noise caused by air currents and thermoelectric effects. See the data sheet on the 807HS for details. Temperature rise in the plastic DIP and SOIC packages can be minimized by soldering the device to the circuit board. Wide copper traces will also help dissipate heat. The OPA627/637 may also be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using 5V power supplies reduces power dissipation to one-third of that at 15V. This reduces the IB of TO99 metal package devices to approximately one-fourth the value at 15V. Leakage currents between printed circuit board traces can easily exceed the input bias current of the OPA627/637. A circuit board guard pattern (Figure 4) reduces leakage effects. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage current will flow harmlessly to the lowimpedance node. The case (TO-99 metal package only) is internally connected to VS. Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and circuit boards may be removed with cleaning solvents and deionized water. Each rinsing operation should be followed by a 30-minute bake at 85C. Many FET-input op amps exhibit large changes in input bias current with changes in input voltage. Input stage cascode circuitry makes the input bias current of the OPA627/637 virtually constant with wide common-mode voltage changes. This is ideal for accurate high inputimpedance buffer applications. PHASE-REVERSAL PROTECTION The OPA627/637 has internal phase-reversal protection. Many FET-input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This is most often encountered in non-inverting circuits when the input is driven below 12V, causing the output to reverse into the positive rail. The input circuitry of the OPA627/637 does not induce phase reversal with excessive commonmode voltage, so the output limits into the appropriate rail. OUTPUT OVERLOAD When the inputs to the OPA627/637 are overdriven, the output voltage of the OPA627/637 smoothly limits at approximately 2.5V from the positive and negative power supplies. If driven to the negative swing limit, recovery

takes approximately 500ns. When the output is driven into the positive limit, recovery takes approximately 6s. Output recovery of the OPA627 can be improved using the output clamp circuit shown in Figure 5. Diodes at the inverting input prevent degradation of input bias current.

+VS

(2) HP 5082-2811

5k

ZD1 1k 5k RF VI RI + OPA627 VS

Diode Bridge BB: PWS740-3

ZD1 : 10V IN961

VO Clamps output at VO = 11.5V

FIGURE 5. Clamp Circuit for Improved Overload Recovery. CAPACITIVE LOADS As with any high-speed op amp, best dynamic performance can be achieved by minimizing the capacitive load. Since a load capacitance presents a decreasing impedance at higher frequency, a load capacitance which is easily driven by a slow op amp can cause a high-speed op amp to perform poorly. See the typical curves showing settling times as a function of capacitive load. The lower bandwidth of the OPA627 makes it the better choice for driving large capacitive loads. Figure 6 shows a circuit for driving very large load capacitance. This circuits two-pole response can also be used to sharply limit system bandwidth. This is often useful in reducing the noise of systems which do not require the full bandwidth of the OPA627.

RF 1k 200pF CF + G = 1+ RF R1 OPA627 R1 RO 20 G = +1 BW 1MHz

CL 5nF

Optional Gain Gain > 1

For Approximate Butterworth Response: 2 RO CL RF >> RO CF = RF f3dB = 1 2 RF RO CF CL

FIGURE 6. Driving Large Capacitive Loads.

OPA627, 637

10

INPUT PROTECTION The inputs of the OPA627/637 are protected for voltages between +VS + 2V and VS 2V. If the input voltage can exceed these limits, the amplifier should be protected. The diode clamps shown in Figure 7a will prevent the input voltage from exceeding one forward diode voltage drop beyond the power supplieswell within the safe limits. If the input source can deliver current in excess of the maximum forward current of the protection diodes, use a series resistor, RS, to limit the current. Be aware that adding resistance to the input will increase noise. The 4nV/Hz theoretical thermal noise of a 1k resistor will add to the 4.5nV/Hz noise of the OPA627/637 (by the square-root of the sum of the squares), producing a total noise of 6nV/Hz. Resistors below 100 add negligible noise. Leakage current in the protection diodes can increase the total input bias current of the circuit. The specified maximum leakage current for commonly used diodes such as the 1N4148 is approximately 25nAmore than a thousand times larger than the input bias current of the OPA627/637. Leakage current of these diodes is typically much lower and may be adequate in many applications. Light falling on the junction of the protection diodes can dramatically increase leakage current, so common glass-packaged diodes should be shielded from ambient light. Very low leakage can be achieved by using a diode-connected FET as shown. The 2N4117A is specified at 1pA and its metal case shields the junction from light.

Sometimes input protection is required on I/V converters of inverting amplifiers (Figure 7b). Although in normal operation, the voltage at the summing junction will be near zero (equal to the offset voltage of the amplifier), large input transients may cause this node to exceed 2V beyond the power supplies. In this case, the summing junction should be protected with diode clamps connected to ground. Even with the low voltage present at the summing junction, common signal diodes may have excessive leakage current. Since the reverse voltage on these diodes is clamped, a diode-connected signal transistor can be used as an inexpensive low leakage diode (Figure 7b).

+VS D + D Optional RS VS (a) OPA627 D: IN4148 25nA Leakage 2N4117A 1pA Leakage Siliconix = VO

IIN VO D D + OPA627 D: 2N3904 = (b) NC

FIGURE 7. Input Protection Circuits.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

(A)

(B)

FPO

When used as a unity-gain buffer, large common-mode input voltage steps produce transient variations in input-stage currents. This causes the rising edge to be slower and falling edges to be faster than nominal slew rates observed in higher-gain circuits.

+ OPA627

G=1

FIGURE 8. OPA627 Dynamic Performance, G = +1.

11

OPA627, 637

LARGE SIGNAL RESPONSE

+10 VOUT (V) VOUT (V)

+10

(C)

(D)

10

10

6pF(1)
When driven with a very fast input step (left), common-mode transients cause a slight variation in input stage currents which will reduce output slew rate. If the input step slew rate is reduced (right), output slew rate will increase slightly. NOTE: (1) Optimum value will depend on circuit board layout and stray capacitance at the inverting input.

2k 2k + OPA627 G = 1 VOUT

FIGURE 9. OPA627 Dynamic Performance, G = 1.

OPA637 LARGE SIGNAL RESPONSE

OPA637 SMALL SIGNAL RESPONSE

+10 VOUT (mV) VOUT (V)

+100

(E)

(F)

FPO
100

10

4pF(1)

2k + 500
NOTE: (1) Optimum value will depend on circuit board layout and capacitance at inverting input.

G=5 OPA637 VOUT

FIGURE 10. OPA637 Dynamic Response, G = 5.

OPA627, 637

12

RI

Error Out 2k CF
OPA627 RI , R 1 CF Error Band (0.01%) 2k 6pF 0.5mV OPA637 500 4pF 0.2mV

HP50822835

2k +15V

High Quality Pulse Generator

RI

51

5V Out

NOTE: CF is selected for best settling time performance depending on test fixture layout. Once optimum value is determined, a fixed capacitor may be used.

15V

FIGURE 11. Settling Time and Slew Rate Test Circuit.

Gain = 100 CMRR 116dB Bandwidth 1MHz 2 25k INA105 Differential Amplifier 3 +In + RF 5k OPA637 Differential Voltage Gain = 1 + 2RF /RG 25k 1 25k 5

In

OPA637 RF 5k

Input Common-Mode Range = 5V RG 101 3pF

+ 25k

Output

FIGURE 12. High Speed Instrumentation Amplifier, Gain = 100.

Gain = 1000 CMRR 116dB Bandwidth 400kHz 2 10k INA106 Differential Amplifier 3 RF 5k OPA637 10k 1 100k 5

In

OPA637
RF 5k

Input Common-Mode Range = 10V RG 101 3pF

+ 100k

Output

+In

Differential Voltage Gain = (1 + 2RF /RG) 10

FIGURE 13. High Speed Instrumentation Amplifier, Gain = 1000.

This composite amplifier uses the OPA603 current-feedback op amp to provide extended bandwidth and slew rate at high closed-loop gain. The feedback loop is closed around the composite amp, preserving the precision input characteristics of the OPA627/637. Use separate power supply bypass capacitors for each op amp.

R2

A1 VI
+

*Minimize capacitance at this node.

VO

OPA603

R1 R3
*

RL 150 for 10V Out

GAIN (V/V) 100 1000

A1 OP AMP OPA627 OPA637

R1 ( ) 50.5(1) 49.9

R2 (k) 4.99 4.99

R3 ( ) 20 12

R4 (k ) 1 1

3dB (MHz) 15 11

SLEW RATE (V/s) 700 500

R4

NOTE: (1) Closest 1/2% value.

FIGURE 14. Composite Amplifier for Wide Bandwidth.

13

OPA627, 637

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION
Orderable Device OPA627AM OPA627AP OPA627APG4 OPA627AU OPA627AU/2K5 OPA627AU/2K5E4 OPA627AUE4 OPA627AUG4 OPA627BM OPA627BP OPA627BPG4 OPA627SM OPA637AM OPA637AM2 OPA637AP OPA637APG4 OPA637AU OPA637AU/2K5 Status
(1)

Package Type Package Pins Package Drawing Qty TO-99 PDIP PDIP SOIC SOIC SOIC SOIC SOIC TO-99 PDIP PDIP TO-99 TO-99 TO-99 PDIP PDIP SOIC SOIC LMC P P D D D D D LMC P P LMC LMC LMC P P D D 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 50 50 75 2500 20 50 50 75 2500 2500 75 75 1 50 50 20 20

Eco Plan
(2)

Lead/Ball Finish AU Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU AU Call TI Call TI AU AU Call TI Call TI Call TI CU NIPDAU CU NIPDAU

MSL Peak Temp

(3)

Op Temp (C)

Top-Side Markings
(4)

Samples

NRND ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE NRND ACTIVE ACTIVE NRND NRND OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE

Green (RoHS & no Sb/Br) TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

N / A for Pkg Type Call TI Call TI Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR N / A for Pkg Type Call TI Call TI N / A for Pkg Type N / A for Pkg Type Call TI Call TI Call TI Level-3-260C-168 HR Level-3-260C-168 HR -25 to 85 -25 to 85 -25 to 85 -25 to 85 -25 to 85 -25 to 85 -25 to 85

OPA627AM OPA627AP OPA627AP OPA 627AU OPA 627AU OPA 627AU OPA 627AU OPA 627AU OPA627BM OPA627BP OPA627BP OPA627SM OPA637AM

OPA637AP OPA637AP OPA 637AU OPA 637AU

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Orderable Device OPA637AU/2K5E4 OPA637AUE4 OPA637AUG4 OPA637BM OPA637BM1 OPA637BP OPA637BPG4 OPA637SM

Status
(1)

Package Type Package Pins Package Drawing Qty SOIC SOIC SOIC TO-99 TO-99 PDIP PDIP TO-99 D D D LMC LMC P P LMC 8 8 8 8 8 8 8 8 50 50 20 75 20 2500

Eco Plan
(2)

Lead/Ball Finish CU NIPDAU Call TI CU NIPDAU AU Call TI Call TI Call TI AU

MSL Peak Temp

(3)

Op Temp (C) -25 to 85 -25 to 85 -25 to 85

Top-Side Markings
(4)

Samples

ACTIVE OBSOLETE ACTIVE NRND OBSOLETE ACTIVE ACTIVE NRND

Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD TBD TBD Green (RoHS & no Sb/Br)

Level-3-260C-168 HR Call TI Level-3-260C-168 HR N / A for Pkg Type Call TI Call TI Call TI N / A for Pkg Type

OPA 637AU OPA 637AU OPA637BM

OPA637BP OPA637BP OPA637SM

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC D D 8 8

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 12.4 12.4 6.4 6.4

B0 (mm) 5.2 5.2

K0 (mm) 2.1 2.1

P1 (mm) 8.0 8.0

W Pin1 (mm) Quadrant 12.0 12.0 Q1 Q1

OPA627AU/2K5 OPA637AU/2K5

2500 2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

*All dimensions are nominal

Device OPA627AU/2K5 OPA637AU/2K5

Package Type SOIC SOIC

Package Drawing D D

Pins 8 8

SPQ 2500 2500

Length (mm) 367.0 367.0

Width (mm) 367.0 367.0

Height (mm) 35.0 35.0

Pack Materials-Page 2

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