PIC16F882/883/884/886/887

Pin Diagrams PIC16F884/887, 40-Pin PDIP

40-pin PDIP

RE3/MCLR/VPP RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/AN5 RE1/AN6 RE2/AN7 VDD VSS RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RD0 RD1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/T1G RB4/AN11 RB3/AN9/PGM/C12IN2RB2/AN8 RB1/AN10/C12IN3RB0/AN12/INT VDD VSS RD7/P1D RD6/P1C RD5/P1B RD4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3 RD2

PIC16F884/887

DS41291F-page 6

2009 Microchip Technology Inc.

PIC16F882/883/884/886/887
FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Registers 96 Bytes 3Fh 40h Indirect addr. (1) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 PR2 SSPADD SSPSTAT WPUB IOCB VRCON TXSTA SPBRG SPBRGH PWM1CON ECCPAS PSTRCON ADRESL ADCON1 General Purpose Registers 80 Bytes 6Fh 70h 7Fh Bank 0 accesses 70h-7Fh Bank 1 EFh F0h FFh accesses 70h-7Fh Bank 2 File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Registers 80 Bytes 16Fh 170h 17Fh accesses 70h-7Fh Bank 3 General Purpose Registers 16 Bytes Indirect addr. (1) TMR0 PCL STATUS FSR WDTCON PORTB CM1CON0 CM2CON0 CM2CON1 PCLATH INTCON EEDAT EEADR EEDATH EEADRH File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h General Purpose Registers 80 Bytes 1EFh 1F0h 1FFh General Purpose Registers 16 Bytes Indirect addr. (1) OPTION_REG PCL STATUS FSR SRCON TRISB BAUDCTL ANSEL ANSELH PCLATH INTCON EECON1 EECON2(1) Reserved Reserved File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h

Unimplemented data memory locations, read as 0. Note 1: Not a physical register. 2: PIC16F887 only.

2009 Microchip Technology Inc.

DS41291F-page 25

PIC16F882/883/884/886/887
TABLE 2-1:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA(3) PORTB(3) PORTC(3) PORTD(3,4) PORTE(3) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0
(2)

PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page

Name

Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counters (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C

xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx

37,217 73,217 37,217 29,217 37,217 39,217 48,217 53,217 57,217 59,217 37,217 31,217 34,217 35,217 76,217 76,217 79,217 81,217 82,217 183,217 181,217 126,217 126,217 124,217 161,217 153,217 158,217 126,217 126,218 125,218 99,218 104,218

Indirect Data Memory Address Pointer RA7 RB7 RC7 RD7 GIE OSFIF RA6 RB6 RC6 RD6 PEIE ADIF C2IF RA5 RB5 RC5 RD5 T0IE RCIF C1IF RA4 RB4 RC4 RD4 RA3 RB3 RC3 RD3 RE3 RA2 RB2 RC2 RD2 RE2(4) RA1 RB1 RC1 RD1 RE1(4) RA0 RB0 RC0 RD0 RE0(4) RBIF(1) TMR1IF CCP2IF

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- xxxx ---0 0000 0000 000x -000 0000 0000 00-0 xxxx xxxx xxxx xxxx

Write Buffer for upper 5 bits of Program Counter INTE TXIF EEIF RBIE SSPIF BCLIF T0IF CCP1IF ULPWUIF INTF TMR2IF

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

0000 0000 0000 0000

Timer2 Module Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000 xxxx xxxx

Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

0000 0000 xxxx xxxx xxxx xxxx

Capture/Compare/PWM Register 1 Low Byte (LSB) Capture/Compare/PWM Register 1 High Byte (MSB) P1M1 SPEN P1M0 RX9 DC1B1 SREN DC1B0 CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D

0000 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx

EUSART Transmit Data Register EUSART Receive Data Register Capture/Compare/PWM Register 2 Low Byte (LSB) Capture/Compare/PWM Register 2 High Byte (MSB) DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0

--00 0000 xxxx xxxx

A/D Result Register High Byte ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

0000 0000

Legend: Note 1: 2: 3: 4:

= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register. See Registers and 13-4 for more detail. Port pins with analog functions controlled by the ANSEL and ANSELH registers will read 0 immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). PIC16F884/PIC16F887 only.

DS41291F-page 26

2009 Microchip Technology Inc.

PIC16F882/883/884/886/887
TABLE 2-2:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(3) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 PR2 SSPADD(2) SSPMSK(2) SSPSTAT WPUB IOCB VRCON TXSTA SPBRG SPBRGH PWM1CON ECCPAS PSTRCON ADRESL ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 xxxx xxxx 1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx TRISA4 TRISB4 TRISC4 TRISD4 TRISA3 TRISB3 TRISC3 TRISD3 TRISE3 TRISA2 TRISB2 TRISC2 TRISD2 TRISA1 TRISB1 TRISC1 TRISD1 TRISA0 TRISB0 TRISC0 TRISD0 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---0 0000
(1)

PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page

Name

37,217 30,218 37,217 29,217 37,217 39,218 48,218 53,218 57,218 59,218 37,217 31,217 32,218 33,218 36,218 62,218 66,218 181,218 81,218 189,218 189,218 189,218 49,218 49,218 97,218 160,218 163,218 163,218 145,218 142,218 146,218 99,218 105,218

Program Counters (PC) Least Significant Byte IRP RP1 RP0 TO

Indirect Data Memory Address Pointer TRISA7 TRISB7 TRISC7 TRISD7 GIE OSFIE GCEN TRISA6 TRISB6 TRISC6 TRISD6 PEIE ADIE C2IE IRCF2 ACKSTAT TRISA5 TRISB5 TRISC5 TRISD5 T0IE RCIE C1IE ULPWUE IRCF1 ACKDT

TRISE2(3) TRISE1(3) TRISE0(3)

Write Buffer for the upper 5 bits of the Program Counter INTE TXIE EEIE SBOREN IRCF0 TUN4 ACKEN RBIE SSPIE BCLIE OSTS TUN3 RCEN T0IF CCP1IE ULPWUIE HTS TUN2 PEN INTF TMR2IE POR LTS TUN1 RSEN RBIF

0000 000x -000 0000 0000 00-0 --01 --qq -110 q000 ---0 0000 0000 0000 1111 1111 0000 0000

TMR1IE CCP2IE BOR SCS TUN0 SEN

Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register MSK7 SMP WPUB7 IOCB7 VREN CSRC BRG7 BRG15 PRSEN MSK6 CKE WPUB6 IOCB6 VROE TX9 BRG6 BRG14 PDC6 MSK5 D/A WPUB5 IOCB5 VRR TXEN BRG5 BRG13 PDC5 MSK4 P WPUB4 IOCB4 VRSS SYNC BRG4 BRG12 PDC4 MSK3 S WPUB3 IOCB3 VR3 SENDB BRG3 BRG11 PDC3 PSSAC1 STRD MSK2 R/W WPUB2 IOCB2 VR2 BRGH BRG2 BRG10 PDC2 PSSAC0 STRC MSK1 UA WPUB1 IOCB1 VR1 TRMT BRG1 BRG9 PDC1 PSSBD1 STRB MSK0 BF WPUB0 IOCB0 VR0 TX9D BRG0 BRG8 PDC0 PSSBD0 STRA

1111 1111 0000 0000 1111 1111 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 ---0 0001 xxxx xxxx

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 STRSYNC

A/D Result Register Low Byte ADFM VCFG1 VCFG0

0-00 ----

Legend: Note 1: 2: 3:

= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. Accessible only when SSPCON register bits SSPM<3:0> = 1001. PIC16F884/PIC16F887 only.

2009 Microchip Technology Inc.

DS41291F-page 27

PIC16F882/883/884/886/887
TABLE 2-3:
Addr Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h INDF TMR0 PCL STATUS FSR WDTCON PORTB CM1CON0 CM2CON0 CM2CON1 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counters (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx WDTPS3 RB4 C1POL C2POL C2RSEL WDTPS2 RB3 WDTPS1 RB2 C1R C2R WDTPS0 RB1 C1CH1 C2CH1 T1GSS SWDTEN RB0 C1CH0 C2CH0 C2SYNC RBIF(1) EEDAT0 EEADR0 EEDATH0 ---0 1000 xxxx xxxx 0000 -000 0000 -000 0000 --10 ---0 0000 0000 000x 0000 0000 0000 0000 --00 0000 37,217 73,217 37,217 29,217 37,217 225,218 48,217 88,218 89,218 91,219 37,217 31,217 112,219 112,219 112,219 112,219 Name

PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page

Indirect Data Memory Address Pointer RB7 C1ON C2ON MC1OUT GIE EEDAT7 EEADR7 RB6 C1OUT C2OUT MC2OUT PEIE EEDAT6 EEADR6 RB5 C1OE C2OE C1RSEL T0IE EEDAT5 EEADR5 EEDATH5

10Ah PCLATH 10Bh INTCON 10Ch EEDAT 10Dh EEADR 10Eh EEDATH 10Fh EEADRH Legend: Note 1: 2:

Write Buffer for the upper 5 bits of the Program Counter INTE EEDAT4 EEADR4 EEDATH4 RBIE EEDAT3 EEADR3 EEDATH3 T0IF EEDAT2 EEADR2 EEDATH2 INTF EEDAT1 EEADR1 EEDATH1

EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000

= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. PIC16F886/PIC16F887 only.

TABLE 2-4:
Addr Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh INDF Name

PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page

Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

xxxx xxxx 1111 1111 0000 0000

37,217 30,218 37,217 29,217 37,217 93,219 48,218 162,219 40,219 99,219 37,217 31,217 113,219 111,219

OPTION_REG PCL STATUS FSR SRCON TRISB BAUDCTL ANSEL ANSELH PCLATH INTCON EECON1 EECON2

Program Counters (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C

0001 1xxx xxxx xxxx

Indirect Data Memory Address Pointer SR1 TRISB7 ABDOVF ANS7(2) GIE EEPGD SR0 TRISB6 RCIDL ANS6(2) PEIE C1SEN TRISB5 ANS5(2) ANS13 T0IE C2REN TRISB4 SCKP ANS4 ANS12 PULSS TRISB3 BRG16 ANS3 ANS11 PULSR TRISB2 ANS2 ANS10 TRISB1 WUE ANS1 ANS9 FVREN TRISB0 ABDEN ANS0 ANS8 RBIF(1) RD

0000 00-0 1111 1111 01-0 0-00 1111 1111 --11 1111 ---0 0000 0000 000x x--- x000 ---- ----

Write Buffer for the upper 5 bits of the Program Counter INTE RBIE WRERR T0IF WREN INTF WR

EEPROM Control Register 2 (not a physical register)

Legend: Note 1: 2:

= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. PIC16F884/PIC16F887 only.

DS41291F-page 28

2009 Microchip Technology Inc.

PIC16F882/883/884/886/887
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: the arithmetic status of the ALU the Reset status the bank select bits for data memory (GPR and SFR) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see Section 15.0 Instruction Set Summary Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction.

REGISTER 2-1:
R/W-0 IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7

STATUS: STATUS REGISTER

R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC(1) R/W-x C(1) bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

bit 6-5

bit 4

bit 3

bit 2

bit 1

bit 0

Note 1:

2009 Microchip Technology Inc.

DS41291F-page 29

PIC16F882/883/884/886/887
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to 1. See Section 6.3 Timer1 Prescaler. The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: Timer0/WDT prescaler External INT interrupt Timer0 Weak pull-ups on PORTB

REGISTER 2-2:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7

OPTION_REG: OPTION REGISTER

R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128

bit 6

bit 5

bit 4

bit 3

bit 2-0

DS41291F-page 30

2009 Microchip Technology Inc.

PIC16F882/883/884/886/887
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register, shown in Register 2-3, is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external INT pin interrupts.

REGISTER 2-3:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7

INTCON: INTERRUPT CONTROL REGISTER

R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE(1) R/W-0 T0IF(2) R/W-0 INTF R/W-x RBIF bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt RBIE: PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTB change interrupt 0 = Disables the PORTB change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred (must be cleared in software) 0 = The INT external interrupt did not occur RBIF: PORTB Change Interrupt Flag bit 1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTB general purpose I/O pins have changed state IOCB register must also be enabled. T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit.

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Note 1: 2:

2009 Microchip Technology Inc.

DS41291F-page 31

PIC16F882/883/884/886/887
3.2 Additional Pin Functions
RA0 also has an Ultra Low-Power Wake-up option. The next three sections describe these functions.

3.2.1

ANSEL REGISTER

The ANSEL register (Register 3-3) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

REGISTER 3-3:
R/W-1 ANS7(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0

ANSEL: ANALOG SELECT REGISTER

R/W-1 ANS6(2) R/W-1 ANS5(2) R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Not implemented on PIC16F883/886.

Note 1:

2:

DS41291F-page 40

2009 Microchip Technology Inc.

PIC16F882/883/884/886/887
3.2.3.8 RA7/OSC1/CLKIN
Figure 3-8 shows the diagram for this pin. This pin is configurable to function as one of the following: a general purpose I/O a crystal/resonator connection a clock input

FIGURE 3-8:
Data Bus

BLOCK DIAGRAM OF RA7

Oscillator Circuit OSC1

D WR PORTA

VDD

CK Q I/O Pin D Q VSS INTOSC Mode

WR TRISA RD TRISA RD PORTA

CK Q

CLKIN

TABLE 3-1:
Name ADCON0 ANSEL CM1CON0 CM2CON0 CM2CON1 PCON OPTION_REG PORTA SSPCON TRISA Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Bit 7 ADCS1 ANS7 C1ON C2ON MC1OUT RBPU RA7 WCOL TRISA7 Bit 6 ADCS0 ANS6 C1OUT C2OUT MC2OUT INTEDG RA6 SSPOV TRISA6 Bit 5 CHS3 ANS5 C1OE C2OE C1RSEL ULPWUE T0CS RA5 SSPEN TRISA5 Bit 4 CHS2 ANS4 C1POL C2POL C2RSEL SBOREN T0SE RA4 CKP TRISA4 Bit 3 CHS1 ANS3 PSA RA3 SSPM3 TRISA3 Bit 2 CHS0 ANS2 C1R C2R PS2 RA2 SSPM2 TRISA2 Bit 1 GO/DONE ANS1 C1CH1 C2CH1 T1GSS POR PS1 RA1 SSPM1 TRISA1 Bit 0 ADON ANS0 C1CH0 C2CH0 C2SYNC BOR PS0 RA0 SSPM0 TRISA0 Value on POR, BOR 0000 0000 1111 1111 0000 -000 0000 -000 0000 --10 --01 --qq 1111 1111 xxxx xxxx 0000 0000 1111 1111 Value on all other Resets 0000 0000 1111 1111 0000 -000 0000 -000 0000 --10 --0u --uu 1111 1111 uuuu uuuu 0000 0000 1111 1111

x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.

DS41291F-page 46

2009 Microchip Technology Inc.

PIC16F882/883/884/886/887
3.3 PORTB and TRISB Registers
3.4.1 ANSELH REGISTER
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 3-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 3-3 shows how to initialize PORTB. Reading the PORTB register (Register 3-5) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISB register (Register 3-6) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read 0. Example 3-3 shows how to initialize PORTB. The ANSELH register (Register 3-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELH bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. The state of the ANSELH bits has no affect on digital output functions. A pin with TRIS clear and ANSELH set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

3.4.2

WEAK PULL-UPS

Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up (see Register 3-7). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the RBPU bit of the OPTION register.

3.4.3

INTERRUPT-ON-CHANGE

EXAMPLE 3-3:
BANKSEL CLRF BANKSEL MOVLW MOVWF

INITIALIZING PORTB

PORTB ; PORTB ;Init PORTB TRISB ; B11110000 ;Set RB<7:4> as inputs ;and RB<3:0> as outputs TRISB ;

All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin. Refer to Register 3-8. The interrupt-on-change feature is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the present value is compared with the old value latched on the last read of PORTB to determine which bits have changed or mismatched the old value. The mismatch outputs of the last read are ORd together to set the PORTB Change Interrupt flag bit (RBIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear the flag bit RBIF.

Note:

The ANSELH register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read 0.

3.4

Additional PORTB Pin Functions

PORTB pins RB<7:0> on the device family device have an interrupt-on-change option and a weak pull-up option. The following three sections describe these PORTB pin functions. Every PORTB pin on this device family has an interrupt-on-change option and a weak pull-up option.

A mismatch condition will continue to set flag bit RBIF. Reading or writing PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RBIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-Change mode. Changes on one pin may not be seen while servicing changes on another pin.

2009 Microchip Technology Inc.

DS41291F-page 47

PIC16F882/883/884/886/887
REGISTER 3-4:
U-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

ANSELH: ANALOG SELECT HIGH REGISTER

U-0 R/W-1 ANS13 R/W-1 ANS12 R/W-1 ANS11 R/W-1 ANS10 R/W-1 ANS9 R/W-1 ANS8 bit 0

Unimplemented: Read as 0 ANS<13:8>: Analog Select bits Analog select between analog or digital function on pins AN<13:8>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

Note 1:

REGISTER 3-5:
R/W-x RB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0

PORTB: PORTB REGISTER

R/W-x RB6 R/W-x RB5 R/W-x RB4 R/W-x RB3 R/W-x RB2 R/W-x RB1 R/W-x RB0 bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL

REGISTER 3-6:
R/W-1 TRISB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0

TRISB: PORTB TRI-STATE REGISTER

R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4 R/W-1 TRISB3 R/W-1 TRISB2 R/W-1 TRISB1 R/W-1 TRISB0 bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

TRISB<7:0>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output

DS41291F-page 48

2009 Microchip Technology Inc.

PIC16F882/883/884/886/887
REGISTER 3-7:
R/W-1 WPUB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4 R/W-1 WPUB3 R/W-1 WPUB2 R/W-1 WPUB1 R/W-1 WPUB0 bit 0

WPUB<7:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled 2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.

REGISTER 3-8:
R/W-0 IOCB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0

IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

R/W-0 IOCB6 R/W-0 IOCB5 R/W-0 IOCB4 R/W-0 IOCB3 R/W-0 IOCB2 R/W-0 IOCB1 R/W-0 IOCB0 bit 0

W = Writable bit 1 = Bit is set

U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown

IOCB<7:0>: Interrupt-on-Change PORTB Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled

2009 Microchip Technology Inc.

DS41291F-page 49

PIC16F882/883/884/886/887
TABLE 3-2:
Name ANSELH CCP1CON CM2CON1 IOCB INTCON OPTION_REG PORTB TRISB WPUB Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Bit 7 P1M1 IOCB7 GIE RBPU RB7 TRISB7 WPUB7 Bit 6 P1M0 IOCB6 PEIE INTEDG RB6 TRISB6 WPUB6 Bit 5 ANS13 DC1B1 IOCB5 T0IE T0CS RB5 TRISB5 WPUB5 Bit 4 ANS12 DC1B0 IOCB4 INTE T0SE RB4 TRISB4 WPUB4 Bit 3 ANS11 IOCB3 RBIE PSA RB3 TRISB3 WPUB3 Bit 2 ANS10 IOCB2 T0IF PS2 RB2 TRISB2 WPUB2 Bit 1 ANS9 T1GSS IOCB1 INTF PS1 RB1 TRISB1 WPUB1 Bit 0 ANS8 Value on POR, BOR Value on all other Resets

--11 1111 --11 1111

CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 C2SYNC 0000 --10 0000 --10 IOCB0 RBIF PS0 RB0 TRISB0 WPUB0 0000 0000 0000 0000 0000 000x 0000 000x 1111 1111 1111 1111 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111

MC1OUT MC2OUT C1RSEL C2RSEL

x = unknown, u = unchanged, = unimplemented read as 0. Shaded cells are not used by PORTB.

DS41291F-page 52

2009 Microchip Technology Inc.