Code No: R5310404 1

III B.Tech I Semester(R05) Supplementary Examinations, May 2009

DIGITAL IC APPLICATIONS
(Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain how to estimate sinking current for low output and sourcing current for high
output of CMOS gate.
(b) Design a CMOS transistor circuit for the following functional behavior.

f (x) = (b + c)(a + c)

Also draw the relevant circuit diagram. [8+8]

2. (a) Compare CMOS, TTL and ECL with reference to logic levels, DC Noise margin, propa-
gation delay and fan-out.
(b) List out different categories of characteristics in a TTL data sheet? Discuss electrical and
switching characteristics of 74LS00. [6+10]

3. (a) Explain with an example the syntax and the function of the following VHDL statements.
i. Process Statement
ii. If, else and elseif statements
(b) Explain Variable assignment and signal assignment in VHDL with suitable examples.[8+8]

4. (a) Explain data-flow design elements of VHDL.

(b) Design the logic circuit and write a data-flow style VHDL program for the following
function. [8+8]

F (X) = ΣA,B,C,D (1, 4, 5, 7, 12, 14, 15) + d (3, 11)

5. Explain the principle of carry look ahead Adder. Using this principle design a 6-bit carry look
ahead adder. Provide the logic diagram. Write the data flow VHDL program for the same. [16]

6. A simple floating-point encoder converts 16-bit fixed-point data using four high order bits
beginning with MSB. Design the logic circuit and write VHDL data-flow program. [16]

7. (a) Design a module-8 binary counter and decoder with glitch-free outputs. Explain the
operation.
(b) Design a module-60 counter using 74×163 ICs. [8+8]

8. (a) Explain how a 4x4 binary multiplier can be designed using 256×8 ROM.
(b) Discuss how PROM, EPROM and EEPROM technologies differ from each other. [8+8]

?????
Code No: R5310404 2
III B.Tech I Semester(R05) Supplementary Examinations, May 2009
DIGITAL IC APPLICATIONS
(Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Design CMOS transistor circuit for 3-input AND gate? With the help of function table
explain the operation of the circuit diagram
(b) Draw the CMOS circuit diagram of tri-state buffer. Explain the circuit with the help of
logic diagram and function table. [8+8]

2. (a) Draw the circuit diagram of two-input 10K ECL OR gate and explain its operation.
(b) List out different categories of characteristics in a TTL data sheet. Discuss electrical and
switching characteristics of 74LS00. [8+8]

3. (a) Explain Variable assignment and signal assignment in VHDL with suitable examples?
(b) What is the use of wait statement? Show the effect of wait statement to produce a delay
of 20ns using VHDL program. [8+8]

4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural VHDL
program for the same. [16]

5. A mechanical disk rotates in a circle in different positions. Two successive positions differ with
an angle of 15o . Provide an encoding mechanism for every position of the disk. The disk in
the mechanical system outputs this encoded information to detect the exact position. Design
a decoder with an enable input to identify the position of the disk. [16]

6. (a) Design a priority encoder with 8 inputs. Write a VHDL program for the same in structural
style.
(b) Design a 4x4 combinational multiplier and the write the necessary VHDL program in data
flow model. [8+8]

7. (a) Design an 8-bit parallel-in and serial-out shift register, Explain the operation of the above
shift register with the help of timing waveforms.
(b) Write a VHDL program for the above shift register. [10+6]

8. (a) Explain the functional behavior of Static RAM cell? Show the internal structure of 8×4
static RAM and explain.
(b) Explain the internal structure of 64K×1 DRAM. With the help of timing waveforms
discuss DRAM access. [8+8]

?????
Code No: R5310404 3
III B.Tech I Semester(R05) Supplementary Examinations, May 2009
DIGITAL IC APPLICATIONS
(Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS
circuits? Mention the typical values of a CMOS NAND gate.
(b) Design a CMOS 4-input AND-OR-INVERT gate. Draw the logic diagram and function
table. [8+8]

2. (a) Mention the DC noise margin levels of ECL 10K family.

(b) A single pull-up resistor to +5V is used to provide a constant-1 logic source to 15 different
74LS00 inputs. What is the maximum value of this resistor? How much high state DC
noise margin can be provided in this case? [6+10]

3. (a) Write a VHDL Entity and Architecture for a 3-bit synchronous counter using Flip-Flops.
(b) Explain the use of Packages. Give the syntax and structure of a package in VHDL. [8+8]

4. (a) Explain structural design elements of VHDL.

(b) Design the logic circuit and write a data-flow style VHDL program for the following
function. [8+8]

F (R) = ΠA,B,C,D (1, 4, 5, 7, 9, 13, 15)

5. (a) Design a 32 to 1 multiplexer using four 74×151 multiplexers and 74X139 decoder.
(b) Realize the following expression using 74×151 IC [8+8]

f (Y ) = AB + BC + AC

6. A 16-bit barrel shifter is a combinational logic circuit with 16-data inputs, 16-data outputs and
4-control inputs. The input word is rotated by a number of bit positions specified by control
bits. Write a VHDL program using data flow style?
[16]

7. (a) Design a module-8 binary counter and decoder with glitch-free outputs. Explain the
operation.
(b) Design a module-60 counter using 74×163 ICs. [8+8]

8. (a) Design an 8x4 diode ROM using 74X138 for the following data starting from the first
location.
1, 4, 9, B, A, 0, F, C
(b) Draw the internal structure of synchronous SRAM and explain its operation? [8+8]

?????
Code No: R5310404 4
III B.Tech I Semester(R05) Supplementary Examinations, May 2009
DIGITAL IC APPLICATIONS
(Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain how to estimate sinking current for low output and sourcing current for high
output of CMOS gate.
(b) Analyze the fall time of CMOS inverter output with RL = 100Ω, VL = 2.5V and CL =
10P F . Assume VL as stable state voltage. [8+8]
2. (a) Design a TTL three-state NAND gate and explain the operation with the help of function
table.
(b) Explain the following terms with reference to TTL gate.
i. Voltage levels for logic ‘1’ & logic ‘0’
ii. DC Noise margin
iii. Low-state unit load
iv. High-state fan-out [8+8]
3. (a) Explain with an example the syntax and the function of the following VHDL statements.
i. Process Statement
ii. Case Statement
(b) Explain Implicit and Explicit visibility of a Library in VHDL? [8+8]
4. (a) Write a process based VHDL program for the prime-number detector of 4-bit input and
explain the flow using logic circuit.
(b) Explain data-flow design elements of VHDL. [10+6]
5. (a) Write a VHDL program for 74×245?
(b) Give the logic diagram of 74×139. Explain with the help of truth table. Using this device
design a 3 to 8 decoder and provide the truth table. [8+8]
6. A simple floating-point encoder converts 16-bit fixed-point data using four high order bits
beginning with MSB. Design the logic circuit and write VHDL data-flow program. [16]
7. (a) Design a conversion circuit to convert a D flip-flop to J-K flip-flop. Write data-flow style
VHDL program.
(b) Design a 4-bit binary synchronous counter using 74x74? Write VHDL program for this
logic using data flow style. [8+8]
8. (a) How many ROM bits are required to build a 16-bit adder/subtractor with mode con-
trol, carry input, carry output and two’s complement overflow output? Show the block
schematic with all inputs and outputs?
(b) Explain the functional behavior of Static RAM cell. Show the internal structure of 8x4
static RAM and explain. [8+8]

?????