Dynamic Voltage (IR) Drop Analysis and Design Closure: Issues and Challenges

Nithin S K, Gowrysankar Shanmugam, Sreeram Chandrasekar Texas Instruments India E-mail: {nithin,gowrysankar,sreeram}@ti.com
AbstractDynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of the design, and hence it is vector dependent. In this paper we have highlighted the pitfalls in the common design closure methodology that addresses static IR drop well, but often fails to bound the impact of dynamic voltage drops robustly. Factors that can aect the accuracy of dynamic IR analysis and the related metrics for design closure are discussed. A structured approach to planning the power distribution and grid for power managed designs is then presented, with an emphasis to cover realistic application scenarios, and how it can be done early in the design cycle. Care-about and solutions to avoid and x the Dynamic voltage drop issues are also presented. Results are from industrial designs in 45nm process are presented related to the said topics. KeywordsDynamic voltage Drop, DvD, Dynamic IR, Peak power, Power switch, VCD, Power gate, SDF. I. Introduction Designing an optimal power grid which is robust across multiple operating scenarios of a chip continues to be a major challenge.[1][2][3] The problem has magnied with technology shrinking allowing more performance to be packed in a smaller area, from one node to another [4]. The power distribution on a chip needs to ensure circuit robustness catering to not only to the average power / current requirements, but also needs to ensure timing or reliability is not aected due to Dynamic IR drop, caused by localized power demand and switching patterns. [5] Further, amongst todays devices power management techniques like power gating and switch power supplies are the norms [6][7][8]. In the case of switched power supplies, typically, power switch cells are uniformly distributed across the standard cell logic (logic gates) area of the oorplan. There may be further sub-divisions in the switched power grid in the form of power domains, depending on the granularity of power gating [10]. These power switches add an additional dimension to the power distribution problem as they often limit the response of the power grid to dynamic power or current needs. While the power distribution robustness can be improved easily by increasing the number of power switches, it has an impact on the omode leakage (Iddq) and hence battery life in handheld applications. So clearly, the requirement is also to minimize the number of switches used as well as minimize the signal routing resources utilized on the power grid. This paper discusses the issues related to design closure and signo (timing, IR Drop, EM, reliability etc.) comprehending Dynamic IR drop eects realistically. On one hand, the factors that introduce pessimism in Dynamic voltage drop analysis have to be removed, while on the other we must ensure the methodology ensures robust coverage of various silicon conditions and design operating scenarios. We then discuss power distribution and power grid planning methodology, and highlight the various aspects that need to be taken care of, from the early stages of design implementation. We also demonstrate some of the systematic power grid enhancements like robust automated switch placement and switched supply resistance minimization through DRC-aware power metal ll. All the discussions and results are based on production implementations of low power application processors for mobile and hand-held devices. The designs include high frequency CPU cores, multimedia subsystems (like imaging and video). The numbers quoted are from the analysis and/or simulation. The structure of the paper is as follows. In section II , the commonly followed Dynamic IR methodology and its pitfalls are highlighted with design results. In section III the issues related to analysis accuracy and signo methodology are discussed. Section IV then elaborates how we went about planning the power distribution and the techniques used to ensure silicon robustness in the tolerant to Dynamic IR drop. II. Common Design Closure Methodology and Its Pitfalls A. Overview Of Static Vs Dynamic IR Drop Static IR drop is average voltage drop for the design.[12][13], whereas Dynamic IR drop depends on the switching activity of the logic[11], hence is vector dependent. Dynamic IR drop depends on the switching time of the logic, and is less dependent on the a clock period. This nature is illustrated in Fig 1. The Average current depends totally on the time period, where as the dynamic IR drop depends on the instantanious current which is higher while the cell is switching. Static IR drop was good for signo analysis in older technology nodes where sucient natural decoupling capacitance from the power network and non-switching logic were available. Where as Dynamic IR drop Evaluates the IR drop caused when large amounts of circuitry switch simultaneously, causing peak current demand[1][14]. This current demand could be highly localized and could be brief within a single clock cycle (a few hundred ps), and

Fig. 1. Average Current Over A Window

Fig. 2. Eect Of Low Switch Density In Notch

could result in an IR drop that causes additional setup or hold-time violations. Typically, high IR drop impact on clock networks causes hold-time violations, while IR drop on data path signal nets causes setup-time violations. B. Deciencies Found By Dynamic Analysis On A Good Power Grid A typical power grid and power switches (count and distribution) are designed for average power or in other words they are designed to meet static IR drop targets and not for Dynamic IR drop. In the initial stage of the design, the grid robustness is checked only with the Static IR drop result. This is because of late availability of use case scenarios (Voltage change dump (VCD) les). For the example, the switch and metal grid densities in the notches region can satisfy the static IR drop criteria, because the average power density in this region is not signicant. But when a particular application is run, notch area could have higher power density because of localized switching in that area and the switches combined with metal grid (Switched supply is distributed to cells by lower layers like MET2 and MET3) may not be enough to support the current density in the notch area. Because of which there can be very high dynamic IR drop. Refer to Notch area as shown in Fig. 2, Here due to less number of switch cells combined with not so robust power grid is the main cause of high dynamic IR drop. As described by the gure, Switch Voltage drop and MET3 voltage drop are the dominant factors in the overall voltage drop. A similar analogy on the power density can be extended to larger region. Refer to Fig. 3, With the original MET3 grid, static IR drops was within the budget. However, to meet the dynamic IR drop goals, an increase of the MET3 (MET3 Grid is Vertical) grid density by 3 times, was needed. The drop across the MET3 and related vias reduced by 50%, after the improvement. This is another example of a robustness issue which was missed in static analysis. As discussed earlier, the number of power switches is cal-

Fig. 3. Eect Of MET3 Grid On Dyanmic IR drop

Fig. 4. Closer View Of Dynamic IR Drop

culated based on the static IR drop requirement. For our design, with the switch density that is calculated as per average power, and with calculated optimal cell density and optimal decap density, our expectation is to have a

good dynamic voltage drop. Static IR drop and vectorless dynamic results runs were within the budgets. Vectorless dynamic IR drop was 70mV, but vector based dynamic IR drop was 153 mV, which is beyond the budget. The main cause for such high voltage drop was localized switching. The high dynamic IR drop region has very high power density and hence this region has high current requirement, which is not fullled by the existing power switch density in that region, and as a result there is high Dynamic voltage drop. The High IR drop region has reasonably good decap density and has low utilization as shown in the Fig. 4. This indicates that the aected region is not really a case of a poorly designed power grid, but more of an exceptionally high power density, due to the design architecture combined with the placement of cells. In any case, the power grid has to eventually be able to support the designs power demands in that region, which requires a dierent approach as will be discussed later. III. Accuracy Of Analysis A. Comprehending Delays In Gate Simulation There are several factors that aect the accuracy of the dynamic IR analysis, and how closely it represents the nature of actual Silicon behavior. One of the key requisites is to generate a realistic VCD (a le format that captures the switching information) which accounts for the real cell and interconnect delays (typically done by annotating an SDF in the gate simulation). Such a simulation captures the realistic spread of switching activity in the design. The other common approach is to use a VCD from a zero-delay simulation, along with the timing windows from STA analysis, which often results in non-realistic Dynamic IR drop that can be pessimistic or optimistic. Refer to Fig. 5 (SDF Annotated VCD) and Fig. 6 (Without SDF annotated VCD). It shows a drop close to 175 mV with a VCD generated with SDF, versus Vs 141 mV from analysis using a VCD without SDF annotation. In this case, 175mV is the more realistic result for the given application. Also, the analysis needs to be done for more than 1 cycle because this would expose more weak spots and allow sucient pre-simulation time for the decap eects to be comprehended more accurately.
Fig. 6. Dynamic IR Drop: Without SDF Annotated VCD Fig. 5. Dynamic IR Drop: SDF Annotated VCD

B. Comprehending Realistic Glitch Propagation Glitches arising out of combinational logic switching can cause a large amount of instantaneous switching. It is important to factor the eect of such switching, with consideration to which of these glitches would die down or propagate, considering cell and interconnect delays under realistic conditions. If the glitches are very narrow, the chances of them getting ltered out by the inertial delay of the path stages (cell + interconnect) is very high. We ltered out glitches much smaller than the stage delay, and let those comparable to (or larger than) the stage delay propagate. The glitches in between were kept as x. We found that the pessimism in the dynamic voltage drop reduced by 20% by using this approach. C. Choice Of Technology Specs For Signo Often, worst case conditions are chosen for timing, electrical and reliability checks to ensure robust silicon operation. However, it is also critical to strike a balance between picking bounding conditions and being overly pessimistic. In an eort to get results closer to realistic silicon conditions, and to detect potentially silicon fails, we selectively evaluated designs under both worst case and non-worstcase conditions. For example if we compare the eect of the worst via resistance spec against the nominal via specs, the drop across vias alone reduce by 50%, as show in Fig. 7. With Via resistance and Metal resistances typically being

Fig. 7. Via Drop: Worst corner Vs Nom Corner

uncorrelated, it is a pessimistic assumption to consider that all vias and metal layers would be in the worst case corner. With sucient characterization data, we can apply a less pessimistic analysis condition for dynamic IR analysis. D. Voltage Annotated Timing Closure Timing impact has been analyzed with dynamic voltage annotation in the STA tool. The voltage annotated timing violations on one particular design before any xes can be seen in Table I. It was ensured that the frequency goals were met by xing these violations, either addressing the voltage drop itself, or at least by improving timing slack on those paths. Design IP1 IP2 IP3 IP4 Worst Slack (ps) -251 -347 -30 -37 Failing End Points 370 95 8 2

Fig. 8. Average Power Vs Peak Average Power

TABLE I Dynamic IR Drop Annotated Timing

IV. Methodology For power Grid Design For Robust Dynamic IR In this section, the care-about in planning the power distribution (grid, switches) for power managed designs are discussed. Knowledge of the design operating scenarios and architecture play a key role in ensuring the robustness across scenarios. Some techniques to improve power grid robustness through simple physical implementation schemes such as power metal ll and decap planning are also touched upon. A. Choosing The Right Average Power The choice of the average power value for which the power distribution is designed for is critical. It is common practice to design for the average power seen in the use case that consumes the highest power. However, there can be a sub-window within the application window, for which the average power is much higher than that of the entire use case time. It is obvious that the grid has to support this

higher average power during the high-power sub-window, else the device would not function as per design. An example of this is shown in Fig. 8, where the application average power is about 214 mW where as the average power over a sub-window is 367mW. This sub window extends over a few hundred clock cycles. In this case, the grid has to support 367 mW of average power and not 214mW. Hence, choosing the right average power for designing the grid would help the design scale up to not just dynamic voltage drop issues, but even to sustain the average cases more robustly. B. Early Dynamic IR Analysis One of the diculties in evaluating the dynamic IR impact on SOCs or complex designs (IPs) is to get vectors for sucient scenarios, and to get them in time to detect issues before the design tapes out. Our Early Analysis ow addresses this issue. In this ow, the switching activity of a sub IP is integrated at the top level, and switching activity at the top level is created, for use in dynamic IR analysis. Using this ow, we were able to identify certain architectural hot-spots for dynamic IR drop, like cases of crossbar interconnects interacting with shared memories having very high power density. The results obtained from this ow

Fig. 11. Region Based Switch Density

Fig. 9. Dynamic IR Drop Prole Using Early Analysis Flow

list of IPs/Modules which consume more power than the rest of the design. This means that these IPs/Modules need higher current. Which implies that there is a need for more switches in these modules. Typically standard cells of sub IPs/Modules are placed within close proximity. Hence planning a higher switch density in this area will make the area better in terms of dynamic IR drop. Covering more scenarios (More VCD) will excite dierent parts of design and hence will show any weakness in the power network. Refer to Fig. 11 for region based switch density. Covering more scenario will also show the area where the voltage drop is low (cool area), the regions which do not have high IR drop region. In the cool area, switch density can be reduced by removing some of the switches. This will help in reducing the leakage power of the design in standby mode. D. Switch Placement In Floorplan Channels / Boundaries Channels (between macro cells) and oorplan edges or boundaries are often weak spots in a designs power distribution scheme. It was highlighted earlier how a channel with power switches placed a bit far from the high switching activity logic gave rise to a dynamic IR hot spot (Refer to Fig. 2). To address such issues, we have implemented an automated bounding scheme where all the standard cell logic area in the oorplan is surrounded by power switches at the boundaries. Refer to Fig. 12. The switch cell bounding is done over the corners of channel, making it more robust to voltage drop variations. E. Using Design Knowledge To Reduce Dynamic IR In one of our design, the architecture of the design was such that, a group of registers banks switching simultaneously, and these banks would switch in every cycle. Also these groups of register banks and associated cells are physically placed close to each another. The Clock to some of the ops were skewed so as to stagger the switching which will reduce the switching activity (These timing paths had high positive slacks). This will reduce the peak current requirement and hence reduce the peak drop. Refer to

Fig. 10. Dynamic IR Drop Prole From Full Subsystem Simulation

were found to correlate well with the analysis done with the complete simulation done at the top level of the subsystem itself. Both cases are shown in Fig. 9 and Fig. 10, where we can notice both the magnitude and the prole of the dynamic IR results match closely (The rst map is based on the sub-design switching ported to the top level while the second map is with switching information from full design simulation ). This technique can be extended to SOCs, to do vector based dynamic IR drop analysis accurately. C. Power Switch Density And Placement For designs with power switches, in most cases, high voltage drop is because of lesser number of switches than needed for localized power density in certain regions. From common power analysis methods, it is possible to get a

Fig. 12. Switch Density In Notches

Fig. 14. Metal density without Vs with Metal ll Fig. 13. Staggering Switching Activity To Reduce Dynamic IR Drop

the metal ll is done on 2 layers and 2% improvement when metal ll was done on all layers. Fig. 13, the switching activity last for around 200ps, where as the clock period is higher, Thus we have used the design knowledge to reduce switching activity. F. Power/Ground Metal Fill Experiment Without Metal Fill Metal Fill on 2 Layers Metal Fill on All layers %Drop 9.3 8.4 7.3 % Improvement 0.9 2 G. Other Methods To Reduce Dynamic IR Drop Load and Slew violation will not only cause crosstalk but also cause high power. This is because, there will be high current requirement for higher loads/slews. Hence xing load/slew violation will help in reducing dynamic voltage drop. Another method to reduce Dynamic IR drop is haloing of Clock tree cells, and adding decaps near these cells. This will help in reducing the voltage drop in clock tree cells due to switching. V. Conclusion We have highlighted the common issues faced in the design closure of power managed designs . Key accuracy and signo methodology issues were addressed and improvements made in replicating actual device operating conditions in analysis. A comprehensive set of techniques adopted in our designs to create a robust power grid, and to ensure device timing robustness considering dynamic voltage drop, was presented. This covered the choice of the correct power values, power switch planning, using design knowledge and power routing techniques.

TABLE II Using Power/Ground Metal Fill to improve power grid robustness

Another technique we followed was Power/Ground Metal ll. After the design is frozen, nal step is to add metal ll in the areas where the free metal tracks are available. These inserted metal straps are connected power or ground. Refer to Fig. 14. By doing so, the power and ground grid becomes stronger and hence would help in reducing voltage drop. Refer to Table.1. We have seen that as much as 0.9% (0.9% of supply voltage) improvement in voltage drop when

A. Future Work The main area of our ongoing work is with respect to comprehending the impact of dynamic IR on timing behavior of the device - path level, and timing yield. Another area of study is on the coverage of multiple scenarios without having to simulate each of them (which is impossible, and hence vector based analysis is not complete today). Further, dynamic IR impact on test modes are presently being studied. Eorts are on to correlate analysis and silicon measurements to establish a close link between analysis and real device operation. References
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