Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Electronics Complex CMOS digital circuits

Prof. M arta Rencz, Gergely Nagy
BME DED

October 25, 2011

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

CMOS logic
Pull-up network:
p-type transistors short circuit, if f (X ) = 1 open circuit, if f (X ) = 0

Pull-down network:
n-type transistors short circuit, if f (X ) = 0 open circuit, if f (X ) = 1

For example: NOR gate

y = f (X )

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Complex gates
Complex gates can be realized at transistor level which is advantageous as the gate delay is smaller for one complex gate than for the series connection of several simple gates realizing the same function. Usually the number of inputs is limited to 4 (the number of transistors in series between the ground and supply is limited). The realized logic function can be any combination of the AND and NOR functions and there is always an inversion at the output: y = (A + B )C y = AB + CD y = (A + B )CD

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Complex gate design an example I.

Lets design the complex gate realizing the logic function y = (A + B )C First the pull-down network (PDN) is created. The OR function is realized by two n-type FETs connected in parallel. The AND function is realized by two n-type FETs connected in series.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Complex gate design an example II.

Next the pull-up network (PUN) is designed with p-type transistors. The PUN has to create a current path between the supply rail and the output for every logic 1 of the logic function. This can be done by creating the dual network of the PDN. In the dual network every series connection is turned into a parallel connection and vica versa.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Complex gate design done an other way

As the p-type transistors conduct when the input is logic 0, the function has to be inverted using the De Morgan laws. In this case: y = C (A + B ) = C + A + B = C + AB As it can now be seen, the two methods yield the same results.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

The sizing of CMOS gates I.

The sizing of digital gates is realitvely easy:
the length of the transistor channels in the inverter is the shortest value allowed by the technology, the width of the channel of the n-type FET is the minimal value (or a little bit larger), the channel width of the p-type is 1.5..2 times that of the n-type (due to the dierences in charge carrier mobilities).

The basic inverter is able to charge a given capacitance during in a given delay time.
Along with the input capacitances of the gates connected to the output of the gate, the wires also contribute to the load capacitance that a gate has to drive. These factors determine the fan-out of a CMOS gate. Usually every gate is designed in multiple forms with 2, 4, ... times larger fan-out. In an inverter this means that the transistors have wider channels.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

The sizing of CMOS gates II.

In case of complex gates, the values of the basic inverter are used as a basis for the calculations. When transistors of the same size are connected
in series, their channel lengths add up; in parallel, their channel lengths add up.

This is just an approximation but the MOS channels can be approximated with resistors with a relatively good accuracy. If two n-type MOS FETs with channel sizes of W and L are connected in series and a positive voltage is applied to their gates:
the current of the transistors is proportional to W/L, ID W/L R L/W , when two FETs are connected in series, the equivalent resistances add up: R 2L/W .

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

The sizing of CMOS gates III.

Using the approximation of the previous slide, complex gates can be sized:
if the goal is to have the same delay as the minimal inverter, every current path should have the same resistance as in the inverter.

In the case of a NOR gate:

the current paths in the PDN consist of one transistor, so their sizes can be equal to the n-type transistor of the inverter, there are two p-type transistors in series in the PUN, so there currents have to be doubled to have the same resistance which means that their channel widths have to be doubled.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

The application of transfer gates in gate design

Some gates can be designed with much less transistors using transfer gates. Selective functions are typical examples. Such a circuit is a two input multiplexer: y = AS + BS

This multiplexer would require 8 transistors in traditional CMOS design. With transfer gates only 4 FETs are needed, provided that S is at disposal (usually this is the case as ipops provide the inverted values as well).

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Transfer gates in logic gate design

Logic functions are created using the multiplexer architecture. For example an XOR gate: y = A B = AB + AB

Both solution uses only 4 transistors instead of 8. The XOR function is used in adder circuits.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Clocked CMOS logic

CMOS gates can be driven by a clock signal that either enables or shuts o the gate letting the output oat. They are called: CCMOS, or C2 MOS.

Advantages: small area, three-state operation:

= 0: the output oats (high-impedance), = 1: the input is inverted.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

CMOS domino logic I.

The operation is divided into two phases: Precharge phase: the load capacitance (C1 ) is precharged to the supply voltage by P1 because it faster discharged than charged. = 0, P1 is open, N4 is o. Evaluation phase: the logic function realized by a single PDN is evaluated it either discharges C1 or leaves it intact. = 1, P1 is o, N4 is open.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

CMOS domino logic II.

No static current consumption, just dynamic. Number of transistors: n + 2 (instead of 2n for traditional CMOS).

Problem: the 0 output appears with a delay, as the capacitor is always charged at the beginning of the evaluation phase, thus there is a false glitch at 0 outputs.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

CMOS domino logic III.

Solution I: an extra inverted is inserted between the stages logic 1 outputs appear with a delay, but there are no glitches double inversion.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

CMOS domino logic IV.

Solution II: if the next stage is realized with an inverted logic, the positive glitch doesnt cause problems.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

CMOS domino logic V.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Elements with two states

Monoops:
have stable and an unstable states, when set to their unstable state, they return to the stable state after a certain time, create impulses of a given width.

Bistable ops:
latches: have two transparent states a change at the input is instantly seen at the output, ipops: the output only changes at the rising or falling edge of the clock.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Latches and ipops

Latches are transparent while clock = 1. Flipops change their outputs only at the edges of the clock.

latch

ipop

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Monostable circuits
They make use of the gate delays. In the circuit built of NOR gates below, there is a short positive impulse at the output when the input switches from 1 to 0.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Setting the delays

The maximum current of the inverters is limited with a current mirror. This is a starved inverter. This is a semi-analog circuit. The charging/discharging current is set by the current source and the sizing of the transistors taking part in the current mirrors. The maximum charging/discharging current is I .

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

The principles of MOS data storage elements

Two state circuits are based on two inverters connected in a ring. The have two stable states. In order to be make it enable them to store data, they need to be writable. Multi input logic gates are used instead of inverters for this reason.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

The SR latch
Latches can be built of logic gates. Designing at the transistor level allows for smaller and faster designs. An SR latch can be built with NOR gates. An enable input can be added using an AND gate.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

D latch
D latches are used much more often than SR latches. A D latch can be created using an SR latch:

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

A D latch with an AOI gate

The circuit can be simplied using complex logic gates. A D latch can be realized with just 12 transistors provided that D is available.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

A D latch with transfer gates

An even simpler D latch can be creating using two transfer gates operated alternatively:
During EN = 1: the operation is transparent Q = D as the transfer gate at the input is open connecting it directly to the output, while the feed back transfer gate is closed. During EN = 0: the input transfer gate is closed, the feed back is open, thus the two inverters are connected in a stable feed back and they keep the last value of the input before the transition at EN.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Master-slave ipops
Master-slave ipops are created of two latches connected in series, and the enable signal (clock) inverted for one of them.

Master-slave SR ipop output at falling edge

Master-slave D ipop output at rising edge

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Dynamic D ipop

When CP = 1: T G1 is open, T G2 is closed. The value of D is stored in the parasitic capacitance shown in blue. When CP = 0: T G1 is closed, T G2 is open. The logic value of the master is copied to the slave.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Dynamic D ipop C2 MOS

Two clocked inverters are connected in series. They are operated alternatively. The information is stored in the parasitic capacitance between the master and the slave.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Full adder I.

Full adder FA: Inputs: A, B , CIN (carry in) Outputs: S (sum), COU T

Logic functions of the full adder COU T = AB + CIN (A + B ) S = ABCIN + (A + B + CIN )COU T

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Full adder II.

A full adder can be realized with two complex gates, but COU T is computed in 1 gate delay, while S in 2. An other problem is that the outputs of the complex gates are inverted, so extra inverters are needed.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Full adder III.

The full adder circuit:

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Ripple carry adder I.

Ripple carry adder: the series connection of full adders for adding multi bit numbers.

Problems: In order to compute bit #1, COU T 0 has to be computed. In order to compute bit #2, COU T 1 has to be computed. The entire computation takes n tCOU T time.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Ripple carry adder II.

The extra inverters between the stages can be spared by using inverted logic at every 2nd FA.

This solution is faster, but every second sum bit is inverted. An even faster way of adding is to calculate the carries in advance this is done by the carry look-ahead architecture.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Multipliers I.

Multiplication can be done using combinational logic:

If a given bit of B is 1, then it will be added to the result, otherwise it wont.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Multipliers II.
The circuit realizing the algorithm above:

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Multipliers IV.
An other subcircuit that appears in the multiplier:

A half adder (HA) is an adder that has no carry input.

This is a critical operation many solutions exist to speed it up.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Buers I.

In complex circuits information is propagated on long, shared lines, called buses.

Long lines impose large capacitive loads on the drivers. Thus driving circuits need to have large output currents. Tristate outputs needed to enable several drivers on the same bus.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Buers II.
Buers can be realized using the series connection of inverters that have an increasing W/L ratio.
Tarnsistors of large W/L ratios have large output currents, but their input capacitance is large as well, so normal inverters can not drive them. This is why the W/L ratio has to be increased step-by-step.

W/L = 5, 20, 80, ...

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

Tristate buer

increased output drive

The output is in high impedance mode when EN = 0.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

I/O circuits I.

Output circuits Usually tristate buers complemented with D ipops to store the output value. Input circuits They protect the circuit from high voltages, that would harm the devices. This is called ESD protection due to the fact, that MOS transistors are very sensitive to electrostatic discharges the oxide breaks down at high voltages. The gates of the input transistors are protected using resistors and diodes.

Realization of logic functions

CMOS monoops, latches and ipops

Arithmetic circuits

Buer circuits

I/O circuits II.

The inputs are protected using the circuit below. When the input voltage goes above the supply voltage or below ground potential, the diodes open, and drive the currents away from the gate. The resistor limits the current of diodes.