IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO.

4, NOVEMBER 1996

519

Obtaining J-K, D, and T Excitation Equations Directly from State Transition Diagrams
Richard S. Sandige, Senior Member, IEEE
Abstract- This paper presents techniques for obtaining J IC, D , and T excitation equations for synchronous state machine designs directly from state transition diagrams. Classical designs using li-maps (Karnaugh maps) are time consumingto draw and difficult to use when large designs are involved. Computer tools are very valuable for assignmentsoutside of the classroom,that is, for homework assignments, laboratory assignments, and special projects, but computers are not generally provided for student use on quizzes and exams. The techniques for obtaining flip-flop excitation equations presented in this paper apply to large or small designs. The excitation equations that are obtained usually need to be reduced prior to implementation. Although equation reduction is not the theme of this paper, some of the excitation equations will be obtained using algebraic reduction, li-map reduction, and computer tool reduction to allow comparisons to be made.

I. INTRODUCTION NE MAJOR disadvantage of using either classical design via K-maps [l], [2] or a computer tool [ 3 ] to obtain excitation equations is the fact that the procedures are rather rote and therefore students are not forced to completely understand the requirements of a specific flip-flop in a design. The techniques presented in this paper allow students to evaluate synchronous state machine designs via a state transition diagram or an equivalent algorithmic state machine (ASM) chart [4]to determine the specific requirements for the excitation inputs of the flip-flops being using in the designs. If reduced excitation equations are to be obtained by hand, the resulting excitation equations can either be minimized algebraically or via K-maps. A computer tool can also be used to minimize the resulting excitation equations for assignments outside of class. In the first digital design course taught by the author at the University of Wyoming [5], student acceptance of the techniques described in this paper has been extremely good. Designs for this paper center around the sample synchronous circuit [6] presented in Section 11. The techniques for obtaining the excitation equations for J-K flip-flops is presented in 1 1 . Techniques for obtaining the excitation equations Section 1 for D and T flip-flops are presented in Sections IV and V respectively. The designs are checked using solutions obtained by K-maps and solutions obtained by the computer tool PLDesigner-XL.

Fig. 1. State transition diagram of the sample synchronous circuit.

11. THE SAMPLE SYNCHRONOUS CIRCUIT

The sample synchronous circuit used in this paper has two input variables XI and X 2 , two output variable 2 1 and 2 2 , and three states in its main sequence as illustrated by the state transition diagram shown in Fig. 1. State d, i.e., the unused, illegal, or dead state, is used to illustrate how to handle dont cares. The state assignment was picked to minimize the output equations for 21 and 2 2 such that 21 = y l and 2 2 = y2, where the State = y1y2 uses a minimum number of flip-flops encoding scheme (less than one flipflop per used state-actually [log, s] flip-flops for s used states or rlog,3] = 2 flip-flops for three used states, where [log, 31 = [ln 3/ In 21 = 2, i.e., the smallest integer greater than or equal to log, 3).
1 1 1 . OBTAINING THE EXCITATION

EQUATIONS FOR J-K FLIP-FLOPS Consider the characteristic table for the J-K flip-flop [51,
[7], Table I. Lower case y is used as the present state variable

while upper case Y is use as the next state variable. The Boolean function for Y , the characteristic equation of the J K flip-flop, is written directly from the characteristic table as follows:

Manuscript received July 7, 1993; revised May 24, 1995. The author is with the Department of Electrical Engineering, University of Wyoming, Laramie, WY 82071 USA. Publisher Item Identifier S 0018-9359(96)08738-9. 0018-9359/96$05.00 0 1996 IEEE

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IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO 4, NOVEMBER 1996

TABLE I

TABLE I1

1 to 0 chan e of i, clear condition

y
111 0

where - = dont care

Ki=Yiwhenyi=l(yi=O), fori=l...n ( n = number of flip-flops).
-

(5)

Y i

~i

+ yi .E, for i = 1. . .n
( n = number of flip-flops).
i2)

Using (2) the excitation inputs Ji and K i are obtained as roilow s: Yz @ Y z= (y2.J?,+ yz .E) @Yz 0 = ($ . J i yz . E )@ Y i 0 @3 J i y i .E) = (@. Ji y i @ Yi@ J i yi .E) Ji + y i . K i ) = 0 @ Y i

Equations (4) and ( 5 ) are expressed in truth table format, called the J - K excitation table, as shown in Table 11. This table is used when deriving excitation equations for J-K flip-flops via the classical K-Map design approach. The technique for writing the J - K excitation equations directly from state transition diagrams is presented as follows: Equation Comment 0 to 1 changes of y i unused state (6)
1 to 0 changes of yz unused state

J i = C(present state) . (0 to 1 condition)

+ (G. + (y.. + (3.

+ C(unused state) . when $ = l ( y i = 0)

.Ki)

Ki = C(present state)

+ C(unused state) - when yz = 1(G = 0).

(3)

(1 to 0 condition)

($. J i +yz . E ) = Yi Jz. = Yz when $ = l ( y i = 0), for z = 1. . . n

( n = number of flip-flops)

(7)

Observe that J i is generated from set conditions (zero to one changes of y i ) while Ki is generated from clear conditions (4) (one to zero changes of y i ) . This technique may be referred to

J1= y l . y2.X1

_ _
e

+ +yl
when

y2 X1 .

0 to 1 change of y l , set condition 0 to 1 change of y l , set condition

y2 -

3 = l ( y 1 = 0)

unused state, dont care J1 = $ . X l + y 2 . X I

.x2

K1 = y l . y2.X1 . X 2

_ - -

1 to 0 change of y l , clear condition 1 to 0 change of y l , clear condition

+ y l .$. E .X 2 + y l . y2.
-

whenyl= l ( s = O ) 5 2 = y 1 . y 2 . x1 . x 2 y l .$. X2 + y 1 . y2 when $ = l(y2 = 0)

_ _ -

unused state, dont care - - - Kl=y2-Xl.X2+y2-Xl.X2+y20 to 1 change of y2, set condition

(9)

m.

0 to 1 change of y2, set condition unused state, dont care - J 2 = y l .X1 . X 2 + y l . X 1 X 2

1 to 0 change of y2, clear condition 1 to 0 change of y2, clear condition

K2 =

9 y2 X1 . X 2 + g .y2 . X1 .
+

- -

y1. y2. unused state, dont care _ - when y2 = l($ = 0) K 2 = y 1 . X 1 . X 2 + g .X1

. m +y 1 . -.

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SANDIGE: OBTAINING J-K, D, AND T EXCITATION EQUATIONS DIRE(3TLY FROM STATE TRANSITION DIAGRAMS

521

yly2blX2 J1

yly2\XlX2
K1 =

J1 = S * X 1
(a)

X1-

yly2\XlX2
52 =

YlY,2\XlX2 K2 =

52 = X1*X2
(c)
(d)

Fig. 2. J - I C excitation equation reduction using IC-maps. (a) J 1 map with reduced equation. (h) Iil map with reduced equation. (c) J 2 map with reduced equation. (d) I i 2 map with reduced equation.

as the setklear method for writing J-K excitation equations. The excitation equations (8)-(11), shown at the bottom of the previous page, are written by inspection from the state transition diagram of the sample synchronous circuit using (6) and (7), respectively. For the small sample synchronous circuit design in this paper, like those on quizzes and exams, excitation equation reduction for J - K flip-flops is not difficult and can be obtained algebraically as illustrated below

reduced, i.e., minimum sum of products equations in this case, obtained using the setklear method after algebraic reduction andor K-map reduction agree with those obtained using the classical K-map design approach as expected. The PLDesigner-XL computer tool reduces large or small equations. The design source file to reduce (8)-( 11) is written
as

INPUT y l , y2, X1, X 2 ; OUTPUT J1,K1,52, K2;

Jl=$.Xl+y2.Xl.X2
= x1. ($+y2

.E)

=Xl.($+x2)
=

J1 = / y 2 * x 1 + y2*Xl*/X2; K l = /y2*/Xl*/X2 /y2*/Xl*X2 + y2*.x.;

2. x 1 + x1 .x2

K1= $.XT*xa+$.XT.X2 y2. =8. XI. X2) y 2 . - = y 2 . x l +9 2 . - =xi+ y2. =x 1 52 = 9. x 2 y1. x 2

(xa+ +

+ 5 2 = /yl*/Xl*X2 + yl*/Xl*X2; K2 = /yl*/Xl*/X2 + /yl*Xl*/X2 + yl*.X.;

Compiling the design source file using the QuineMcCluskey equation reduction method results in REDUCED EQUATIONS: J1. EQN = X1*/X2

xi. + xi.

37. x2. (S+ yl) -

+ Xl*/y2; (2 terms, 3 symbols)

=Xl.X2 K 2 = iji. XI. x2+3 .x1.x2+ y 1 .

=

3 .x2.(XIS XI) + y l .
- -

K1. EQN = /X1; (1 term, 1 symbol) 52. EQN = /Xl*X2; (1 term, 2 symbols) K2. EQN = /X2; (1 term, 1 symbol).
To obtain a complete set of equations for the sample synchronous circuit, i.e., those available for fuse map implementation in a programmable logic device (PLD), the following design source file was written using the setklear equations (8)-(11). Notice in the new design source file that the inputs must be changed, the J - K flip-flop outputs must be specified and clocked, and the left side of each equation must be modified, i.e., all variables had to be present in all dont care product terms (product terms ending with .X.), to insure

=yl .X2+yl. = x2.

___

=x 2 + y l .

Excitation equation reduction is simple combinational logic reduction that can also be performed using K-maps as shown in Fig. 2(a)-(d) for (8)-(11). Fig. 3(a) shows the flow map for the sample synchronous circuit in K-map format with the state assignment filled in. Fig. 3(b)-(e) is drawn and plotted using the excitation table for the J-K flip-flop. Observe that the

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IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 4. NOVEMBER 1996

y 1 y2\x 1x2

/z122
00 01

-lo

J1

00 01 11 10

K1

y 1y2\x 1x2

J2

YlY K2 =

K2 = X2
(4
(e)
Fig. 3. (a) Flow map for sample synchronous circuit. (b) J1 map for classical solution with reduced equation. (c) K1 map for classical solution with reduced equation. (d) J 2 map for classical solution with reduced equation. (e) K 2 map for classical solution with reduced equation.

proper equation reduction INPUT X1, X 2 , CK; JKPLOP OUTPUT y l , y2 CLOCKEDBY CK; y 1 . J = /y2*Xl+ y2*Xl*/X2;

TABLE I11

+ /y2*/XI*X2 + yl*y2*.X.; y2.J = /yl*/Xl*X2 + yl*/Xl*X2; y2.K = /yl*/Xl*/X2 + /yl*Xl*/X2 + yl*y2*.X.;

y1.K = /y2*/Xl*/X2 The following design equations were obtained after compiling the design. Note that y1.J represents the J input to flip-flop one, y1.K represents the K input to flip-flop one, y2. J represents %e J input to flip-flop two, and y2.k represents the K input to flip-flop two. REDUCED EQUATIONS: y1.J = Xl*/X2 Xl*/y2;/(2 terms, 3 symbols)

method after algebraic reduction and/or K-map reduction and with those obtained using the classical K-map design approach. The signal yl.CLK represents the CLK input of flipflop one, and y2.CLK represents the CLK input of flip-flop two.

Iv.

OBTAINING THE EXCITATION EQUATIONS FOR D FLIP-FLOPS

y1.K = /Xl;(1 term, 1 symbol) yl.CLK = CK;/(l term, 1 symbol)

y2. J = / X l * X 2 ; I ( 1 term, 2 symbols) y2.K = /X2;(1 term, 1 symbol) y2.CLK = CK;/(l term, 1 symbol).

The characteristic table for the D flip-flop [SI is listed in Table 111. The Boolean function for Y , the characteristic equation of the D flip-flop, is obtained by inspection as Y = D or in general as

Y i = Dz, for z = 1 ... n ( n = number of flip-flops). (16)

The excitation input D i is obtained as follows:

Note that the reduced equations for y l . J , yl.K, y2.4 and y2. K agree with those obtained earlier using the setlclear

Yi @ Y i= Di @ Yi 0 = Di @ Y i

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SANDIGE: OBTAINING J-K, D, AND T EXCITATION EQUATIONS DIRECTLY FROM STATE TRANSITION DIAGRAMS

523

D1=i!
gly2 1xic
0 1 1 11

- - - 0 1 1

10 0
=

'Dl

2 ~ x+ 1Xl-z

D2 = y 2 . n + z * X Z

Fig. 4. D excitation equation reduction using A-maps. (a) DI map with reduced equation. (b) 0 2 map with reduced equation.

Di = D i@Y i@ Di

TABLE IV

D i = Yi, fori = l . . . n
(n = number of flip-flops).

(17)

0 to 1 change of yi, set condition Expressing (17) in truth table format results in the D 1 0 0 excitation table, Table IV. This table is usually bypassed 1 1 1 1 to 1 change of yi, hold 1 condition when obtaining excitation equations for D flip-flops using the i reduction for large or small designs is a computer tool if classical K-Map design approach by simply solving for Y and substituting Y i for Di. one is available. For small designs like those on quizzes and The technique for writing the D excitation equations directly exams, the preferred method of equation reduction is to enter from state transition diagrams is presented as the combinational logic excitation equations into K-maps then obtain the minimum equations as illustrated in Fig. 4(a) and Equation Comment Di = C(present state) (b), for (19) and (20), shown at the bottom of the page. 0 to 1 changes of yi . (0 to 1 condition) The design source file to reduce (19) and (20) using the C(present state) computer tool PLDesigner-XL is listed as follows: . (1 to 1 condition) 1 to 1 changes of yi C(unused state) . unused state. (18) INPUT y l , $2, X1, X 2 ; Observe that Di is generated from set conditions (zero to OUTPUT D1,DZ; one changes of yi) or hold one conditions (one to one changes D1 = / y l * / y 2 * X 1 + /yl*y2*XI*/XZ of yi). This technique may be referred to as the "set or hold y l * / y 2 * X l + yl*y2*.X.; 1 method" for writing D excitation equations. The excitation equations (19) and (20), shown at the bottom of the page, are 0 2 = /yl*/y2*/Xl*X2 yl*/y2*/XI*XZ written by inspection from the state transition diagram of the /yl*yZ*X2 yl*y2*.X.; . sample synchronous circuit using (18). Since two conditions (set or hold 1) must be used to derive Compiling the design source file using the Quineeach D excitation equation, algebraic equation reduction is usually difficult. The preferred method to use for equation McCluskey equation reduction method results in the following

00 0 1

0 1

+ +

D1= ~ 1 ~ .2X1 . + $. y2 . X1 .
+yl.$.Xl

_ _

0 to 1 change of y l , set condition 0 to 1 change of y l , set condition

1 to 1 change of y l , hold 1 condition unused state, don't care y l .y 2 . = iji. $. xl+iji. $2. x1. x'2+ yl * 8 . xl+ y l . y 2 . -

0 2 =g

.2 .x1. x2 X2 + y l .$.

+ $ . y2 . x 2 unused state, don't care + y1 . y2 . = iji.$. x 2 + x 2 + y l .$. xi. x 2 + g .y 2 . x 2 + y l . y 2 . -.

0 to 1 change of y2, set condition 0 to 1 change of y2, set condition 1 to 1 change of y2, hold 1 condition

xi.

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IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 4, NOVEMBER 1996

TABLE V

TABLE VI

*
equations: REDUCED EQUATIONS: D1.EQN = X l * / X 2 D2.EQN T / X l * X 2

0 0 0 1
1 0 1 1

10 1 1 0

0 to 1 change of yz, set condition 1 to 0 change of yz, clear condition

+ X l * / y 2 ; (2 terms, 3 symbols)
+ X2*y2; (2 terms, 3 symbols).

Expressing (22) in truth table format results in the T excitation table, Table VI. This table is used when deriving excitation equations for T flip-flops via the classical K-Map design approach. The technique for writing the T excitation equations directly from state transition diagrams is presented as follows: Equation Comment 0 to 1 changes of yi
1 to 0 changes of y i unused state.

Observe that the reduced equations obtained using the set or hold 1 method after K-map reduction agree with the reduced equations obtained using the computer tool. V.
OBTAINING THE EXCITATION EQUATIONS FOR T

Ti = C(present state)

FLIP-FLOPS

The characteristic table for the T flip-flop [5] is listed in Table V. The Boolean function for Y , the characteristic equation of the T flip-flop, is obtained as follows: Y =g.T+y.T @ T i , for i = 1

+ C(present state) . (1 to 0 condition) + C(unused state)

. (0 to 1 condition)

Yi = yi

s..

( n = number of flip-flops).

(21)

The excitation input Ti is obtained as follows:

Y i @ Y i = y i @ T i@ Y i 0,=y i @ T i@ Yi 0 $ T i = y i $ T i $ Y i @ Ti Ti = y i @ Y i @ 0 T i = y i @ Yi, for i = l . . . n ( n = number of flip-flops).

(22)

(23) Observe that Tz is generated from set conditions (0 to 1 changes of yz) or clear conditions (one to zero changes of y i ) . This technique may be referred to as the set or clear method for writing T excitation equations. The excitation equations (24) and (25), shown at the bottom of the page, are written by inspection from the state transition diagram of the sample synchronous circuit using (23). Like D excitation equations, T excitation equations are derived with two conditions usually making algebraic equation reduction difficult. The preferred method to use for equation reduction for large or small designs is a computer tool. For small designs in the classroom, the preferred method to perform equation reduction is to enter the combinational logic excitation equations into K-maps then obtain the minimum equations as illustrated in Fig. 5(a) and (b) for (24) and (25).

T1= y l . y 2 . X l

- _

+ y l . y 2 . X1 . X 2 + y l .g . X 2 + y l . y2

+5 .y2 . X1 . x2 - -

0 to 1 change of y l , set condition 0 to 1 change of y l , set condition

1 to 0 change of yl, clear condition

=jji.y2.Xl+iJ.

1 to 0 change of y l , clear condition unused state, dont care y2 .x1. x 2 + y l .$.xl.;!+y1 .$.xi. x 2

+yl .y2. -

T2=g.$*XZ.X2 y1 . $ . X2 - _ 9.y2 . X 1 . X 2 g .y2 . X1 . x2 y1 . y 2 . = 3.8. x 2 + y l

+ + + +

0 to 1 change of y2, set condition

0 to 1 change of y2, set condition 1 to 0 change of y2, clear condition 1 to 0 change of y2, clear condition unused state (dont care)
. $2.

xi.

T i . x2 + 3 .y 2 . XI. x2+ 5 .y 2 . x1.x2+y l . y 2 . -.

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SAN1XGE: OBTAINING J-K, D, AND T EXCITATION EQUATIONS DIRLECTLY FROM STATE TRANSITION DIAGRAMS

525

Y 1Y,2t(lX2
T1 =

TI = y 1 . x +

g.Z.x1 +
(a)

3.x1.5

T2 = $.X1.X2
(b)

y2.S

Fig. 5. T excitation equation reduction using K-maps. (a) T1 map with reduced equation. (b) T2 map with reduced equation.

The design source file to reduce (24) and (25) using the computer tool PLDesigner-XL is listed as follows: INPUT y l , y2, X1, X2; OUTPUT TI, T2; T1 = /yl*/y2*X1+ /yl*y2*Xl*/X2

+ yl*y2*.X.;

+ yl*/y2*/Xl*/X2 + yl*/y2*/Xl*X2
+ + yl*y2*.X.; . + +

T2 = /yl*/y2*/Xl*X2 yl+/y2*/Xl*X2 /yl*y2*/Xl*/X2 /yl*y2*Xl*/X2 Compiling the design source file using the QuineMcCluskey equation reduction method results in the following equations:

state was also used as a dont care to simplify the excitation equations. Since modern designs generally use power-up reset to initialize synchronous circuits to a used state at turn on or when a power line glitch occurs, unused states can be used in this manner. The derivation of D and T excitation equations each require two conditions (set or hold 1 for D and set or clear for T ) making algebraic equation reduction difficult. Several methods were presented for obtaining reduced excitation equations. For small designs on quizzes and exams, K-map reduction was stressed as a good technique for excitation equation reduction. The preferred method for excitation equation reduction is to use a computer tool such as the one used in this paper, PLDesigner-XL. With such a tool a final design can also be implemented in a PLD from major vendor.

REDUCED EQUATIONS: T1.EQN = Xl*/X2*/yl+ Xl*/yl*/y2 + /Xl*yl;(3terms, 4 symbols) T2.EQN = /Xl*X2*/y2 + /X2*y2; (2 terms, 3 symbols).
Observe that the reduced equations obtained using the set or clear method after K-map reduction agree with the reduced equations obtained using the computer tool. VI. CONCLUSION

REFERENCES
V. T. Rhyne, Jr., Fundamentals of Digital Systems Design. Englewood Cliffs, NJ: Prentice-Hall, 1973. R. S . Sandige, The transition-map-entered-variable (T-MEV) mapping technique for sequential machine design, Doctoral dissertation, Texas A&M Univ., 1978. PLDesigner-XLTM users guide, The next generation in programmable logic design synthesis, Version 3.2, MINC Incorporated, Colorado Springs, CO, i994. Systems Using State Machines. New C. R. Clare, Designing Lonic . York McGraw-Hill, 1973. R. S. Sandiae. Modern Digital Design. New York: McGraw-Hill, 1990. S . H. Ungir, The Essen& of Losic Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1989. C. H. Roth Jr., Fundamentals ofLogic Design, 4th ed. St. Paul, M N West, 1992. R. S. Sandige 73.3 bistable devices, in The Electrical Engineering Handbook, R. C. Dorf, Ed. Boca Ratan, FL: CRC, 1993, pp. 1635-1641.

This paper has presented techniques for obtaining J - K , D , and T excitation equations for synchronous circuits directly from state transition diagrams. The three methods presented were the sevclear method for J-K flip-flops, the set or hold 1 method for D flip-flops, and the set or clear method for T flip-flops. Students tend to gain a superior understanding Richard S. Sandige (S63-M64-SM90) received the B.S.E.E. and M.S.E.E. degrees from West Virginia University, Morgantown, WV, in 1963 and 1969, of each type of flip-flop and the role it plays in the design respectively, and the Ph.D. degree in electrical engineering from Texas A&M of synchronous circuits by using these methods. The J - K University, College Station, TX, in 1978. He is currently a Professor in the Department of Electrical Engineering, flip-flop excitation equations were shown to be the easiest University of Wyoming, Laramie. Prior to joining the staff at the University to obtain. Since the derivation of J - K flip-flop excitation of Wyoming, he worked for ten years as a Member of the Technical Staff in equations only require one condition (set for Jlclear for K ) , the Research and Development Laboratory at Hewlett Packard, Fort Collins, algebraic equations reduction is not difficult for small designs. CO. His research interests include PLDs and FPGAs and their applications in digital design and microprocessor systems. He currently supports the research The sample synchronous circuit used in this paper has an and development activities of Minc Incorporated, a technology leader in unused state to illustrate how to handle dont cares. The unused programmable logic synthesis tools.

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