J Comput Electron DOI 10.

1007/s10825-013-0483-6

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

Punyasloka Bal M.W. Akram Partha Mondal Bahniman Ghosh

Springer Science+Business Media New York 2013

Abstract In this paper we examined the short channel behavior of junction less tunnel eld effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET. Keywords Band to band tunneling (BTBT) Drain induced barrier lowering (DIBL) Scaling Junctionless tunnel eld effect transistor (JLTFET) Subthreshold slope (SS)
P. Bal ( ) M.W. Akram P. Mondal Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India e-mail: punya@iitk.ac.in M.W. Akram e-mail: mwakram@iitk.ac.in P. Mondal e-mail: partham@iitk.ac.in B. Ghosh Microelectronics Research Center, University of Texas at Austin, 10100 Burnet Road, Austin, TX, 78758, USA e-mail: bghosh@utexas.edu

1 Introduction As we scale down the metal oxide semiconductor eld effect transistor (MOSFET) to sub-30 nm regime, it faces fundamental challenges and major difculties in fabrication of sharp doping gradient at the source and drain junction [1, 2]. Poor electrostatic control and diminished short channel behavior of conventional MOSFET gives rise to low value of drain induced barrier lowering (DIBL) and high leakage current in OFF state. The MOSFET is named as the inversion mode (IM) device due to the formation of inversion layer for making the path of current to ow. Scaling down the supply voltage and threshold voltage in IM devices is a major contributor to the subthreshold leakage which leads to excessive power consumption. The limitation in subthreshold swing (SS) due to Fermi Dirac distribution of energy becomes the bottleneck for further scaling of supply voltage. A low value of subthreshold swing gives a lower subthreshold leakage which further gives rise to low power dissipation. A conventional MOSFET cannot overcome this theoretical limitation due to its drift diffusion mechanism of current conduction. Over the last few decades, alternative transistors have been proposed to achieve SS lower than 60 mV/decade at room temperature, because of low power demand. The most commonly reported among alternative transistors is tunnel eld effect transistor (TFET) [3], which does not suffer from short channel effects (SCEs) due to its tunneling barrier. Though conventional TFET has better subthreshold slope (SS) than inversion mode (IM) device, it has low ON current and fabrication becomes challenging in sub-20 nm region for both TFET and IM device. Based on lilienfelds rst transistor architecture [4], very recently, a transistor has been proposed and named as junctionless eld effect transistor (JLFET). The JLFET is basically an accumulation mode

J Comput Electron Fig. 1 Schematic representation of (a) structure of JLTFET (b) structure of inversion mode (IM) device

device which does not require any ultra-steep doping prole at the source and drain junctions. This shows that JLFET is a promising device for future technology as it reduces the fabrication complexity as well as cost of fabrication. To optimize the performance of JLFET, new design approaches, such as, SOI JLFET, bulk planar JLFET, nanowire junctionless transistors [57], gate all around FET [8] have been proposed. By taking the fabrication issue and limitation in supply voltage scaling into account, a new structure named junctionless tunnel eld effect transistor (JLTFET) has been proposed [9, 10], which is a tunnel FET without any sharp doping prole. A JLTFET is a heavily doped junctionless transistor which uses the concept of band to band tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF [11]. Since JLTFET is based on junctionless principle, so intrinsically it has better short channel effects and variability. Though the conventional tunnel FET shows an improved IOFF and subthreshold slope, however it is still limited due to its low ON current. The newly proposed JLTFET overcomes the challenges of low ON current suffered by conventional tunnel FET and also have improved subthreshold slope than conventional MOSFET. In this paper we explore the performance of JLTFET and conventional MOSFET and comparison was made on the basis of variation of gate length and oxide thickness.

2 Device structure and operation Figure 1(a) shows the structure of JLTFET for n-channel operation. The JLTFET is a junctionless transistor with two gates; one is the controlling gate and second is the xed gate. The function of xed gate is to make the source of JLFET behave as p-type by work function engineering. By making the source p type, we made JLFET to behave similar to TFET where, by xing the side gate voltages and sweeping the voltage of the control gate from 0 to VDD , we made the device ON and OFF. The JLTFET is basically a junctionless transistor with uniform doping throughout the source, drain, and channel region, however the operation of JLTFET is similar to that of conventional tunnel FET. Figure 1(b) shows the structure of IM device, which has similar device parameter as that of JLTFET for performance comparison. Both the device have a uniform doping of 2 1019 cm3 for source and drain and are simulated for same threshold voltage of Vth = 0.407 V at a drain bias of VDS = 1 V. The spacer widths of 5 nm and gate dielectric thickness of 2 nm are taken same for both the devices. For JLTFET the xed gate uses platinum as the gate material, with a work function of 5.93 eV and the control gate uses p.polysilicon as gate material with work function of 4.7 eV. For inversion mode device we have used p.polysilicon as gate material with a work function of 4.89 eV. Figure 2 shows the band diagram of

J Comput Electron

Fig. 2 Valence band and conduction band prole of ON state (VGS = 1 V) and OFF state (VGS = 0 V) of JLTFET with gate length Lg = 25 nm Table 1 Parameters for device simulation Parameter Channel doping (Nd) Gate oxide thickness (TOX ) Gate work function Channel length (Lg ) Silicon thickness (Tsi ) Width of spacers Work function of xed gate JLTFET 2 1019 cm3 2 nm 4.7 eV 25 nm 5 nm 5 nm 5.93 eV MOSFET 2 1015 cm3 2 nm 4.89 eV 25 nm 5 nm 5nm

Fig. 3 ID VG characteristic of JLTFET and MOSFET with gate length of 25 nm

OFF state and ON state of JLTFET. When a positive voltage is applied to the control gate the band bending occurs and tunneling phenomenon begins, where electrons tunnel from source side to channel region to make device ON. The basic approach is to convert the (N + N + N+) source, channel and drain of junctionless FET into a (P I N) structure without any physical doping. Hence JLTFET by combining advantage of both JLFET and TFET signies its importance both in high ION /IOFF ratio and improved subthreshold slope without any fabrication issue.

3 Results and discussion All simulations are carried out using Silvaco Atlas version 5.15.32 R [12] which uses non-local band to band tunneling model (BTBT) to account for the current accumulated due to tunneling of electron from source to channel side of the regime [12, p. 245]. We include the effect of Fermi Dirac statistics in the calculation of the intrinsic carrier concentration required in the expressions for Shockley Read Hall (SRH) recombination. We have used non local band to band tunneling model and calibrated it with models used in [11]. Assuming high doping concentrations Band gap narrowing (BGN) and auger recombination models are included in the

simulations. Because of presence of high impurity atom in the channel and also consideration of an interface trap (or defect) effect, Shockley-Read -Hall (SRH) model is also included [14]. The interface trap effect on BTBT is also enabled, by inclusion of trap assisted tunneling (TAT) model given by Schenk [15, 16]. With the assumption of high k metal stack direct gate tunneling was not included in the simulation [13]. Figure 1(a) and (b) shows the structure of JLTFET and MOSFET respectively and all the relevant parameters used for simulation are listed in Table 1. The simulated JLTFET structure has uniform doping throughout the source, drain and channel region. For inversion mode device the channel is doped P-type with a concentration of 2 1015 cm3 and source and drain doping remain same for both the devices. Both the device (IM mode and JLTFET) were optimized for same threshold voltage i.e. Vth = 0.407 V (at a drain voltage of VDS = 1 V) (Vth extraction was done using constant current method i.e. at VDS = 1 V at IDS = 107 Amp/m). All other simulation parameters like oxide thickness (Tox ), gate dielectric constant (K), silicon thickness (Tsi ), gate length (Lg ) were remain same for both the device. The electrical characteristics of JLTFET and conventional MOSFET are compared in Fig. 3. We can observe that JLTFET has better ION /IOFF ratio and also have better DIBL and subthreshold slope than conventional MOSFET. As the current conduction in MOSFET is due to diffusion mechanism, the theoretical limit of sub threshold slope is 60 mV/decade. On the other hand, a JLTFET does not experience the same theoretical limitation because here the current conduction mechanism is due to tunneling of electron by lowering the barrier height between source and channel of the device. Figure 4 shows the qualitative comparison of junctionless tunnel FET and MOSFET at different drain voltages. By considering the operating point A, we can observe that due to sub-thermal subthreshold swing, TFET offers not

J Comput Electron

Fig. 4 Qualitative comparison of JLTFET and MOSFET at different drain bias. At operating point A due to sub thermal sub-threshold swing JLTFET offers an improved performance in terms of high ON current and improved ION /IOFF

Fig. 6 Effect of ON to OFF ratio as a function of drain bias for JLTFET and MOSFET, Nd = 2 1019 cm3 , Lg = 25 nm and Tsi = 5 nm

Fig. 5 ON state and OFF state current as a function of drain bias, Nd = 2 1019 cm3 , Tox = 2 nm, Tsi = 5 nm, Lg = 25 nm

only an improved ION /IOFF but also superior performance in terms of high ON current as well as steep SS (drain voltages VDS = 50 mV and VDS = 1 V) than that of conventional MOSFET. SO TFET shows a good power saving (same ION at lower voltage) at the same performance of conventional MOSFET. At lower gate bias (for different drain bias), TFET can be a good switching device as compared to MOSFET but as we go towards higher gate voltage (consider point B) then it can use as a good switching alternative only for drain bias of 1 V. For 50 mV of drain bias MOSFET can be a better solution in case of efcient switching performance which provides high ON current at same voltage as compared to JLTFET. 3.1 Supply voltage scaling Figure 5 shows the plot for ON state current and OFF state current as a function of different supply bias. We can observe an interesting phenomenon like at low drain bias VDS ranging from 50 mV to 0.7 V, the ON current of JLTFET is

lower than that of MOSFET but OFF state current is signicantly lower than the conventional one. At higher drain bias ON state current both almost lies in the same order for both the devices but OFF state current of JLTFET has a marginal lower value as compared to OFF state current of MOSFET. So the JLTFET not only gives high ION /IOFF but also provides improved performance in terms of low OFF current and low SS at same drain voltage, than that of conventional MOSFET. At drain bias of 0.5 V the optimized performance is observed in terms of good ON state current as well as low leakage. The threshold voltages of devices are xed at 0.4 V, which degrades the performance of JLTFET in terms of low ON current below 0.4 V. The performances can be improved by decreasing the threshold voltages by xing the metal gate work function to some lower value. Figure 6 shows the comparative study of ION /IOFF for both conventional MOSFET and JLTFET. As discussed from Fig. 5 due to lower OFF state current at lower drain bias, JLTFET offers an improved ION /IOFF as compared to conventional MOSFET. At higher drain bias the value almost lies in same order as negligible difference observed between the ON state current and OFF state current at higher bias. So JLTFET can be a good alternative for switching application in terms of good ION /IOFF and better SS at a drain bias of 0.5 V. This value can be lowered by making the threshold voltage minimum. At drain bias of 50 mV there is signicant improvement is observed, but at lower gate bias. With increase of VG the JLTFET fails to provide improved ON current as compared to MOSFET. 3.2 Length scaling Figure 7 shows the performance comparison of DIBL and subthreshold slope of JLTFET and IM device, as a function of gate length and we observed that JLTFET have better DIBL and subthreshold slope than that of IM device. The simulation results illustrates that, even a 10 nm gate length

J Comput Electron

Fig. 7 DIBL and subthreshold slope of JLTFET and IM device as a function of gate length scaling

Fig. 9 ION /IOFF ratio and subthreshold slope as a function of oxide thickness for JLTFET and MOSFET with gate length of 25 nm, Tox = 2 nm, Tsi = 5 nm and Nd = 2 1019 cm3

3.3 Gate dielectric Figure 9 shows the ION /IOFF ratio and subthreshold slope of JLTFET and conventional MOSFET versus different oxide thickness. Through simulation we observed that JLTFET with Tox = 5 nm have better subthreshold slope (38 mV/decade) than inversion mode device with Tox = 2 nm (SS = 70 mV/decade), taking all other device parameter same for both JLTFET and IM device. The ION /IOFF of both the devices are obtained by taking the ON state current (at drain bias of 1 V and gate bias of 1 V) and OFF state current (at drain bias of 1 V and gate bias of 0 V) in to account. At Tox = 2 nm, the JLTFET has an ION /IOFF of 4.08 109 and for MOSFET the ratio is approximately 1.39 109 , which is three times less in magnitude as compared to ION /IOFF of JLTFET. As we increase the oxide thickness to 5 nm (JLTFET offers an ION /IOFF of 1.85 108 and for MOSFET the value is 1.825 105 ), the difference in ION /IOFF for both the devices increases and at thicker gate oxide JLTFET offers an improved performance both in terms of low SS and high ION /IOFF (more than 3 order in magnitude than that of MOSFET). The conventional thermally grown silicon dioxide (SiO2 ) will soon reach the thickness limit to serve as an effective gate dielectric for MOS devices. For performance optimization a new dielectric with a high dielectric constant (ex., HfO2 , TiO2 , Ta2 O5 , and ZrO2 ) is needed for serving the purpose of gate oxide [1719]. Tantalum oxide (Ta2 O5 ) is widely used as a high-k (K = 26) dielectric material due to its superior dielectric properties (low band gap of 4.4 eV and electron band offset of 0.3 eV). For future technology node the highk gate dielectric lm should be small (in the range of 0.6 1.1 nm) to serve for the performance optimization. The Tantalum oxide (Ta2 O5 ) can be grown in to an ultra-thin lm by postdeposition annealing (PDA) atmosphere [20]. In our simulation we have taken a high K dielectric with effective oxide thickness of 2 nm [10]. We have neglects the gate leakage in the calculation of tunneling current as we are using

Fig. 8 Variation of threshold voltage as a function of gate length for both the device with Nd = 2 1019 cm3 , Tox = 2 nm, Tsi = 5 nm

JLTFET have better subthreshold slope (32 mV/decade) and DIBL (49 mV/V) than a 25 nm inversion mode device (where SS = 73 mV/decade, DIBL = 98 mV/V), which illuminates the better immunity of JLTFET towards short channel effects over conventional MOSFET. Figure 8 shows the variation of threshold voltage of JLTFET and conventional MOSFET as a function of gate length, with gate length scale down from 25 nm to 10 nm at VDS = 1 V. We can see the variation in threshold voltage of MOSFET is more as compared to JLTFET. With scaling of gate length threshold voltage of IM device drops from 0.407 V at 25 nm to 0.25 V at 10 nm, whereas for JLTFET it remains insensitive to channel length scaling. The gate capacitance (which include oxide related capacitance Cox ) in MOSFET depends on the thickness of gate dielectric (Tox ). The current in MOSFET is inversely proportional to thickness of gate dielectric (Tox ), so the variation in Tox changes the ON current and subthreshold slope as well. But in JLTFET the on current mainly depends on the height and width of tunneling junction between source and channel of the region.

J Comput Electron

Fig. 10 ION /IOFF ratio and subthreshold slope as a function of gate dielectric constant (from SiO2 with K = 3.9 to TiO2 with K = 80) for JLTFET and MOSFET with gate length of 25 nm and Nd = 2 1019 cm3

Fig. 11 Effect of SS and DIBL as a function of silicon lm thickness ranging from 5 nm to 12 nm, with gate length of 25 nm

3.4 Thin lm thickness the high-K as gate dielectric [5, 6]. The further improvement in different performance parameters could be done by work function engineering, uses of IIIV compound semiconductor materials as a channel material, proper selection of source drain extension length with optimized silicon body thickness. An improvement can also be done by choosing proper isolation thickness between the gates. The effect of sub-threshold swing and ION /IOFF on the dielectric constant of gate material is studied and results are compared for both JLTFET and MOSFET as shown in Fig. 10. For our simulation we have considered different dielectric materials (such as TiO2 (k = 80), HfO2 (k = 25), Al2 O3 (k = 9), Si3 N4 (k = 7.5), SiO2 (k = 3.9)), and the dielectric constants of different materials are taken from [14]. It is observed from above gure that the material with higher dielectric constant gives a higher ON current and also an improved SS. The improved ION and SS are observed, because of a higher gate coupling offered by high-k dielectric gate material of higher dielectric constant value ranging from 3.9 to 80, keeping the physical thickness of the gate oxide xed and equal to 2 nm. The ON state current (ION ) and OFF state current (IOFF ) are measured at the supply voltages of (VDS = 1 V, VGS = 1 V) and (VDS = 1 V, VGS = 0 V), respectively. The highest ION /IOFF for JLTFET is observed at gate dielectric constant of k = 80, taking TiO2 as gate dielectric and the value is approximately 6 1011 , whereas for MOSFET with same simulation environment we observed an ION /IOFF of 4.2 1011 . Looking at the same plot we observed that with increase of gate dielectric from 3.9 to 80, the SS decreases for both the device (in case of JLTFET 27 mV/decade at k = 3.9 to 11 mV/decade at k = 80 and for MOSFET 102 mV/decade at k = 3.9 to 60 mV/decade at k = 80). However from the above results it can be concluded that, JLTFET with a low k dielectric with k = 3.9 can provide an improved SS of 37 mV/decade which is much lower than the SS of MOSFET with a high k dielectric with k = 80 (SS = 60 mV/decade). Figure 11 shows the effect of silicon lm thickness on the short channel behavior of JLTFET and MOSFET in terms of SS and drain induced barrier lowering. We observed that with increase of silicon thickness from 5 nm to 12 nm both SS and DIBL increase, but interestingly JLTFET at Tsi = 12 nm offers an improved SS and lower DIBL than MOSFET with layer thickness of 5 nm, which signies the short channel integrity and superior performance of JLTFET over conventional MOSFET. With increase of Tsi from 5 nm to 12 nm, sub-threshold swing of JLTFET increases from 24 mV/decade to 56 mV/decade (below the theoretical limit of MOSFET) and DIBL from 30 mV/V to 98 mV/V respectively. Whereas observing the same behavior of MOSFET, it can be concluded that at higher silicon thickness the MOSFET has a very poor short-channel performance as compared to JLTFET. 3.5 Effect of temperature variations Figure 12 shows the dependence of OFF state current with variation of temperature. We have studied the behavior of JLTFET and MOSFET for temperature values of 243 K, 300 K and 393 K. With increase of temperature OFF current increases to signicant amount due to shift in threshold voltages of the device. When temp rises from 300 K to 393 K there is difference in OFF current of more than two orders in magnitude is observed for MOSFET, whereas in case of JLTFET the temp rise affects the OFF current by increasing its value to one order in magnitude as shown in Fig. 12. So JLTFET has better temperature stability in nanoscale regime than conventional MOSFET. The variation of sub-threshold slope with temperature instability is shown in Fig. 13. It is clear from the picture that with increase in temperature SS increases, which degrades the switching behavior of both the devices. It can be concluded that JLTFET has better temperature stability than

J Comput Electron

ratio as compared to conventional MOSFET. The JLTFET is less sensitive to temperature variation as compared to conventional MOSFET. Moreover JLTFET would be simpler to fabricate and less prone to variability and short channel effect than conventional MOSFET. So JLTEFT can be a future device for many applications, which offers combined advantages of both TFET and JLFET without need of any sharp doping gradient.
Acknowledgement The authors thank the University of Texas at Austin, USA, and the Ministry of Human Resource and Development, Government of India, for funding this project.

Fig. 12 Comparative study of OFF state behavior of JLTFET and MOSFET with variation of device temperature with gate length of 25 nm, Tox = 2 nm, Tsi = 5 nm and Nd = 2 1019 cm3

References
1. Bhuwalka, K.K., Schulze, J., Eisele, I.: Performance enhancement of vertical tunnel eld-effect transistor with SiGe in the p+ layer. Jpn. J. Appl. Phys. 43(7A), 40734078 (2004) 2. Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling eldeffect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743745 (2007) 3. Colinge, J.-P., Lee, C.-W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Razavi, P., ONeill, B., Blake, A., White, M., Kelleher, A.-M., McCarthy, B., Murphy, R.: Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225229 (2010) 4. Lilienfeld, J.E.: Method and apparatus for controlling electric current. U.S. Patent 1 745 175, Oct. 22, 1925 5. Gundapaneni, S., Ganguly, S., Kottantharayil, A.: Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling. IEEE Electron Device Lett. 32(3), 261263 (2011) 6. Kranti, A., Yan, R., Lee, C.-W., Ferain, I., Yu, R., Dehdashti Akhavan, N., Razavi, P., Colinge, J.P.: Junctionless nanowire transistor (JNT): properties and design guidelines. In: Proceedings of the European, Solid-State Device Research Conference (ESSDERC), pp. 357360 (2010) 7. Lee, C.W., Ferain, I., Kranti, A., Dehdashti Akhavan, N., Razavi, P., Yan, R., Yu, R., ONeill, B., Blake, A., White, M., Kelleher, A.M., McCarthy, B., Gheorghe, S., Murphy, R., Colinge, J.P.: Short-channel junctionless nanowire transistors. In: Proc. SSDM, pp. 10441045 (2010) 8. Su, C.-J., Tsai, T.-I., Liou, Y.-L., Lin, Z.-M., Lin, H.-C., Chao, T.-S.: Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett. 32(4), 521523 (2011) 9. Ghosh, B., Bal, P., Mondal, P.: A junctionless tunnel eld effect transistor with low subthreshold slope. J. Comput. Electron. (2013). doi:10.1007/s10825-013-0450-2 10. Ghosh, B., Akram, M.W.: Junctionless Tunnel Field Effect Transistor. IEEE Electron Device Lett. 35(5) (2013) 11. Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high- gate dielectric. IEEE Trans. Electron Devices 54(7), 17251733 (2007) 12. Silvaco, Version 5.15.32.R. (2009). [Online]. Available http://www.silvaco.com 13. Gundapaneni, S., Bajaj, M., Pandey, R.K., Murali, K.V.R.M., Ganguly, S., Kottantharayil, A.: Effect of band-to-band tunneling on junctionless transistors. IEEE Electron Device Lett. 59(4), 10231029 (2012) 14. Lide, D.R.: CRC Handbook on Chemistry and Physics 89th edn. pp. 12114. Taylor & Francis, London (2008) 15. Hansch, W., Vogelsang, Th., Kirchner, R., Orlowski, M.: Carrier transport near the Si/SiO2 interface of a MOSFET. Solid-State Electron. 32(10), 839849 (1989)

Fig. 13 Sub-threshold slope as a function of variation of temperature ranging from 243 K to 393 K

that of conventional MOSFET. This can be demonstrated by looking at the change in SS of both the devices. (For JLTFET at temperature of 243 K, SS = 9 mV/decade is observed which further increases to 36 mV/decade with increase in device temperature to 393 K. But in case of MOSFET SS of 64 mV/decade is observed even at lower temperature of 243 K which increases to 93 mV/decade at further increases in temperature to 393 K.) So the short channel performance of JLTFET is more stable towards the temperature variation as compared to metal oxide FET.

4 Conclusion In this paper the short channel performance of both JLTFET and MOSFET are compared. By doing extensive simulations it can be concluded that in deep deca-nanometer (sub-30 nm) region JLTFET offers improved performance in terms of very low subthreshold swing and high I ON /I OFF

J Comput Electron 16. Schenk, A.: A model for the eld and temperature dependence of SRH lifetimes in silicon. Solid-State Electron. 35(11), 15851596 (1992) 17. Vandervorst, W., Brijs, B., Bender, H., Conard, O.T., Petry, J., Richard, O., Van Elshocht, S., Delabie, A., Caymax, M., De Gendt, S.: Physcial characterization of ultrathin high k dielectrics. 2002 MRS Fall Meeting 18. Seo, J.W., Dieker, Ch., Locquet, J.-P., Mavrou, G., Dimoulas, A.: HfO[sub 2] high-k dielectrics grown on (100) Ge with ultrathin passivation layers: structure and interfacial stability. Appl. Phys. Lett. 87, 221906 (2005). doi:10.1063/1.2137897 19. Zhu, J., Liu, Z.G.: Structure and dielectric properties of ultrathin ZrO2 lms for high-k gate dielectric application prepared by pulsed laser deposition. Appl. Phys. A 78(5), 741744 (2004) 20. Lu, J., Kuo, Y.: Hafnium-doped tantalum oxide high-k dielectrics with sub-2 nm equivalent oxide thickness. Appl. Phys. Lett. 87, 232906 (2005). doi:10.1063/1.2140482