Memory BIST PDF

Chapter 4: Memory Built-In Built In Self Test Self-Test
Jin Fu Li Jin-Fu Dept. of Electrical Engineering National Central University Jhongli, Taiwan
Outline
ROM BIST RAM BIST Serial BIST for RAMs Processor Processor-Based Based RAM BIST RAM BISTs in SOCs References
EE, National Central University
Jin-Fu Li
Introduction
Characteristics of todays SOC designs
Typically more than 30 embedded memories on a
chip hi Memories scattered around the device rather than concentrated in one location Different types and sizes of memories Memories doubly embedded inside embedded cores Test access to these memories from only a few chip I/O pins p
Built-in self-test (BIST) is considered the best solution for testing embedded memories within SOCs
It offers a simple and low-cost low cost means without
significantly impacting performance

Jin-Fu Li
General BIST Architecture
Test Generator
Circuit Under Test (CUT)
Response Verification
Test Controller
Jin-Fu Li
ROM Functional Block Diagram

Inputs Buffer
Decoder
NOR/NAND (ROM Array)
Buffer Outputs O t t
EE, National Central University Jin-Fu Li
An Example of ROM BIST
Counter Controller Go/No-Go Status

ROM
MISR
Typical RAM BIST Architecture

Normal I/Os
T t Controller Test C t ll
Test Collar C
Test Pattern Generator Go/No-Go Comparator
RAM
Jin-Fu Li
In general, two BIST approaches have been

proposed for the RAMs
FSM-based RAM BIST ROM-based RAM BIST Generate control signals to the test pattern
RAM BIST
Controller
Test pattern generator (TPG) Comparator

generator & the memory under test
Generate the required test patterns and Read/Write
signals g
Evaluate the response

Jin-Fu Li
The features of ROM-based BIST scheme
ROM-Based RAM BIST
The ROM stores test procedures for generating test
The BIST circuits consists of the following

functional blocks
ROM TPG Comparator
patterns Self-test is executed by using BIST circuits controlled by the microprogram ROM A wide range of test capabilities due to ROM programming p g g flexibility y
Microprogram ROM to store the test procedure Program counter which controls the microprogram
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ROM-Based RAM BIST Architecture

Normal I/Os
E d End
Mi Microprogram Test Collar ROM
RAM
TPG
Go/No-Go Comparator
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10
March-9N Test Procedure & Microcodes

M h 9N March-9N:
STEP OPERATION
CLEAR WRITE(D), INC AC, IF AC=MAX THEN INC PC READ(D) WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC READ(D) READ(D ) WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC DEC AC READ(D) WRITE(D) DEC AC WRITE(D), AC, IF AC=0 THEN INC PC ELSE DEC PC READ(D) WRITE(D), DEC AC, IF AC=0 THEN INC PC ELSE DEC PC STOP IF AC=MAX/0 ELSE DEC PC INCREMENT AC DECREMENT AC EXCLUSIVE OR INVERT/NORMAL COMPARE/MASK WRITE/READ CLEAR TEST END Jin-Fu Li
MICROCODE
0000000010 1010000100 0000000100 1110010100 0000011000 1110000100 0001000000 0000001000 1101010100 0000011000 1101000100 0000000001
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FSM-Based RAM BIST

Normal I/Os
E d End
FSM
Test Collar
RAM
TPG
Go/No-Go Comparator
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12
FSM-Based RAM BIST

A example An l of f the h state di diagram of f controller ll
W0 R0 W1 R1 W0 R0 W1 End S0 S1 S2 S3 S4 S5 S4 S4
Jin-Fu Li
NOT last address?
NOT last address?
NOT last address?
NOT last address?
13
Programmable RAM BIST

A example An l of f the h programmable bl RAM BIST
Normal I/Os CMD BSI Con ntroller BSC BRS BGO CLK BNS TGO ENA DONE T TPG & Compar C rator
Test Collar C
RAM
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14
FSM State Diagram of the Controller

Idle
BRS=1 BSC=1 DONE=1
Shift Shift_cmd d
BSC=0
Get_cmd
Apply
DONE=0
ENA=1
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15
Programmability
The programmability Th bili can b be achieved hi db by using i test command The test command format
U/D OP Data background
U/D: ascending/descending address
sequence OP: test operations
For o example, e a p e, wa, a, rawa, a a , rawara, a a a, warawara, a a a a , etc.
Data backgrounds
The width Th idth of f each h field fi ld affects ff t the th programmability of the BIST design
For F example, l if 4 bit bits are used df for OP OP, th then only l 16
possible test operations can be generated Jin-Fu Li
16
FSM State Diagram of the TPG

Idle
ENA=1 ENA=0
Init
Null=1 Null=0
DONE/GO
Ifetch Exec Dfetch No-Go

Error=1
Compare
Error=0
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17
Todays telecommunication ICs often have a Typical RAM BISTs

variety if multiport memories on one chip evaluate all the bits of a memory word in parallel as it is read
Serial BIST
We can encounter significant problems when

port configurations
unacceptably high
The area cost of these BIST designs would be
applying these BIST schemes to chips that have multiple embedded RAMs of varying sizes and
One better solution is a serial BIST technique

To T share h BIST d design i among several l RAM RAMs
Jin-Fu Li EE, National Central University
18
Benefits of Serial BIST
Only a small amount of additional circuitry is Only a few lines are needed to connect the RAM Several RAM blocks easily y share the BIST The serial serial-access access mode does not compromise Existing E i ti memory d designs i d do not t need d any
modification to use the serial interface
required
to the test controller controller hardware
the RAM cycle time
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Serial-Data-Path Connection
Row de ecoder
Ci
Ci+1
Column decoder
Latch
Latch
Write Read BIST on

From previous output or serial input To next test input or serial input
Ii
Oi
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Ii+1
Oi+1
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An example of serial shift operations for the

match element (R0W1)
0 1 0 1 1 0 0 0 0 0 0 2 3 4 0 1 0 1 X 1 0 0 0 0 0 0 0 0 0 0 X 5 6 7 8
Serial Shift Operation

Time Operation Serial in
Word content
Serial out
X R0 W1 R0 W1 R0 W1 R0 W1 X 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1
X 0 0 0 0 0 0 0 0
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Assume that a RAM has W words, and each A Read operation is denoted by R0, R1, or Rx,
word contains C bits depending on the expected value at the serial output (x=dot care) used and only the serial input is forced to the value indicated f ll follows c ( RxW 0 ) C ( R 0 , W 0 ) C ; ( R 0 , W 1) C ( R1, W 1) C
Serial March (SMarch)
For a write operation operation, the terms W0 or W1 are The SMarch modified from March C- is as
( R1, W 0 ) C ( R 0 , W 0 ) C ; ( R 0 , W 1) C ( R1, W 1) C
( R1, W 0 ) C ( R 0 , W 0 ) C ; ( R 0 , W 0 ) C ( R 0 , W 0 ) C
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Serial BIST Architecture

BIST GO Done
Counters Control Data out Data in Address Multiplexer
Controller SO
lsb
Timing SI generator
msb
C-1
Multiplexer
C C
Multiplexer
Address
Data in
Data out
Control
RAM (W words of C bits)

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Sharing BIST in Daisy-Chain Style

BIST GO Done
Counters
Controller SO SI
Timing generator g
Add Address
R d/W it Read/Write
Test Collar RAM1 Serial Interface SI


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Test Collar RAM3 Serial Interface SI SO

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SO
SO
Sharing BIST in Parallel Style

BIST GO Done
DeMux
C Counters t
SO SI Controller
Timing g generator
Read/Write
Address


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Test Collar RAM3 Serial Interface SI SO

25
SO
SO
BIST Using Data Decoding/Encoding
n m wire n
n e m wire
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Processor-Based RAM BIST

Normal I/Os
Processor
Test Collar
RAM
TPG
Go/No-Go Comparator
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NTHU Processor-Programmable BIST

ADDR_cpu ADDR_bist DATAO DATAO_sys DATAO_bist
ADDR
DATAO
Mux_sel
Embedded CPU
Clock_cpu
BIST core
On-chip bus
Embedded Memory
Ctrl_cpu
Ctrl_bist
control
DATAI_cpu
DATAI_bist
DATAI_sys
DATAI
Source: Prof. C. W. Wu, NTHU
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BIST core
DATAO_bist RBG RAL L Lowest/highest t/hi h t addr dd REA RFLAG RED Controller Address counter ADDR_bist
DATAO_cpu
ADDR_cpu Address
decorder
RAH RME RIR
Up/down Read/Write Control
DATAI_bist
Match/unmatch DATAI sys DATAI_sys
Comparator Data background

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Data registers
Register RBG RAL RAH RME RIR RFLAG RED REA Function Store background data Store lowest address Store highest address Store current March element Instruction register of BIST circuit Status register of BIST circuit Erroneous response of defective cell Address of defective cell
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BIST procedure
Test program write data background to RBG Test program write lowest/highest address to RAL/RAH
Performed by test program
Test program write March instructions to RME Test program write START to RIR
(Wa)
(Ra,Wa)
(Ra,Wa)
(Ra,Wa)
(Ra,Wa)
(Ra)
Performed by BIST circuit No
Compare Data error
yes
No
March element complete
Write ERROR to RFLAG Write error response to RED Write faulty addr to REA
yes Write FINISH to RFLAG

Test program take over 31
SOC Testing
A typical SOC chip

ADC FPGA Wrapper CPU UDL DSP Sink Source Test Access Mechanism (TAM) TAM y Flash Memory
MPEG
SRAM
SRAM
DRAM
Source: Y. Zorian, et al.-ITC98
Jin-Fu Li
32
SOC Test Access

ADC FPGA
Wrapper
Flash Memory
Off-chip Source/Sink
1. Pins determine bandwidth 2. More TAM area 3. Requires expensive ATE
CPU
UDL TAM
DSP Sink TAM DRAM
Source MPEG
SRAM
SRAM
ADC
FPGA
Wrapper
Flash Memory
On chip Source/Sink On-chip

1. Close to Core-under-test 2 Less TAM area 2. 3. BIST IP area 4. Requires lightweight ATE
CPU
UDL
DSP
Sink
Sink
Source MPEG
Source
SRAM
SRAM
DRAM
Source: Y. Zorian and E.J. Marinissen

Jin-Fu Li
33
1500 Scalable Test Architecture

Source TAM-in User Defined Parallel TAM TAM-out TAM-in TAM-out Sink
1500 Wrapper W Fin
1500 Wrapper W Fout Fin
Core1
WIR
CoreN
WIR
Fout
WSI
WSO WIP
WSI
WSO
User-Defined Test Controller
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34
1500 Test Wrapper
Test stimuli Functional data
WPI W WBR W WBR Core
WPO Test response Functional data
WBY WSI WIR WSC WSO
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35
Memories in SOCs
ADC FPGA Flash Memory CPU UDL DSP
DRAM SRAM SRAM BIST DRAM BIST SRAM BIST
MPEG
SRAM BIST
SRAM
N BIST memory cores Non-BIST

BIST BIST-ready d memory cores

Jin-Fu Li
36
Memory cores in an SOC can be categorized

into two types in term of testability
BIST-ready memory cores Non-BIST memory cores
RAM BIST in SOCs
An SOC can contain tens or even hundreds of

memory e o y cores co es
Although a BIST usually have only about 8
The BIST controlling pins should be shared

One solution is using g memory y BIST interface
controlling pins The total BIST controlling pins is huge if each BISTready memory cores has its own BIST controlling pins
37
Sharing BIST Controlling Pins

ADC FPGA Flash Memory CPU UDL DSP DRAM SRAM SRAM BIST
MBI MBI
SRAM
BIST
MBI MBI
BIST SRAM DRAM
MPEG
BIST SRAM
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Memory BIST Interface (MBI)
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Instruction Register Bypass yp Register g

tested
Memory BIST Interface (MBI)
Store the instructions
RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL
It is selected if the corresponding memory core is not
Monitor Register Status Register

the BIST
Monitor o to the t e error e o flag ag ( (indicating d cat g whether et e a memory e oy
fault is detected or not)
Record the key status values, such as Fail output from
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40
Testing Multiple Memories with MBI
Using RUN_BIST instruction, we can test multiple memory cores concurrently

When one or more BIST circuits detect faults, the primary
MSO_N will be high after N-K clock cycles if the concurrent output of the (K+1) through the N memory cores are fault free
Jin-Fu Li
41
Sharing BIST Hardware

BIST controlling signals TPG & BIST Controller Comparator
ll BIST C Collar RAM 1
BIST C Collar ll RAM 2
ll BIST C Collar RAM N
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RAM BIST Compiler
S Source: P Prof. f C. C W W. Wu, W NTHU

43
1500-Compilant BIST
T TAP Con ntroller
Wrapper
TAP P
BIST
RAM
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44
Programmable BISD for RAMs in SOCs

General test architecture ATE SOC
Wrapper Processor + Test Program Memory TAP controller
TAM
Embedded Memory Core
S Source: A Appello ll D D., et. al. l ITC03

45

Test Processor
Processor
Wrapper P1500 Instructions
Control Unit
Test Program
P1500 Output Data
Memory Adapter
Address Bus Data Bus g Control Signals
S Source: A Appello ll D D., et. al. l ITC03

46
Control Unit

Manage the test program execution Include an Instruction Register (IR) and
Program Counter (PC) The control unit allows the correct update of some registers located in Memory Adapter This part simplifies the processor reuse in different applications without the need for any re-design
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Memory Adapter
Control Address registers g (Current ( _address) ) Control Memory registers
Current_data Received_data R i d d t
Control Test registers Result registers
Dbg g_index, , Step, p, Direction flag, g, and Timer registers g Status, Error, and Result registers Add_Max, Add_Min, DataBackGround, Dbg_max
Some constant value registers
Jin-Fu Li
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Processor instruction set

I t ti Instruction
SET_ADD RST_ADD STORE_DBG INV_DBG READ WRITE
M Meaning i
Current_address Add_Max Direction flag BACKWARD Current_address Add_Min g FORWARD Direction flag Current_data DataBackGround[Dbg_index] Dbg_index Dbg_index+1 Current_data NOT (Current_data) Current data Memory[Current_address] Current_data Memory[Current address] Memory[Current_address] Current_data
Source: Appello D., et. al. ITC03
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Wrapper
WSI
WRCK WRSTN ShiftWR UpdateWR CaptureWR SelectWIR
W I R W B Y
W D R
W C D R
TAP controller c
Processor
W B R
Me emory
CORE
Test Program
WSO
Wrapper Source: Appello D., et. al. ITC03

Jin-Fu Li
50
Summary
ROM BIST has been presented p ROM-based and FSM-based RAM BIST have Serial BIST methodology for embedded BIST approaches pp for testing g multiple p RAMs in an
SOC have also been addressed memories i h has also l presented t d been introduced
Jin-Fu Li
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[1] A. K. Sharma,Semiconductor memories technology, testing, and reliability, li bilit IEEE P Press, 1997 1997. [2] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal,Serial interfacing for embedded-memory testing, IEEE D&T, pp.52-63, apr. 1990. [3] C. W. Wu,VLSI testing & design for testability II: Memory built-in selftest, http://larc.ee.nthu.edu.tw/~cww/ [4]C. H. Tsai and C.-W. [4]C.-H. C. W. Wu, ``Processor-programmable Processor programmable memory BIST for bus-connected embedded memories'', in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 325-330 [5]C.-W [5]C W. Wang, Wang C C.-F F. Wu, Wu J J.-F F. Li, Li C C.-W W. Wu, Wu T T. Teng, Teng K K. Chiu, Chiu and H. H -P P. Lin Lin, ``A A built-in self-test and self-diagnosis scheme for embedded SRAM'', in Proc. 9th IEEE Asian Test Symp. (ATS),Taipei, Dec. 2000, pp. 45-50 [6]D. Appello, [6]D Appello F F. Corno Corno, M. M Giovinetto, Giovinetto M M. Rebaudengo Rebaudengo, and M M. S S. Reorda Reorda,A A P1500 compliant BIST-Based approach ro embedded RAM diagnosis, pp.97-102, MTDT, 2001. [7]J. F [7]J F. Li Li, H H. J J. H Huang, J J. B B. Ch Chen, C. C P. P Su, S C. C W. W Wu, W C. C Cheng, Ch S. S I. I Chen, Ch C. C Y. Y Hwang, and H. P. Lin,A hierarchical test methodology for systems on chip, IEEE Micro, pp. 69-81, Sep./Oct., 2002. [8]S. Mourad and Y. Zorian,Principles of f Testing Electronic Systems, John Wiley & Sons, 2000.
Jin-Fu Li
References
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Chapter 4: Memory Built-In Built In Self Test Self-Test

EE, National Central University

significantly impacting performance

EE, National Central University

General BIST Architecture

Circuit Under Test (CUT)

EE, National Central University

ROM Functional Block Diagram

NOR/NAND (ROM Array)

An Example of ROM BIST

Counter Controller Go/No-Go Status

Typical RAM BIST Architecture

Test Pattern Generator Go/No-Go Comparator

EE, National Central University

In general, two BIST approaches have been

Test pattern generator (TPG) Comparator

generator & the memory under test

Generate the required test patterns and Read/Write

Evaluate the response

The features of ROM-based BIST scheme

ROM-Based RAM BIST

The ROM stores test procedures for generating test

The BIST circuits consists of the following

ROM-Based RAM BIST Architecture

Mi Microprogram Test Collar ROM

EE, National Central University

March-9N Test Procedure & Microcodes

EE, National Central University

FSM-Based RAM BIST

EE, National Central University

FSM-Based RAM BIST

NOT last address?

NOT last address?

NOT last address?

NOT last address?

EE, National Central University

Programmable RAM BIST

EE, National Central University

FSM State Diagram of the Controller

EE, National Central University

U/D OP Data background

U/D: ascending/descending address

sequence OP: test operations

For o example, e a p e, wa, a, rawa, a a , rawara, a a a, warawara, a a a a , etc.

EE, National Central University

possible test operations can be generated Jin-Fu Li

FSM State Diagram of the TPG

Ifetch Exec Dfetch No-Go

EE, National Central University

Todays telecommunication ICs often have a Typical RAM BISTs

We can encounter significant problems when

One better solution is a serial BIST technique

Benefits of Serial BIST

to the test controller controller hardware

the RAM cycle time

Write Read BIST on

An example of serial shift operations for the

Serial Shift Operation

Serial March (SMarch)

Serial BIST Architecture

Counters Control Data out Data in Address Multiplexer

RAM (W words of C bits)