Plan of Altera Labs

Contents
STT 1 2 3 4 5 6 7 Task Name Lab1 Lab2 Lab3 Lab4 +Lab5 Lab6 Lab7 Lab8 Duration 7 days 7 days 7 days 7 days 14 days 14 days 7 days Start Sat 2/3/13 Sat 9/3/13 Sat 16/3/13 Sat 23/3/13 Sat 30/3/13 Sat 13/4/13 Sat 27/4/13 Finish Fri 8/3/13 Fri 15/3/13 Fri 22/3/13 Fri 29/3/13 Fri 12/4/13 Fri 26/4/13 Fri 3/5/13

Lab 1: Switches, Lights, and Multiplexers

( 1 week) The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these devices. Final goal: Your circuit should be able to display words with three (or fewer) characters on the four displays, and rotate the displayed word when the defined switches are toggled. Steps: 1. Install and learn to use Quartus II 10.1 Web Edition (Any others version is accepted, but this version is recommended) 2. Watch video Quartus 10.1 for beginner at here 3. Do the part_1part_3 in lab_1: Switches and Mux 4. Learn to write a test-bench file at here and how to use ModelSim to simulate the circuit (link here) 5. Do the part_6 in lab_1: rotating characters on 7-segments LEDs

Lab 2: Numbers and Displays

(1 week) This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion and binary-coded-decimal (BCD) addition. Final goal: An Adder of BCD numbers Steps: 1. Part_2: Convert a 4-bit number from BIN to BCD format 2. Part_6: Design a circuit that converts a 6-bit binary number into a 2-digit BCD number 3. Part_4: Design an adder of BCD numbers

Lab 3: Latches, Flip-ops, and Registers

(1 week) Final goal: Display two numbers on different HEXs with only one port to input numbers value, that means using register to store value of first number. Steps: 1. Part_2: D-Flip flops 2. Part_3: Master and Slave Filp flops 3. Part_5: Flip flops and MUX

Lab 4: Counters
(1 week) Final goal: An 1-Hz clock from frequency divider to tick a banner rotating. Steps: 1. Part_1: Synchronous Counter using T-Flip Flops 2. Part_4: Design a frequency divider ( using counter in part_1) to divide 50-Mhz input clock into 1Hz output clock 3. Part_5: Control circuit designed in part_6_lab_1 by using 1Hz clock instead of SWes.

Lab 5: Clocks and Timers

(optional) Final goal: A real-time clock Steps: 1. Design a seconds counter 2. Design a hours counter 3. Using part_2_lab_2 to display value of above counters

Lab 6: Adders, Subtractor, and Multipliers

(2 week) Final goal: The purpose of this exercise is to examine arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: rst by writing VHDL code that describes the required function-ality, and second by making use of predened subcircuits from Alteras library of parameterized modules (LPMs). Steps: 1. Part_3 in lab_2: ripple-carry adder 2. All parts in lab_6 using LPM functions library

Lab 7: Finite State Machines

(2 week) Final goal: Control data using some state of machine, depends on previous state and current inputs Steps: 1. 2. 3. 4. 5. 6. Part_1: One-hot codes for the FSM Part_2: Use some standard rule to build a FSM system Part_4: A counter using FSM Part_5: A register using FSM Part_6: A ticker banner with FSM which automatically rotate when it is hit by 1Hz clock Part_7: Control the rate of rotation using FSM

Lab 8: Memory Blocks

(1 week) Final goal: connecting external memory chips to the FPGA Steps: 1. 2. 3. 4. 5. 6. Part_1: RAM_1port in LPM library Part_2: Read and write data in RAM block Part_3: RAM structure in VHDL, user defined RAM block Part_4: Control SRAM chip on DE1 board Part_5: Dual-port RAM in LPM library Part_7: M4K Memory Block in FPGA

Tools
Quartus 10.1 web edition ModelSim 6.6c ( is part of Quartus II 10.1) Link: ftp://ftp.altera.com/outgoing/release/

Books
http://www.mediafire.com/?xdcvvv1uoa54s