TCM8230MD (A) Ver. 1.

20 TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

TCM8230MD (A)
TENTATIVE

VGA CAMERA MODULE

The TCM8230MD(A) is a camera module which includes area color image sensor embedded with camera signal processor that meets with VGA format. In the sensor area 492 vertical and 660 horizontal signal pixels, and the image size meets with 1/6 inch optical Format. Use of the CMOS process enables low power consumption operations. It also provides excellent color reproduction through its primary color filter, and embedded camera signal processor enables small and simple camera system. And this module can be assembled by the socket which is suitable for the reflow soldering. So it is fit to use as an image input device for digital still cameras, PC cameras and mobile devices.

Features
1. General

Module size : 6(W) x 6(D) x 4.5(H) mm 2 I C BUS I/F 2 Sleep mode operation (It can be controlled by the I C Bus command) Power supply : 2.8+/-0.2V or 2.5+/-0.2V (Sensor(photo diode), I/O) and 1.5+/-0.1V(Sensor(A/D converter), Digital)

2. Sensor
Optical size : 1/6 inch optical format Total pixel numbers : 698(H)x502(V) Signal pixel numbers : 660(H)x492(V) Pixel pitch : 3.75um(H)x3.75um(V) (square pixel) Color filter : RGB color filter, Bayer arrangement (GR line and GB line are arranged alternately.) Frame rate : Max 30fps Raw data bit precision : 10bit Feed back clamp

3. Camera signal processing

Maximum exposure time can be adjust from 1V to 15V Digital outputs YUV=4:2:2 or RGB=5:6:5 ( 8bit parallel output ) Picture size VGA, QVGA, QQVGA, CIF, QCIF, subQCIF ( Sub-sampling , Windowing ) Readout internal parameters Sensor gain setting, Electrical shutter exposure period, ALC and AWB reference value Auto electrical shutter control (AES), auto gain control (AGC) and auto white balance (AWB) circuit Flickerless auto luminance control (ALC=AES+AGC) and auto flicker detection circuit for AC 50Hz / 60Hz fluorescent light Automatically blemish correction Vertical and Horizontal flip mode

TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or jail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating range as set forth in the most recent products speci f ications. Also, please keep in mind the precautions and conditions setf orth in the TOSHIBA Semiconductor Reliability Handbook. The products described in this document are subject to f oreign exchange and f oreign trade control laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights o f TOSHIBA CORPORATION or others. The inf ormation contained herein is subject to change without notice.

04/01/05

1/27

TCM8230MD (A) Ver. 1.20

UPDATE INFORMATION
Ver. 1.20 Ver. 1.10 Ver. 1.09 Ver. 1.08 Ver. 1.07 Ver. 1.06 Ver. 1.05 Ver. 1.04 Ver. 1.03 Ver. 1.02 Ver. 1.01 Ver. 1.00 Jan-05, 2004 Dec-23, 2003 Dec-16, 2003 Oct-29, 2003 Oct-07, 2003 Sep-19, 2003 Sep-08, 2003 Aug-11, 2003 Jul-31, 2003 Jul-16, 2003 Jul-03, 2003 Jun-25, 2003

04/01/05

2/27

TCM8230MD (A) Ver. 1.20

BLOCK DIAGRAM

TCM8230MD
Double Lens VGA CMOS Sensor

CDS / AGC

ADC Signal Processing

Image Area

TG / SG

AWB

ALC

I2C bus I/F

Connecting terminals

PVDD IOVSS IOVDD (2.8V)

SDA SCL

HD DVSS DOUT0 RESET DVDD AVSS to VD EXTCLK (1.5V) DOUT7 DCLK

Host system
CDS : Correlated Double Sampling AGC : Automatic Gain Control ADC : Analog to Degital Converter TG : Timing pulse Generator SG : Sync pulse Generator AWB : Auto White Balance ALC : Auto Luminance Control

04/01/05

3/27

TCM8230MD (A) Ver. 1.20

PIN LAYOUT

5
SDA

4
SCL

3
RESET

2
EXTCLK

1
PVDD

DVDD

DOUT7

20

DVSS

TCM8230MD
TOP (Lens side) view

DOUT6

19

VD

DOUT5

18

HD Orientation

DOUT4

17

10

DCLK DOUT0 DOUT1 DOUT2 DOUT3 IOVSS

IOVDD

16

11

12

13

14

15

04/01/05

4/27

TCM8230MD (A) Ver. 1.20

PIN FUNCTIONS

No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

NAME PVDD EXTCLK RESET SCL SDA DVDD DVSS VD HD DCLK DOUT0 DOUT1 DOUT2 DOUT3 IOVSS IOVDD DOUT4 DOUT5 DOUT6 DOUT7

I/O I I I I/O O O O O O O O O O O O

FUNCTION VDD for sensor (photo diode) ( 2.8V ) Clock for external input RESET terminal ("L" active) Clock for I2C-bus command Data for I2C-bus command VDD for digital circuits, (1.5V ) VDD for sensor (A/D converter) (1.5V ) GND for digital circuits GND for sensor (A/D converter) GND for sensor (photo diode) Vertical syncronization pulse output Holizontal syncronization pulse output Clock for output data Data output (LSB) Data output Data output Data output GND for I/O VDD for I/O ( 2.8V ) Data output Data output Data output Data output (MSB)

04/01/05

5/27

TCM8230MD (A) Ver. 1.20

INTERFACE CIRCUITS
PIN No. NAME I/O INTERFACE CIRCUIT
IOVDD IOVDD IOVDD

EXTCLK

I
GND GND
IOVDD

GND

GND

IOVDD

IOVDD

IOVDD

RESET ("L" active)

GND

I
GND

GND

IOVDD

SCL

I
GND

GND

IOVDD

SDA

I/O
GND

GND

GND

IOVDD

IOVDD

8-14, 17-20

DOUT0 to DOUT7, HD, VD, DCLK

GND

GND

04/01/05

6/27

TCM8230MD (A) Ver. 1.20

PIXEL ARRANGEMENT
1. V_INV=0
Dummy pixels OB 44pixels Signal pixels660pixels Light shielded pixels 2pixels

B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R 492 491 490 489 488 487 B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R

B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R

6 5 4 3 2 1 B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R

655

656

657

658

659

Start pixel

Horizontal

OB: Optical Black

R: Red pixels

Gr,Gb: Green pixels

B: Blue pixels

2. V_INV =1 (Vertical flip mode)

Start pixel Dummy pixels OB 44pixels Signal pixels660pixels Light shielded pixels 2pixels

1 2 3 4 5 6

B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R

B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R

660

487 488 489 490 491 492 B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R B Gb B Gb B Gb B Gb B Gb Gr R Gr R Gr R Gr R Gr R

655

656

657

658

659

Horizontal

OB: Optical Black

R: Red pixels

Gr,Gb: Green pixels

B: Blue pixels

04/01/05

660

7/27

Signal pixels494pixels

Vertical

Signal pixels494pixels

Vertical

TCM8230MD (A) Ver. 1.20

CONTROL I/F
TCM8230MD(A) control interface configuration is based on fast mode I2C bus. Register setting can be changed via I2C bus. All register settings are able to read via I2C bus.

Write mode
S Slave Address MSB 7bit 0 A Sub Address 8bit A Data 1 8bit A Data n 8bit A P

Read mode
S Slave Address MSB 7bit : Host Command : TCM8230MD(A) 0 A Sub Address 8bit S P A A S Slave Address MSB 7bit : Start condition : End condition : Acknowledge 1 Data 1 8bit A Data n 8bit A P

Start condition, End condition

Bit Transfer

SDA

SDA

SCL

S Start condition

P End conditon

SCL

data line stable ; data valid

change of data allowed

Acknowledge
SDA from trancemitter HiZ

Slave address
A6 A5 A4 A3 A2 A1 A0 R/W 0 1 1 1 1 0 0 1/0

SDA from reciver

HiZ

* TCM8230MD(A) use 7bit Slave address

SCL from master

Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

04/01/05

8/27

TCM8230MD (A) Ver. 1.20

INTERNAL REGISTER
DEC ADDRESS BIN 0 00000000 1 00000001 2 00000010 fast HEX 00 01 02
BIT7(MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1

last

default(ROM data) 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0

BIT0(LSB) B7B6B5B4 B3B2B1B0 HEX

Test Mode FPS

0:30fps 1:15fps

70 10 40

ACF
0:50Hz 1:60Hz

DCLKP
0 : normal 1: reverse

ACFDET
1 1 0 0 0 : AUTO 1: MANUAL 0 0 0 0

DOUTSW DATAHZ 3 00000011 03

0:ON 1:0FF 0:OUT 1:Hi-Z

PICSIZ[3:0] 0h:VGA 1h:QVGA(f) 2h:QVGA(z) PICFMT 3h:QQVGA(f) 4h:QQVGA(z) 5h:CIF(f) 0:YUV422 6h:QCIF(f) 7h:QCIF(z) 8h:subQCIF(f) 1:RGB565 9h:subQCIF(z) ESRLSW[1:0] 0h : Short 1h : 2h & 3h : Long V_LENGTH[3:0]

CM
0:COLOR 1:B/W 1 0 0 0 0 0 0 0

80

V_INV 4 00000100 04
0:normal 1:invert

H_INV
0:normal 1:invert

0 0 0 0

1 1 1 1

0F 02 0D C0 38 40 00 40 40 00 2F 04 22 9A 0C 0A 08 38 38 01 27 04 20 46 9E 83 68 00

ALCSW 5 00000101 6 00000110 7 00000111 05 06 07 ESRLIM[1:0] 0:AUTO 1:MANUAL ESRSPD[7:0] AG[7:0] ALCMODE[1:0] 8 00001000 08
0h:Centaer Weight 1h:Average 2h:Center only 3h:Backlight

ESRSPD[12:8]

0 0 0 0 0 0 0 0

0 0 1 0 1 1 0 1

1 1 0 0 0 0 0 0

ALCH[3:0]

0 0 1 1

1 0 0 0

9 00001001 10 00001010 11 00001011 12 00001100 13 00001101 14 00001110 15 00001111 16 00010000 17 00010001 18 00010010 19 00010011 20 00010100 21 00010101 22 00010110 23 00010111 24 00011000 25 00011001 26 00011010

09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A

ALCL[7:0] AWBSW
0:AUTO 1:MANUAL

0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 0 0
0 0 0 0

MRG[7:0] MBG[7:0] GAMSW

0:ON 1:OFF

0 0 0 0 0 0 0 0
1 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0

HDTG[7:0] VDTG[7:0] HDTCORE[3:0] CONT[7:0] BRIGHT[7:0] VHUE[6:0] UHUE[6:0] VGAIN[5:0] UGAIN[5:0]

VDTCORE[3:0]

0 0 1 0 1 0 0 1

0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0
0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1

UVCORE[3:0] SATU[6:0] MHMODE MHLPFSE 0: L 0: YMODE[1:0]

1: 1: LENS[5:0]

0 0 0 0 0 0 1 0

MIXHG[2:0]

0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0

LENSRPO L 0:Gain 27 00011011 1B AGLIM[2:0] ES100S[7:0] ES120S[7:0] D_MASK[1:0]

SLEEPSW 0:ACTIVE 1:SLEEP

up 1:Gain down

LENSRGAIN[3:0]

0 1 0 0 0 1 1 0

28 00011100 29 00011101 30 00011110

1C 1D 1E

1 0 0 1 1 0 0 0 CODESW 0:OFF 1:OUT CODESEL HSYNCSEL TESPIC 0 : original 0 : normal 0:Not out 1 : ITU656 1 : 1:Out PICSEL[1:0] 0h:Colorbar1h:Ramp1 2h :Ramp2

1 1 1 0 0 0 1 1

0 1 1 0 1 0 0 0

SRST
0:OFF 1:reset

31 00011111

1F

0 0 0 0 0 0 0 0

The registers of gray mesh (unassigned registers) are not defined. Input data of the registers of gray mesh must input 0. The registers of testmode must input default data.

04/01/05

9/27

TCM8230MD (A) Ver. 1.20

DEC

ADDRESS BIN

fast HEX 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E
BIT7(MSB) HNUM[7:0] HPPH[7:0] VRRPH[6:0] HPPH[8] HDSPPH[7:0] HDSPPH[8] VDSPPH[6:0] HAPRPH[7:0]
HAPRPH[8]

last
BIT6 BIT5 BIT4 BIT3 BIT2 BIT1

default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 1

BIT0(LSB) B7B6B5B4 B3B2B1B0 HEX

32 00100000 33 00100001 34 00100010 35 00100011 36 00100100 37 00100101 38 00100110 39 00100111 40 00101000 41 00101001 42 00101010 43 00101011 44 00101100 45 00101101 46 00101110

HOUTPH[7:0] HOUTPH[8] FSSTBSW 0 : NOT OUT 1 : OUT VOUTPH[6:0] FSSTBPOL 0 : normal 1 : invert

00 01 26 40 27 5F 00 16 23 08 08 04 00 00 00 00 00

FSSTBPH[3:0] FSSTBW[3:0]
SCMD[19:16]

0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCMD[15:8] SCMD[7:0]
TCSB1L 0: 1: TCRAMS 0: 1: TCPEROSW [2:0] TSPCHK TCPERAGC TALCRST 0: 1: TGAMROM 0: 1: TALCOSW[2:0] ESROUT [14:8] ESROUT [7:0] AGOUT[7:0] DGOUT[5:0] ALCDATA[7:0] AWBRYDA[7:0] AWBBYDA[7:0] TCSBIN 0: 1: TWBS TCRAM 0: 1: TWBG TROM[1:0]

0 0 0 0 0 0 0 0

47 00101111

2F

TACDET[1:0]

0 0 0 0 0 0 0 0

48 00110000

30
TALCDISP

TCSB[3:0]

0 0 0 0 0 0 0 0

49 00110001 50 00110010 51 00110011 52 00110100 53 00110101 54 00110110 55 00110111 56 00111000 57 00111001 58 00111010 59 00111011 60 00111100 61 00111101

31 32 33 34 35 36 37 38 39 3A 3B 3C 3D

0: 1:

PBDISP[1:0]

TDISP[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00 00 00 00 00 00 00 00 8C CF 80 00 17 85 C0

AGSLOW1[1:0]
DETSEL[3:0]

FLLSMODE[1:0] DG[5:0]

FLLSLIM[3:0] ACDETNC[3:0]

1 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AGSLOW2[1:0]

62 00111110 63 00111111

3E 3F

REJHLEV[7:0] FPSLNKS ALCLOCK W ALCSPD[1:0] 0: 0: 1: 1: SHESRSW ESLIMSEL 0:Disable 0: SHESRSPD[1:0] 1:Enable 1: AGMIN[7:0]

ALCSTEP[1:0]

REJH[1:0]

0 0 0 1 0 1 1 1

ELSTEP[1:0]

ELSTART [1:0]

1 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0

The registers of gray mesh (unassigned registers) are not defined. Input data of the registers of gray mesh must input 0. The registers of testmode must input default data.

04/01/05

10/27

TCM8230MD (A) Ver. 1.20

ADDRESS BIN 0100000 0 fast HEX 40
BIT7(MSB) LI1POL 0: 1: JAMP 0: 1: BIT6 CS1POL 0: 1: JAMG[6:0] BIT5 LI3POL 0: 1: BIT4 CS3POL 0: 1: BIT3 BIT2 BIT1

last DINCKSW
0: 1: 0 0 0 0

default

DEC 64

BIT0(LSB) B7B6B5B4 B3B2B1B0 HEX 0 0 0 0

00 00 00 00 15 1F 00 44 44 20 45 66 30 E0 20 09 07 2F 02 00 2B 60 40 06 22 23 08 04 08 08 08

65 01000001

41

0 0 0 0

0 0 0 0

66 01000010

42

PREGRG[5:0]

0 0 0 0 0 0 0 0

67 01000011

43

PREGBG[5:0]

0 0 0 0 0 0 0 0

68 01000100

44

PRERG[5:0]

0 0 0 1 0 1 0 1

69 01000101

45

PREBG[5:0]

0 0 0 1 1 1 1 1

70 01000110 71 01000111 72 01001000 73 01001001 74 01001010

46 47 48 49 4A
MSKBR[6:0] MSKGR[6:0] MSKRB[6:0] MSKGB[6:0]

0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0

0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1

75 01001011 76 01001100 77 01001101

4B 4C 4D
HDTCSW 0: 1: HDTPSW 0: 1: LI12POL 0: 1: YLCUTLMS K 0: 1: YLCUTHM SK 0: 1:

MSKRG[6:0] MSKBG[6:0] VDTCSW 0: 1: VDTPSW 0: 1: CS12POL 0: 1: DTCYLV[5:0]

0 1 1 0 0 0 1 1

0 1 1 0 0 0 0 0

1 1 1 0 0 0 0 0

78 01001110

4E

DTCGAIN[5:0] DTLLIMSW DTLYLIM [3:0] 0: 1: YLCUTL[5:0]

0 0 1 0 0 0 0 0

79 01001111

4F

0 0 0 0 1 0 0 1

80 01010000

50

0 0 0 0 0 1 1 1

81 01010001 82 01010010 83 01010011 84 01010100 85 01010101 86 01010110 87 01010111 88 01011000

51 52 53 54 55 56 57 58

YLCUTH[5:0] UVSKNC[6:0] UVLJ[6:0]

0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 0 0 0 0 0
WBNOLJS WB2IM1 0: 0: C 1: 1:

WBGMIN[7:0] WBGMAX[7:0] AWBCSPO WBDIVCLP LE WBNOLJ[1:0] 0: 0: 1: 1: ALLAREA 0: 1: WBLOCK 0: 1: PBRDSW

WBSPDUP[1:0]

0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0
0 0 1 0 0 0 1 0

WBDIVSC[2:0]
WB2SP [3:0]

KIZUSW 89 01011001 90 01011010 91 01011011 92 01011100 93 01011101 94 01011110 59 5A 5B 5C 5D 5E

PBDLV[7:0] PBC1LV[7:0] PBC2LV[7:0] PBC3LV[7:0] PBC4LV[7:0] 0:OFF 1:ON

ABCSW[1:0]

0 0 1 0 0 0 0 0 0 0 0 0

0 0 1 1 1 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

The registers of gray mesh (unassigned registers) are not defined. Input data of the registers of gray mesh must input 0. The registers of testmode must input default data.

04/01/05

11/27

TCM8230MD (A) Ver. 1.20

OUTLINE OF INTERNAL REGISTER

* Frame rate setting (30fps, 15fps ) * Picture size setting of digital output ( VGA, QVGA, QQVGA, CIF, QCIF, subQCIF ) * Selection of digital data output format (8bit YUV422, RGB565) * Sync. code setting ( ON/OFF, 2 mode ) * Color signal adjustment ( Masking, color axis correction, saturation, etc. ) * Luminance signal adjustment ( Contrast, Brightness, Gamma, H,V edge enhancement ) * ALC ON/OFF * ALC mode setting ( area selection, speed selection, flicker reduction mode setting ) * AWB ON/OFF * Vertical and Horizontal flip * Sleep mode setting * Some kinds of correction setting ( Lens shading correction etc. )

8bit parallel image data

DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 1st U0(n) U1(n) U2(n) U3(n) U4(n) U5(n) U6(n) U7(n) YUV mode 2nd 3rd Y0(n) V0(n) Y1(n) V1(n) Y2(n) V2(n) Y3(n) V3(n) Y4(n) V4(n) Y5(n) V5(n) Y6(n) V6(n) Y7(n) V7(n) 4th Y0(n+1) Y1(n+1) Y2(n+1) Y3(n+1) Y4(n+1) Y5(n+1) Y6(n+1) Y7(n+1) RGB mode 1st 2nd B0 G3 B1 G4 B2 G5 B3 R0 B4 R1 G0 R2 G1 R3 G2 R4

Image size format

Image size Display mode VGA QVGA QQVGA CIF QCIF subQCIF Full Full Zoom x 2 Full Zoom x 2 Full Full Zoom x 2 Full Zoom x 2 Pixels per H 640 320 160 352 176 128 Effective H lines 480 240 120 288 144 96 Start point (H, V) (1, 1) (1, 1) (161, 121) (1, 1) (161, 121) (21, 1) (21, 1) (173, 121) (1, 1) (161, 121) End point (H, V) (640 ,480) (639, 479) (480 ,360) (637, 477) (479, 359) (608, 478) (608, 478) (466, 360) (636, 476) (479, 359) DCLK mode 1 1/2 1 1/2 1 1/2 1 1/2 Operation mode Normal Low power Normal Low power Normal Low power Normal Low Power Resizing method Sub-sampling from VGA Windowing from VGA Sub-sampling from QVGA(f) Sub-sampling from VGA 3/5 filtering from VGA 3/5 filtering from QVGA(f) Windowing from CIF 4/5 filtering from QQVGA(f) 1st: 3/5 filtering from QVGA(f) 2nd: Sub-sampling from "1st"

QVGA(f) means QVGA full. QQVGA(f) means QVGA full. VGA QVGA QQVGA CIF QCIF Video Graphics Array Quarter VGA Quarter QVGA Common Intermediate Format Quarter CIF

04/01/05

12/27

TCM8230MD (A) Ver. 1.20

SYNCHRONIZATION CODE
Synchronization code output format
CODESW=1
DCLK DOUT70 FFh 00h 00h Code

CODESW(Address=1Eh, Bit5) is able to add synchronization codes. Code part is changed Mode1 or Mode2 by CODESEL(Address=1Eh, Bit4).

Mode1 Original format, CODESEL=0 These codes only exists in active lines
Frame Start Code Active Line 1 Line End Code Line Start Code Active Line 2 Line End Code Line Start Code
Active Line 480 (VGA)

Frame End Code

Code

Picture

Code

02 00 00 00

Blanking Blanking Line 1 Line 2 Line 3 Line 4

01 01 01 01

00
Line 480 (VGA) Line 240 (QVGA) Line 120 (QQVGA) Line 288 (CIF) Line 144 (QCIF) Line 96 (subQCIF)

01

00

03

Blanking Blanking

640 pixels (VGA) 320 pixels (QVGA) 160 pixels (QQVGA) 352 pixels (CIF) 176 pixels (QCIF) 128 pixels (subQCIF)

Line start code : FFh 00h 00h 00h Line end code : FFh 00h 00h 01h Frame start code : FFh 00h 00h 02h Frame end code : FFh 00h 00h 03h

04/01/05

13/27

TCM8230MD (A) Ver. 1.20

Mode2 (ITU656 format, CODESEL=1) These codes exists in every lines

Code

V : 1:Blanking

0:Active Line 0:Start of Active Pixel

H : 1:End of Active Pixel

Code

Picture

Code

A0 A0 80 80 80 80

Blanking Blanking Line 1 Line 2 Line 3 Line 4

B0 B0 90 90 90 90

80
Line 480 (VGA) Line 240 (QVGA) Line 120 (QQVGA) Line 288 (CIF) Line 144 (QCIF) Line 96 (subQCIF)

90

80

90

A0 A0

Blanking Blanking

B0 B0

640 pixels (VGA) 320 pixels (QVGA) 160 pixels (QQVGA) 352 pixels (CIF) 176 pixels (QCIF) 128 pixels (subQCIF)

Blanking and start active pixel code Blanking and endactive pixel code Active line and start active pixel code Active line and end active pixel code

: FFh 00h 00h A0h : FFh 00h 00h B0h : FFh 00h 00h 80h : FFh 00h 00h 90h

04/01/05

14/27

TCM8230MD (A) Ver. 1.20

DATA OUTPUT TIMING CHART

TCM8230MD supports 2 HD pulses, one is Blanking pulse, and another one is Normal pulse. You can choose HD pulse by HSYNCSEL (Address=1Eh Bit3).

Pixel Size mode (HD=Blanking pulse)

1. Vertical timing (HSYNCSEL=1)
Normal operation mode (VGA, CIF(full), QVGA(zoom), QCIF(zoom))
1 frame
VD

18 lines 507 lines

HD

VGA full

478 479 480

CIF full

286 287

288

QVGA zoom

238 239 240

QCIF zoom

143 143

144

Low power operation mode (QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))
1 frame
VD

9 lines 254 lines

HD

QVGA full

238

239

240

QCIF full

142

143

144

QQVGA full

119

120

QQVGA zoom

119

120

subQCIF full

96

subQCIF zoom

96

04/01/05

15/27

TCM8230MD (A) Ver. 1.20 2. Horizontal timing (HSYNCSEL=1)

Normal operation mode (VGA, CIF (full), QVGA (zoom), QCIF (zoom))
DCLK (DCLKP=0)

VD

156.5 cycles of DCLK

VGA full

1 line 280 cycles of DCLK 1280 cycles of DCLK (640 PIXEL)

HD Data

blanking

638

639

640

blanking

CIF full

856 cycles of DCLK

HD Data

704 cycles of DCLK (352 PIXEL) blanking

1 2 3
350 351 352

blanking 920 cycles of DCLK

QVGA zoom

HD Data

640 cycles of DCLK (320 PIXEL)

blanking

318

319

320

blanking 1208 cycles of DCLK

QCIF zoom

HD Data

352 cycles of DCLK (176 PIXEL)

blanking

174

175

176

blanking

Blanking Y=0x00, UV=0x80 HNUM=0

Low power operation mode (QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))
DCLK (DCLKP=0)

VD

156.5 cycles of DCLK

QVGA full

1 line 920 cycles of DCLK 640 cycles of DCLK (320 PIXEL)

HD Data

blanking

318

319

320

blanking 1208 cycles of DCLK

QCIF full

HD Data

352 cycles of DCLK (176 PIXEL)

blanking

175

176

blanking 1240 cycles of DCLK

QQVGA full/zoom

HD Data

320 cycles of DCLK (160 PIXEL)

blanking

159

160

blanking 1304 cycles of DCLK

subQCIF full/zoom

HD Data

256 cycles of DCLK (128 PIXEL)

blanking

128

blanking

Blanking Y=0x00, UV=0x80

04/01/05

16/27

TCM8230MD (A) Ver. 1.20

Pixel Size mode (HD=Normal pulse)

1. Vertical timing (HSYNCSEL=0)
Normal operation mode (VGA, CIF(full), QVGA(zoom), QCIF(zoom))
1 frame
VD

18 lines 507 lines

HD

VGA full

478 479 480

CIF full

286 287

288

QVGA zoom

238 239 240

QCIF zoom

143 143

144

Low power operation mode (QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))
1 frame
VD

9 lines 254 lines

HD

QVGA full

238

239

240

QCIF full

142

143

144

QQVGA full

119

120

QQVGA zoom

119

120

subQCIF full

96

subQCIF zoom

96

04/01/05

17/27

TCM8230MD (A) Ver. 1.20 2. Horizontal timing (HSYNCSEL=0)

Normal operation mode (VGA, CIF (full), QVGA (zoom), QCIF (zoom))

DCLK (DCLKP=0)

VD

156.5 cycles of DCLK

VGA full 156 cycles of DCLK HD DOUT

1 line 1404 cycles of DCLK

1 2 3
638 639 640

156 cycles of DCLK

blanking
156 cycles of DCLK

blanking
156 cycles of DCLK

CIF full

HD DOUT

1404 cycles of DCLK blanking

156 cycles of DCLK 1 2 3
350 351 352

blanking
156 cycles of DCLK

QVGA zoom

HD DOUT

1404 cycles of DCLK

1 2 3
318 319 320

blanking
156 cycles of DCLK

blanking
156 cycles of DCLK

QCIF zoom

HD DOUT

1404 cycles of DCLK blanking

1 2 3
174 175 176

blanking

Blanking Y=0x00, UV=0x80 HNUM=0

Low power operation mode (QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))

DCLK (DCLKP=0)

VD

156.5 cycles of DCLK

QVGA full 156 cycles of DCLK HD DOUT

1 line
156 cycles of DCLK

1404 cycles of DCLK blanking

156 cycles of DCLK

318

319

320

blanking
156 cycles of DCLK

QCIF full

HD DOUT

1404 cycles of DCLK blanking

156 cycles of DCLK

175

176

blanking
156 cycles of DCLK

QQVGA full/zoom

HD DOUT

1404 cycles of DCLK 1 159 160 blanking

blanking
156 cycles of DCLK

1
156 cycles of DCLK

subQCIF full/zoom

HD DOUT

1404 cycles of DCLK blanking 1 128 blanking 1 2 3

Blanking Y=0x00, UV=0x80 HNUM=0

04/01/05

18/27

TCM8230MD (A) Ver. 1.20

Exposure mode
TCM8230MD supports long exposure time mode (ESRLSW (Address=04h, Bit5,4)= 1) and extra-long exposure time mode (ESRLSW (Address=04h Bit5,4)= 2, 3).

Vertical timing
Normal mode
ESRLSW=0 Data
1st frame 2nd frame 3rd frame

VD

Long exp. mode

ESRLSW=1

VD

Data

blanking

1st frame

blanking

2nd frame

blanking

Extra-long exp. mode

ESRLSW=2,3 V_LENGTH=3

VD

Data

blanking

1st frame

blanking

2nd frame

blanking

3rd frame

blanking

When use these modes, you should be sent below I2C commands before entry these modes. ESRLSW (Address=04h Bit5,4)= 1, 2 or 3 Address=22h, Data=10h (Default Data=26h) Address=24h, Data=0Fh (Default Data=27h) Address=28h, Data=06h (Default Data=23h)

04/01/05

19/27

TCM8230MD (A) Ver. 1.20

POWER ON SEQUENCE
EXTCLK
(V p-p = 2.8V)

DVDD
(1.5V)

PVDD
(2.8V)

100ms>x>=0ns

100ms>x>=0ns

IOVDD
(2.8V)
>0ns >=100 cycles of EXTCLK

RESET
(from Outside)
>=2000 cycles of EXTCLK

SCL/SDA

Commands are available

*
VD DOUT
> 1V

1st picture

2nd picture

((VOUTPH + 3) - VRRPH) + 4 In default case: VOUTPH=35dec, VRRPH=38dec, ((35 + 3) - 38) + 4 = 4H D_MASK=1

TCM8230MD cannot output pictures after power on immediately. You should be sent some I2C commands after power on as below. Address=03h, Data=00h (Default Data=80h)

POWER OFF SEQUENCE

EXTCLK
(V p-p = 2.8V)

IOVDD
(2.8V)
100ms>x>0ns

PVDD
(2.8V)
100ms>x>=0ns

DVDD
(1.5V)

100ms>x>=0ns

04/01/05

20/27

TCM8230MD (A) Ver. 1.20

SLEEP MODE SEQUENCE

1. From normal operation to sleep mode
2 frames

VD SCL/SDA DOUT
Operation Mode Sleep Command Picture Normal operation

Sleep mode

EXTCLK

((VOUTPH + 3) - VRRPH) + 4 In default case: VOUTPH=35dec, VRRPH=38dec, ((35 + 3) - 38) + 4 = 4H

2. From sleep mode to normal operation

VD 1 frame SCL/SDA DOUT

Operation Mode Sleep mode Wake up Command

3H

> 1 frame

x Normal operation

Picture

EXTCLK

D_MASK=1

Some registers data, AWB calculated data and ALC calculated data are kept the last values during sleep mode.

04/01/05

21/27

TCM8230MD (A) Ver. 1.20

MAXIMUM RATING
RATING 1.5V -0.3 to 3.0 -30 to 85 2.8V -0.3 to 3.6 UNITS V Degree C

Power supply voltage Storage tempature

RECOMMENDED OPERATING CONDITION

MIN 2.6 2.3 1.4 -20 TYP 2.8 2.5 1.5 MAX 3.0 2.7 1.6 60 UNITS V Degree C

Power supply IOVDD, PVDD* voltage DVDD Operational tempature

*If using 2.5V, must input setting command. (Default setting is 2.8V.)

04/01/05

22/27

TCM8230MD (A) Ver. 1.20

ELECTRICAL CHARACTERISTICS
DC Characteristic ( Ta=25 degree C, DVDD(=AVDD) =1.5V, PVDD= IOVDD =2.8V ) 1. POWER
ITEM POWER VGA(15fps) CONDITION (Normal operation mode) Sleep mode MIN TYP 40 MAX TBD TBD UNITS mA uA

* Measurement condition : Machbeth chart (full) *Peak current = 180mA

2. EXTCLK
ITEM LOW level input voltage Rectangular shape HIGH level input voltage LOW level input current HIGH level input current DUTY SYMBOL VIL;EXTCLK VIH;EXTCLK IIL;EXTCLK IIH;EXTCLK CONDITION VIN=GND VIN=IOVDD MIN -0.3 IOVDD*0.8 -10 -10 45/55 TYP IOVDD 50/50 MAX IOVDD*0.2 3.0 10 10 55/45 UNITS V V uA uA % *1 NOTES

1) Duty referred to 50% level of input EXTCLK

3. SCL and SDA

SCL ITEM LOW level input voltage HIGH level input voltage LOW level input voltage SDA HIGH level input voltage LOW level output voltage (IOL=4mA) SYMBOL VIL;SCL VIH;SCL VIL;SDA VIH;SDA VOL;SDA MIN 0.0 IOVDD*0.7 0.0 IOVDD*0.7 0.0 TYP IOVDD IOVDD MAX 0.4 3.0 0.4 3.0 0.4 UNIT V V V V V NOTES

4. DOUT0 to DOUT7, DCLK, HD and VD

ITEM SYMBOL DOUT0 to DOUT7, LOW level output voltage (IOL=2mA) VOL;DATA DCLK, HD and VD HIGH level output voltage (IOH=-2mA) VOH;DATA MIN 0.0 2.4 TYP IOVDD MAX 0.4 UNIT V V NOTES

5. RESET
ITEM SYMBOL CONDITION LOW level input voltage VIL;RESET HIGH level input voltage VIH;RESET LOW level input current HIGH level input current IIL;RESET IIH;RESET VIN=GND VIN=IOVDD MIN -0.3 IOVDD*0.8 -10 -10 TYP IOVDD MAX IOVDD*0.2 3.0 10 10 UNIT V V uA uA NOTES

04/01/05

23/27

TCM8230MD (A) Ver. 1.20 AC Characteristic ( Ta=25 degree C, DVDD(=AVDD) =1.5V, PVDD= IOVDD =2.8V ) 1. EXTCLK
ITEM Clock frequency Rise time Fall time SYMBOL fEXTCLK tr;EXTCLK tf;EXTCLK FPS 0 1 MIN 11.90 TYP 24.54 MAX 25.00 27.00 5 5 UNITS MHz ns ns NOTES *1 *2

1) FPS : Address=02h, Bit7 2) All values referred to VIHmin and VILmax levels
fEXTCLK

VIH VIL

Tr;EXTCLK

Tf;EXTCLK

2. EXTCLK input circuit

TCM8230MD

2.8V 0V Duty 50:50

EXTCLK

04/01/05

24/27

TCM8230MD (A) Ver. 1.20 3. SCL and SDA

ITEM Clock frequency Low period SCL High period Rise time Fall time Fall time Hold time(repeated) START condition After this period, the first clock pulse is Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Width of spike pulse Normal Wake-up from sleep mode SDA Rise time SYMBOL fSCL tLOW;SCL tHIGH;SCL tr;SCL tf;SCL tr;SDA tf;SDA tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tSP1 tSP2 MIN 1.3 0.6 0.6 0.6 0 100 0.6 0 0 MAX 400 300 300 300 300 50 20 UNITS KHz us us ns ns ns ns us us ns ns us ns ns *1 NOTES

1) All values referred to VIHmin and VILmax levels

SDA
tf tr tLOW tHD;STA tHD;DAT tSU;DAT tHIGH tf tHD;STA tSU;STA tSP tr

tBUF

SCL

tSU;STO

START

RE-START

STOP

START

04/01/05

25/27

TCM8230MD (A) Ver. 1.20 4. DOUT0 to DOUT7, DCLK, HD and VD

ITEM DCLK DOUT0 to DOUT7, HD, and VD Rise time Fall time Rise time Fall time SYMBOL tr;DCLK tf;DCLK tr;DATA tf;DATA tpd;SU tpd;HD MIN 10 10 MAX 6 6 6 6 UNITS ns ns ns ns ns ns *1 NOTES

Setup time of data Hold time of data

1) All values referred to VOHmin and VOLmax levels

tf;DCLK tr;DCLK VOH;DCLK VOL;DCLK tpd;SU tpd;HD VOH;DATA VOL;DATA tr;DATA, tf;DATA

DCLK

Data Out
DCLKP=0

CHARACTERISTICS OF LENS
ITEM Optical format Holizontal Field of view Vertical Diagonal F number TV distotion Focal length Focusing area Manual focusing Structure VALUE 1/6 57.4 44.5 69.1 F2.8 -0.4 TBD TBD Not avairable Double lens UNITS inch degree degree degree % mm cm -

04/01/05

26/27

TCM8230MD (A) Ver. 1.20

Appendix 1: Module Drawing

04/01/05

27/27