L16A1616T

LCM 200/183/166/143 MHz 3.3 VOLT, 4K REFRESH

ULTRA HIGH PERFORMANCE
1M X 16 SDRAM 2 BANKS X 512Kbit X 16

L16A1616T -5 -55 -6 -7 Unit

Clock Frequency (tCK) 200 183 166 143 MHz

Latency 3 3 3 3 clocks

Cycle Time (tCK) 5 5.5 6 7 ns

Access Time (tAC ) 5 5.3 5.5 5.5 ns

Features
■ JEDEC Standard 3.3V Power Supply
■ The L16A1616T is ideally suited for high per-
formance graphics peripheral applications
■ Single Pulsed RAS Interface
■ Programmable CAS Latency: 2, 3
■ All Inputs are sampled at the positive going edge
of clock
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave
■ UDQM & LDQM for byte masking
■ Auto & Self Refresh
■ 4K Refresh Cycles/64 ms
■ Burst Read with Single Write Operation
Description
The L16A1616T is a 16,777,216 bits synchro-
nous high data rate DRAM organized as 2 x
524,288 words by 16 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation.

Rev.2.9 September 2001

LCM L16A1616T

50 Pin Plastic TSOP-II Pin Names

PIN CONFIGURATION
CLK Clock Input
Top View
CKE Clock Enable

CS Chip Select
VCC 1 50 VSS
I/O1 2 49 I/O16 RAS Row Address Strobe
I/O2 3 48 I/O15
CAS Column Address Strobe
VSSQ 4 47 VSSQ
I/O3 5 46 I/O14 WE Write Enable
I/O4 6 45 I/O13
VCCQ 7 44 VCCQ A0–A10 Address Inputs
I/O5 8 43 I/O12
I/O6 9 42 I/O11 BA Bank Select
VSSQ 10 41 VSSQ
I/O1–I/O16 Data Input/Output
I/O7 11 40 I/O10
I/O8 12 39 I/O9 LDQM, UDQM Data Mask
VCCQ 13 38 VCCQ
LDQM 14 37 NC VCC Power (+3.3V)
WE 15 36 UDQM
CAS 16 35 CLK VSS Ground
RAS 17 34 CKE
CS 18 33 NC VCCQ Power for I/O’s (+3.3V)
BA 19 32 A9 VSSQ Ground for I/O’s
A10 20 31 A8
A0 21 30 A7 NC Not connected
A1 22 29 A6
A2 23 28 A5
A3 24 27 A4
VCC 25 26 VSS

Rev. 2.9 September 2001 2

Block Diagram

Write
Control MUX
Logic

Buffer
Input
DQMi

UDQM
Column Decoder

Column Decoder
LDQM I/O1-I/O16
Sense Amplifier

Sense Amplifier
Memory Array Memory Array
CLK
Bank 0 Bank 1
CKE
512k x 16 512k x 16
CS

Output
Buffer
Register

RAS
Timing

CAS
WE Row Row
Decoder Decoder
DQMi

Row Address Refresh

Buffer Counter

Column Address
Counter
A0-A10, BA
Programming

CLK
Burst Length
Latency 8
Register

Row Addresses
Column Address
Buffer
Address

A0-A7, BA

Column Addresses

Rev.2.9 September 2001 3

LCM L16A1616T

Signal Pin Description

Pin Name Input Function
CLK Clock Input System clock input. Active on the positive rising edge to sample all inptus

CKE Clock Enable Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self
refresh mode

CS Chip Select Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi

RAS Row Address Strobe Latches row addresses on the positive edge of CLK with RAS low.
Enables row access & precharge

CAS Column Address Strobe Latches column addresses on the positive edge of CLK with CAS low.
Enables column access

WE Write Enable Enables write operation

A0-A10 Address During a bank activate command, A0-A10 defines the row address.
During a read or write command, A0-A7 defines the column address. In
addition to the column address A10 is used to invoke auto precharge BA
define the bank to be precharged. A10 is low, auto precharge is disabled
during a precharge cycle, If A10 is high, both bank will be precharged ,
if A10 is low, the BA is used to decide which bank to precharge. If A10 is
high, all banks will be precharged.

BA Bank Select Selects which bank to activate. BA low select bank A and high selects
bank B

I/O1-I/O16 Data Input/Output Data inputs/output are multiplexed on the same pins

UDQM, LDQM Data Input/Output Mask Makes data output Hi-Z. Blocks data input when DQM is active

VDD/VSS Power Supply/Ground Power Supply. +3.3V ± 0.3V/ground

VDDQ/VSSQ Data Output Power/Ground Provides isolated power/ground to DQs for improved noise immunity

NC No Connection

Rev.2.9 September 2001 4

LCM L16A1616T

Package Diagram

50-Pin Plastic TSOP-II (400 mil)

0.039 ± 0.002 +0.003

[1 ± 0.05] 0.4 ± 0.005 0.006 –0.001
0.004±0.002 0.047 Max [10.16 ± 0.13] +0.08
0.15 –0.03
[0.1±0.05] [1.2 Max]

0.020±0.004
0.031 [0.8] 0.004 [0.1] [0.5 ± 0.1]

0.016 +0.002
–0.004 0.008 [0.2] M 44x 0.463±0.008
0.4 +0.05 [11.76 ± 0.2]
–0.1
50 26

1 25
1
0.825±0.005
[20.95±0.13] Unit in inches [mm]

1 Does not include plastic or metal protrusion of 0.010 [0.25] max. per side

Rev.2.9 September 2001 20