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SPCA707A

VCD Boom Box Decoder

AUG. 21, 2001


Version 1.0

SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPCA707A

Table of Contents
PAGE

1. GENERAL DESCRIPTION ..................................................................................................................................................................... 4


2. FEATURES............................................................................................................................................................................................. 4
3. BLOCK DIAGRAM ................................................................................................................................................................................. 5
4. SIGNAL DESCRIPTIONS....................................................................................................................................................................... 5
4.1. GLOBAL SIGNALS .............................................................................................................................................................................. 5
4.2. CD INTERFACE SIGNALS ................................................................................................................................................................... 6
4.3. VIDEO INTERFACE SIGNALS ............................................................................................................................................................... 6
4.4. AUDIO INTERFACE SIGNALS ............................................................................................................................................................... 6
4.5. DRAM INTERFACE SIGNALS .............................................................................................................................................................. 6
4.6. HOST INTERFACE SIGNALS ................................................................................................................................................................ 6
4.7. ROM/GIO INTERFACE SIGNALS ......................................................................................................................................................... 6
5. SYSTEM SYNC ...................................................................................................................................................................................... 7
5.1. SOME ABBREVIATIONS FOR SYSTEM SYNC MODULE ............................................................................................................................ 7
5.2. TIMERS AND TIME STAMPS ................................................................................................................................................................. 7
5.3. TIME MASTER ................................................................................................................................................................................... 7
6. VIDEO DECODER.................................................................................................................................................................................. 7
7. VIDEO PROCESSOR............................................................................................................................................................................. 7
7.1. VIDEO PROCESSOR INTERFACE.......................................................................................................................................................... 8
7.2. USAGE FOR 8 BIT VIDEO INTERFACE .................................................................................................................................................. 8
8. ON SCREEN DISPLAY .......................................................................................................................................................................... 8
8.1. LINK ADDRESS .................................................................................................................................................................................. 8
8.2. START ROW ADDRESS ....................................................................................................................................................................... 8
8.3. START COLUMN ADDRESS ................................................................................................................................................................. 9
8.4. HSIZE ............................................................................................................................................................................................. 9
8.5. VSIZE ............................................................................................................................................................................................. 9
8.6. COLOR TABLE UPDATE ...................................................................................................................................................................... 9
8.7. BLEND LEVEL ................................................................................................................................................................................... 9
9. AUDIO DECODER ................................................................................................................................................................................. 9
9.1. AUDIO OUTPUT INTERFACE ................................................................................................................................................................ 9
10. RISC PROCESSOR ..............................................................................................................................................................................10
11. DRAM INTERFACE...............................................................................................................................................................................10
11.1. DRAM TIMING.................................................................................................................................................................................10
11.2. DRAM MEMORY MAP ......................................................................................................................................................................10
12. CD INTERFACE ....................................................................................................................................................................................11

13. PROGRAMMABLE I/O..........................................................................................................................................................................15


14. IR INPUT/OUTPUT................................................................................................................................................................................16
14.1.IR INPUT .........................................................................................................................................................................................17
14.2.IR OUTPUT......................................................................................................................................................................................18

© Sunplus Technology Co., Ltd. 2 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

15. HOST INTERFACE................................................................................................................................................................................19


15.1. HOST READ TIMING .......................................................................................................................................................................19
15.2. HOST W RITE TIMING......................................................................................................................................................................19
15.3. VFD CONTROL .............................................................................................................................................................................20
16. MACRO COMMANDS ...........................................................................................................................................................................23
17. ELECTRICAL SPECIFICATIONS..........................................................................................................................................................29
17.1. OPERATING CONDITIONS ...............................................................................................................................................................29
17.2. AC TIMING CHARACTERISTICS .......................................................................................................................................................30
17.3. THE RELATIONSHIP BETWEEN VOLTAGE (V) AND THE CURRENT (MA):................................................................................................34
18. APPLICATION CIRCUITS .....................................................................................................................................................................35
18.1. APPLICATION CIRCUIT - (1).............................................................................................................................................................35
18.2. APPLICATION CIRCUIT - (2).............................................................................................................................................................36
18.3. APPLICATION CIRCUIT - (3).............................................................................................................................................................37
18.4. APPLICATION CIRCUIT - (4).............................................................................................................................................................38
19. PACKAGE/PAD LOCATIONS ...............................................................................................................................................................39
19.1. PACKAGE OUTLINE DIMENSIONS .....................................................................................................................................................39
20. DISCLAIMER ........................................................................................................................................................................................40

21. REVISION HISTORY .............................................................................................................................................................................41

© Sunplus Technology Co., Ltd. 3 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

VCD BOOM BOX DECODER

1. GENERAL DESCRIPTION 2. FEATURES


The SPCA707A VCD BOOM BOX decoder is designed to  General features
maximize system performance and minimize cost. The standard ─ Only requires one 256K x 16 DRAM
configuration requires only a 256K x 16 DRAM, a ROM, a VCD-AV ─ 14K bytes free space for user usage and OSD
interface IC and a CD-kit to build a complete VCD player. An ─ Glueless interface to CD-DSP, DRAM, ROM, Audio DAC
enhancement mode extends external DRAM from 4Mbits to and TV encoder
8Mbits (extendable to 16Mbits if package uses a 160 pin QFP).  Real time video decompression
─ MPEG1 video decoder conforming to ISO-11172
The SPCA707A integrates functions needed for a VCD BOOM ─ Programmable hybrid video error concealment
BOX system, such as Stereo Key controller for Karaoke, Audio  Real time audio decompression
wide sound and Digital audio decoder. And in order to make the ─ MPEG audio layer 1, 2 and 3 decompression conforming to
VCD system more sophisticated, the SPCA707A also includes a ISO-11172 standard
flexible programmable interface. Through the interface, not only ─ Automatic audio error concealment
can the microprocessor in a VCD player be neglected, but it also ─ Digital volume control
allows the VCD player to be programmed for numerous  Real time system layer decompression conforming to
applications. ISO-11172 standard
 Advanced video processing and display
The SPCA707A is designed as a glueless connection for ─ Supports NTSC and PAL TV standards
traditional TV encoder and audio DAC. In order to further reduce ─ Performs vertical scaling to allow NTSC/PAL source to be
costs, it can also be directly interfaced with CD-DSP IC, AV displayed on PAL/NTSC TV in correct aspect ratio
interface IC, and echo generator. Designed to fulfill VCD ─ Performs real-time processing at 720 x 480 x 30 fps,
requirements, the SPCA707A includes, not only the latest 720 x 240 x 60 fps, 720 x 576 x 25 fps or 720 x 288 x 50 fps
technology, but also the full service and support of Sunplus. ─ Horizontal and Vertical Interpolation for high quality video
output
A common implementation utilizing the SPCA707A is presented ─ Video fade-in/fade-out
below:  Component features
─ Supply voltage : 3.0 volts to 3.6 volts
DRAM ROM
─ I/O interface : 5 volts tolerance
─ Package : 128-pin QFP

CD-DSP TV Encoder TV
 Built-in Programmable Karaoke processor with
─ Key control for MPEG audio layer1, layer2 and layer3
SPCA707A ─ Programmable wide sound
up(optional)
Stereo
Audio DAC
Audio
Front
Panel
Function
Keys  Software Drivers
─ Drivers for CD-I (green book, white book), Karaoke CD,

Figure 1-1 VCD Boom Box System Block Diagram Video CD 2.0/1.1 and Audio CD (CD-DA)
─ Preview
─ User definable features
─ RISC game software
─ ZoomPro: Programmable video Zoom-in/out
─ ImagePro: Programmable digital image processing

© Sunplus Technology Co., Ltd. 4 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A
VCCKP DA(9:0)
 Built-in PLLs generating system and audio clocks VCC5OP
VCC5IP
DD(15:0)
CAS_B
VCCAP RAS_B0 DRAM Interface Signals
 Programmable serial bitstream CD interface VCCTVP SPCA707A RAS_B1
GNDIKP (128 pin) WE_B
Global Signals GND5OP
 Supports parallel mode Host control Interface GNDAP
GNDTVP
CLKIN
 Low voltage detection circuit to prevent power instability CLKIO
TEST_MODE
NDATA(7 : 0)
NSTROBE Host Interface Signals
BIST_MODE NWRITE

 Versatile programmable interface RESET_B

─ Support system controller emulation HSYNC_IN


CD_BCK
CD_LRCK CD Interface Signals
VSYNC_IN CD_DATA
Video Interface Signals
─ Programmable serial I/O interface for IR in/out, PAL_NTSC
CLK27OUT
DATA_TV(7 : 0)
VFD_CLK
CD-kit (DSA or CD-DSP IC) control and VFD control etc. VFD_DATA
VFD_STB
AUD_XCK
IR_IN ROM/GIO/IR
─ Accept digital audio PCM format input Audio Interface Signals
AUD_BCK
AUD_LRCK PIOs Interface Signals
AUD_DATA ROM_DATA(7 : 0)
AUD_EMP ROM_ADDR(17 : 0)

Figure 2-2 SPCA707A Signal Group Map


3. BLOCK DIAGRAM
4.1. Global Signals
VCC5OP,VCC5IP Power Input
DRAM Video TV
DRAM
Interface Interface Encoder This pin supplies 5 volts to I/O pad.
GND5OP Ground Input
System
Programmable OSD
Control
Serial I/O I/O Interafce Controller Ground for I/O buffers.
VFD, DSA
VCCKP Power Input
CD CD Interafce MPEG1 This pin supplies 3.3 volts to internal logic.
Video Decoder
GNDIKP Ground Input
Host Host Interafce
Ground for internal logic and input pad.
PCM Audio
Interface DAC VCCAP Analog power Input
This pin supplies 3.3 volts to internal PLL circuit.
KaraOk&
RISC
Sound Effect
Processor
Processor
GNDAP Analog ground Input
This pin is the ground for internal PLL circuit.
Clock MPEG1
Generator Audio Decoder VCCTVP TV power Input
This pin supplies 3.3 volts or 5 volts to TV encoder

Figure 1-2 SPCA707A Block Diagram


associated interface signals.
GNDTVP TV ground Input
This pin is ground for TV encoder associated interface

4. SIGNAL DESCRIPTIONS signals.


CLKIN, CLKIO Crystal Pin Input/output
ROM_ADDR17
ROM_ADDR16
ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10

ROM_ADDR9

ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
AUD_LRCK
AUD_DATA
PAL_NTSC

HSYNC_IN
DATA_TV0
DATA_TV1
DATA_TV2
DATA_TV3
DATA_TV4
DATA_TV5
DATA_TV6
DATA_TV7

VSYNC_IN

AUD_EMP
AUD_BCK

AUD_XCK
CD_DATA
CD_LRCK

CK27OUT

GND5OP

These two pins connect to 27 MHz crystal.


GNDTVP
CD_BCK

VCC5OP
VCCTVP

GNDIKP
VCCKP

TEST_MODE Test Enable Input


102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

RESET_B
VCC5IP
103
104
64
63
ROM_ADDR5
ROM_ADDR4
Bringing this pin high will put the chip in test mode.
NDATA0 105 62 ROM_ADDR3

This pin should normally be low.


NDATA1 106 61 ROM_ADDR2
VCCKP 107 60 GNDIKP
NDATA2 108 59 ROM_ADDR1
GNDIKP 109 58 VCCKP
NDATA3
NDATA4
110
111
57
56
ROM_ADDR0
ROM_DATA0
BIST_MODE BIST Enable Input

SPCA707A
NDATA5 112 55 ROM_DATA1
NDATA6 113 54 ROM_DATA2
NDATA7
NSTROBE
114
115
53
52
ROM_DATA3
ROM_DATA4
Bringing this pin high will put the chip in bist test mode.
MD 116 51 ROM_DATA5
MC
NWRITE
117
118
50
49
ROM_DATA6
ROM_DATA7 This pin should normally be low.
VFD_DATA 119 48 DA0
VFD_CLK 120 47 DA1
VFD_STB
IR_IN
121
122
46
45
VCC5IP
DA2
RESET_B Hardware reset Input
IR_OUT 123 44 GNDIKP
DSA_ACK
DSA_DATA
124
125
126
43
42
DA3
VCCKP This signal is active low and must be active for at least 25
DSA_STB 41 DA4
VCC5OP 127 40 DA5
GND5OP 128 39 DA6
CLK27OUT clock cycles. After reset, the SPCA707A will be
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9

in the initialization state.


CLKIN
PIO12
PIO13

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD15
DD14
DD13
DD12
DD11
DD10
DD9
DD8

RAS_B0
RAS_B1

DA9
DA8
DA7
VCCKP

GNDIKP
VCCAP
TEST_MODE
GNDAP
BIST_MODE
SCAN_ENABLE

WE_B
VCCKP
CAS_B
GNDIKP

VCC5OP
GND5OP
CLKIO

Figure 2-1 SPCA707A Pin Map

© Sunplus Technology Co., Ltd. 5 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

4.2. CD Interface Signals 4.5. DRAM Interface Signals


CD_DATA CD serial data Input DA(9:0) DRAM address bus Outputs
This pin is input for serial data from CD-DSP. Address bus of fast-page or EDO DRAM
CD_LRCK CD left/right clock Input DD(15:0) DRAM data bus Bidirectional
CD_LRCK provides 16-bit word synchronization to the DRAM access data bus. The direction is determined by
SPCA707A and has several programmable features, such as DR_WE_L signal.
polarity, delay and pulse mode. CAS_B Column address strobe Output
CD_BCK CD bit clock Input DRAM CAS signals.
The CD_BCK is the CD-Decoder bit clock. The SPCA707A RAS_B Row address strobes Output
can accept multiple BCK rates. DRAM RAS signals for bank 1 to 0.
WE_B Memory write enable Output
4.3. Video Interface Signals DRAM write enable signal.
HSYNC_IN Horizontal sync Input
Horizontal sync signal input from TV encoder. 4.6. Host Interface Signals
VSYNC_IN Vertical sync Input NDATA(7:0) data bus Bidirectional
Vertical sync signal input from TV encoder.
Bus interface between host and Mpeg chip.
DATA_TV(7:0) Video out Output
NSTROBE strobe signal Input
These pins form the video data output bus. It contains
Strobe signal for other host interface signals
multiplexed Luminance and Chrominance video data.
NWRITE write/read enable Input
PAL_NTSC PAL/NTSC control Output
This pin controls the PAL/NTSC mode of TV encoder.
4.7. ROM/GIO Interface Signals
CLK27OUT 27MHz clock Output
27 MHz video pixel clock output to the TV encode. ROM_DATA(7:0) ROM data bus Input
Generic 8-bit parallel ROM data bus.

4.4. Audio Interface Signals ROM_ADDR(17:0) ROM address bus Output


Generic ROM address bus.
AUD_XCK Audio clock Bidirectional
VFD_DATA data signal Bidirectional
When the SPCA707A is programmed for external audio clock
Data signal for VFD.
mode, the audio clock will come from this signal. When
VFD_CLK clock signal Output
programmed for internal audio clock, this signal will reflect
Clock signal for VFD.
the internal audio clock.
VFD_STB strobe signal Output
AUD_BCK Audio bit clock Output
Strobe signal for VFD.
This pin is the audio bit clock output. Depending on audio
output mode, this signal can be derived from the master DSA_ACK Ack signal Bidirectional

clock or be AUD_XCK divided by 8. It can be either 48 or Ack signal for DSA interface

32 times the sampling clock. DSA_DATA Data signal Bidirectional

AUD_LRCK Audio left/right clock Output Data signal for DSA interface.
This pin is used as the Left/Right data channel indicator. DSA_STB Strobe signal Bidirectional
AUD_DATA Audio data bus Output Strobe signal for DSA interface.
This pin is used as the serial audio data clocked out relative IR_IN IR input Input
to AUD_BCK. IR input pin. This input supports both NEC and Philips
AUD_EMP Emphasis control Output format IR signal.
This signal is used to control the de-emphasis circuitry of the IR_OUT IR output pin Output
audio output DACs. In CD-DA pass-through mode, this IR output pin.
output follows the state of the CD_EMP signal; when in VCD
mode, this pin follows the LSB of the emphasis field of the
MPEG-1 audio header.

© Sunplus Technology Co., Ltd. 6 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

5. SYSTEM SYNC 5.3.1. DSM as time master


5.1. Some Abbreviations for System Sync Module To use the Digital Storage Medium, in this case the Video CD

STC - System Time Clock reader, as the time master, follow the synchronization guidelines

SCR - System Clock Reference given below:

DTS - Decode Time Stamp 1). Initialize the STC to the first SCR received.

PTS - Presentation Time Stamp 2). Set the STC to run (incrementing at 90KHz).

STD - System Target Decoder (ideal decoder) 3). Maintain the STC by updating it with SCR values received.

PU - Presentation Unit 4). Video presentations are made when the video PTS==STC.

AU - Access Unit 5). Audio presentations are made when the audio PTS==STC.

DSM - Digital Storage Medium


Fs - Sampling Frequency 5.3.2. Audio as time master
To use the Audio block as the time master, follow the
5.2. Timers and Time Stamps synchronization guidelines given below:

5.2.1. System time clock (STC) 1). Initialize the STC to the first SCR received.
2). Set the STC to run (incrementing at 90KHz)
The System Time Clock is the main clock counter used for all time
3). Maintain the STC by updating it with Audio PTS values
reference. The STC is a 33-bit counter based on a 90kHz clock.
received.
4). Video presentations are made when the video PTS==STC.
5.2.2. System clock reference (SCR)
5). Use SRC values to determine if the DSM data rate is correct.
The System Clock Reference is a time stamp in the MPEG system
stream. The SCR value represents the time when the last byte of
the SCR field leaves the encoder. For the decoder, this value is
6. VIDEO DECODER
used to initialize the STC and for updating the STC when using
The Video Decoder is an MPEG 1 video decoder optimized for
the DSM as time master.
minimum size while conforming to ISO 11172 standard. The
module will read an MPEG 1 video stream in and continuously
5.2.3. Decode time stamp (DTS)
generate frames in external DRAM. The frames will then be
The Decode Time Stamp value represents the time when an
processed by a video processor for final display. The Video
access unit should be ready for decoding. For the Audio stream,
Decoder performs the following functions:
the DTS==PTS so it is not used. In the Video stream, the DTS
1). Huffman Decoding
for I-Frames and P-Frames are nominally equal to the PTS value
2). Dequantization
minus the number of picture periods of video reordering delay
3). Inverse Cosine Transform
multiplied by the picture period, in units of the 90KHz STC.
4). Motion Vector Generator
5). Address Generator
5.2.4. Presentation time stamp (PTS)
6). Motion Compensation
A Presentation Time Stamp represents the time at which a
presentation unit should be displayed. In the case of Audio, this
is the time when the decoder should begin the playback of an 7. VIDEO PROCESSOR
audio frame. In the case of Video, this is the time when the
The Video Processor & Output Interface is responsible for taking
corresponding video frame should be displayed.
decompressed data from memory (DRAM), and process the data
into raster (interlaced or non-interlaced) video. Some of the
5.3. Time Master
important processing functions include horizontal/vertical
A decoding system, including all of the synchronized decoders and interpolation, filtering and clipping.
the source of the coded data, must have exactly one independent
time master. The SPCA707A chip allows the microcode to use The video processing functions performed by the video processor
either the DSM or Audio block as the time master. The time include vertical interpolation, horizontal interpolation, horizontal
master selection depends on how the STC is updated. filtering, proprietary high-resolution functions and clipping
functions. Video interpolations allow for small SIF images of
MPEG video decoding to be enlarged without blocking or

© Sunplus Technology Co., Ltd. 7 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

discontinuity effects. The final display of the SIF image will have 7.2. Usage for 8-Bit Video Interface
smooth transitions in both horizontal and vertical directions. The SPCA707A co-operates with master-mode TV-encoders.
Horizontal filtering will also be performed to reduce any aliasing VSYNC_IN and HSYNC_IN signals come from a standard
effects. The proprietary high-resolution functions are used to TV-encoder(as in figure 5-2). The SPCA707A will lock to these
maintain quality in the 704 X 576 high resolution still image mode. reference timing and put the data onto the DATA_TV[7:0]. Data
The Clipping function can be turned on to allow for compatibility on the DATA_TV[7:0] is multiplexed data of 4_1_1 format. The
with CCIR 601 specifications. data is sequenced out (Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3..) after
HSYNC_IN. Detailed timing diagram of TV encoder interface is
Active
Video Active presented in Figure 5-3 below:
OSD
Display
Output CLK27OUT
HSYNC_IN

1-Blend DATA_TV(7:0) Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11

Figure 5-3 8 bit Video Interface Timing

8. ON SCREEN DISPLAY
OSD Blend
The on screen display feature is intended to display a rectangular
area which can be a graphic or text overlay the decoded video on
Figure 5-1 Video Processor Output Mixer
the screen. There are flexible numbers of rectangular regions
that can be in a field and each region consists of a region header
7.1. Video Processor Interface and data. Host or RISC will program these headers and data
The I/O interface to the video processor is defined below: then store to the DRAM for various application purpose. OSD
HSYNC_IN Horizontal sync Input decoder reads the header and data, then interpreted as graphic
Horizontal sync signal input from TV encoder. data and overlaid with video for output to the display device.
VSYNC_IN Vertical sync Input There are headers in each region and they can give the OSD
Vertical sync signal input from TV encoder. decoder information to interpret the succeeding bit mapped data.
DATA_TV(7:0) Video out Output
These pins form the video data output bus. It contains 8.1. Link Address
multiplexed Luminance and Chrominance video data.
This address shows the address of next OSD region and OSD
PAL_NTSC PAL/NTSC control Output
decoder use it to next OSD block in the DRAM. Figure 6-1
This pin control the PAL/NTSC mode of TV encoder.
shows the linked list structure.
CLK27OUT 27 MHz clock Output
27 MHz video pixel clock output to the TV encoder signal.
OSD1
OSD1 Block
The recommended interface scheme is shown in Figure 5-1
OSDm
below:
OSDn Block

OSDn

SPCA707A PAL_NTSC OSDm Block


CLK27OUT
8
DATA_TV
TV
Encoder Figure 6-1 Link List Structure

VSYNC_IN
HSYNC_IN 8.2. Start Row Address
This address indicates the start vertical address of bitmapped data
Figure 5-2 Video Processor Interface which will be begun to display on the screen.

© Sunplus Technology Co., Ltd. 8 AUG. 21, 2001


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SPCA707A

8.3. Start Column Address 9.1.1. Audio output interface signals


This address indicates the start horizontal address of bitmapped The signals from the Audio Output Interface are as follows:
data which will be begun to display on the screen.
AUD_DATA Audio data bus Output
8.4. HSIZE Serial audio data clocked out relative to AUD_BCK.

This parameter gives the width of the associated OSD region. AUD_LRCK Audio Left/Right clock Output
Left/Right data channel indicator.

8.5. VSIZE AUD_BCK Audio bit clock Output


Audio bit clock output. Depending on audio output mode,
This parameter gives the height of the associated OSD region.
this signal can be derived from the master clock or be
AUD_XCK divided by 8. It can be either 48 or 32 times the
8.6. Color Table Update
sampling clock.
If this bit is active, there will be a color look up table following the
AUD_XCK External audio clock Input
header. The luminance part, Y, is represented by 6 bit and the
When the SPCA707A is programmed for external audio clock
chrominance part, Cb and Cr, are represented by 4 bit for each.
mode, the audio clock will come from this signal. When
The bitmapped data following the OSD header are 2 bits per pixel.
programmed for internal audio clock, this signal will reflect
the internal audio clock.
8.7. Blend Level
AUD_EMP Emphasis Control Output
This parameter gives the ratio of OSD that will mix with the This signal is used to control the de-emphasis circuitry of the
corresponding video data to be displayed on the screen. audio output DACs. In CD-DA pass-through mode, this
output follows the state of the CD_EMP signal; when in VCD
mode, this pin follows the LSB of the emphasis field of the
9. AUDIO DECODER MPEG-1 audio header.
The Audio Decoder will process all computation intensive
functions for the MPEG 1 Layer1, Layer 2 and Layer3 A typical connection scheme is shown in Figure 8-1 below:
decompression tasks. However, Layer3 can not be decoded
AUD_XCK
when the video decoding function is in progress. Layer1 and
Layer2 can be smoothly decoded when the video decoding
function is enabled. RISC and Audio Decoder cooperate in the SPCA707A AUD_DATA

audio decoding procedure. Front-end decoding functions, which


AUD_LRCK Audio
AUD_BCK DAC
have low computational requirements, are handled by the RISC
AUD_EMP
processor. The Re-quantization and Synthesis Subband Filter
functions are the most computationally intensive portions of audio
Figure 8-1 Audio Output Interface
decompression and are processed by the Audio Decoder. After
audio data has been decompressed, the resulting PCM data is
stored in DRAM for final output by the Audio Output Interface A timing diagrams of the audio interface clocking modes are
Module. presented in Figure 8-2 below.

AUD_BCK

9.1. Audio Output Interface AUD_LRCK

AUD_DATA 0 15 14 1 0 15 14 1 0 15

The Audio Output Interface takes PCM data from memory (DRAM) BCK = 32 x Fs

and outputs it in bit-serial format to external audio DACs. The AUD_BCK

AUD_LRCK

PCM audio data will be in alternating left/right channel format if the AUD_DATA 0 15 14 1 0 15 14 1 0 15 14

BCK = 48 x Fs

data is in stereo mode. In mono mode, the data will be a list of


PCM values. Figure 8-2 Audio Interface Clocking Modes

© Sunplus Technology Co., Ltd. 9 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

10. RISC PROCESSOR


The RISC processor is used to help decode high level data Refresh is done with CAS-before-RAS type refresh cycles. This
formats, MPEG system layers, low bandwidth MPEG audio and eliminates the need for a refresh address counter. The requency
video decoding and assorted miscellaneous functions. If the of refresh is programmable.
SPCA707A were used in a low cost system with simple user
interfaces, additional savings can be accomplished by using the 11.2. DRAM Memory Map
RISC core to perform host micro-controller functions; thereby Figure 10-4 shows the DRAM memory map of the SPCA707A.
dropping the micro-controller from the bill-of-materials. The memory is partitioned into several regions. These regions
are:
1). Software Usage
11. DRAM INTERFACE 2). Audio Work Buffer
The DRAM interface is used by the SPCA707A to access DRAM 3). OSD buffer
for all required functions in the system including bit stream store 4). CD buffer
after parsing, reading bit stream into the VLD, reference 5). Video Channel Buffer
macroblock read and motion compensated macroblock write, 6). Audio Channel Buffer
display data read for display interface, OSD data store and read, 7). Reference Frame0 of Luminance
and so on. The DRAM interface operates at 54 Mhz and can 8). Reference Frame0 of Chrominance
support up to 2 M Byte addressing arrange. 9). Reference Frame1 of Luminance
10). Reference Frame1 of Chrominance

11.1. DRAM Timing 11). B Frame of Luminance


12). B Frame of Chrominace
The DRAM interface is designed to work with 70 ns or 80 ns fast
page-mode DRAMs. This type of DRAM is very economical and
A programmable pointer points to each region. RISC can change
allows fast accesses when data falls within a DRAM page
the content of any pointer via register file.
boundary. Figures 10-1 and 10-2 provide some timing diagrams
of fast page mode read and write accesses.

CLK
Software usage
RAS_B

CAS_B

DA Row 1 Col 0 Col 1 Col 2 Col 3 Row 2


AUDYA
DD D0 D1 D2 D3 Audio work buffer
OSDYA
WE_B OSD
CDYA
CD
Figure 10-1 DRAM Read Timing EVBYA

Video Channel Buffer

EABYA
CLK Audio Channel Buffer
RAS_B REF0_LUMA

CAS_B Reference Frame 0 - (Luma)


DA Row 1 Col 0 Col 1 Col 2 Col 3 Row 2
REF0_CHROMA
DD D0 D1 D2 D3 Reference Frame 0 - (Chroma)
REF1_LUMA
WE_B
Reference Frame 1 - (Luma)

REF1_CHROMA
Figure 10-2 DRAM Write Timing
Reference Frame 1 - (Chroma)
BIDIR_LUMA

BF - (Luma)
CLK

RAS_B BIDIR_CHROMA
BF - (Chroma)
CAS_B

Figure 10-3 DRAM Refresh Timing Figure 10-4 DRAM Memory Map

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12. CD INTERFACE
The CD interface is a simple serial interface for standard Notice that the preprocessed serial data can be routed directly to
CD-DSPs. Serial data from the CD-DSP is shifted into the the Audio output stage for CD-DA format data or stored in DRAM
SPCA707A, preprocessed by the CD interface module, then for post-processing.
written to DRAM for post-processing by the RISC processor.
Since post-processing is accomplished by the RISC processor, the The CD interface is composed of the following signals:
data stream can be in any format. For example CD-DA,
CD-ROM, CD-ROM/XA, CD-I, MPEG1 system streams, MPEG1 CD_DATA CD serial data Input
video streams and MPEG1 audio streams. Note that for the The serial data input from the CD-DSP.
CD-DA format, since no post-processing is necessary, the serial CD_LRCK CD Left/Right Clock Input
data can be routed directly to the audio DACs. CD_LRCK provides 16-bit word synchronization to the
SPCA707A and has several programmable features, such as
The RISC processor and dedicated hardware is responsible for polarity, delay and pulse mode.
the following CD data stream post-processing functions when the CD_BCK CD Bit Clock Input
data format is not CD-DA: The CD_BCK is the CD-Decoder bit clock. The SPCA707A
can accept multiple BCK rates. The CD-BCK can be set to
1). Real-time parsing for Mode 2 form 2 sectors. multiple rates as in Table 11-1.
2). Real-time parsing for Mode 1 and Mode 2 form 1 sectors
(including error correction when not decoding MPEG). The CD input format can be selected by several programmable
3). Real-time processing of Mode 0 and skipping to next sector. control bits. Six common CD data formats are presented in Table
4). Q-erasure correction, P-erasure correction and P-error check. 11-2.

Table 11-1: BCK/Data rate/ LRCK relationships


BCK CD Speed Data Rate BCK per LRCK
1.42 MHz Normal 1.42 Mbits/sec 32
2.13 MHz Normal 1.42 Mbits/sec 48
2.84 MHz Normal 1.42 Mbits/sec 64
2.84 MHz Double 2.84 Mbits/sec 32
4.26 MHz Double 2.84 Mbits/sec 48
5.84 MHz Double 2.84 Mbits/sec 64

Table 11-2: CD Input Format


Mode # of BCK Data MSB/LSB first LRCK left/right polarity Data latch timing

1 32 MSB Right 1
2 32 MSB Left 0
3 24 MSB Right 1
4 24 LSB Right 0
5 24 MSB Right 1
6 16 MSB Left 1

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Table 11-3: CDDSP configuration examples:

Register Name Reg Bits Description RW RST


BCLK polarity for LRCK/DATA/C2P0
[0] 0: falling edge
1: rising edge
[1] Data bit-order 1: MSB first 0: LSB first
[2] Data justify 1: left-justified 0: right-justified
Data delay (with respect to LRCK)
[3] 0: zero-delay
1: 1-cycle delay
[4] LRCK polarity 0: low-is-left 1: low-is-right
[5] LRCK mode 0: level 1: pulse
C2P0 location
[6] 0: LSB error first
CD_CONFIG 146 r/w 0
1: MSB error first
Data-width
000: 16-bit
[9:7] :
110: 22-bit
111: 24-bit
Data-container-size
00: 16-cycle
[12:11]
01: 24-cycle
10: 32-cycle
[13] Data-descrambling 0: primitive 1: descrambled
[14] Data byte-swapping 0: no-swapping 1: swapping

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Functional timing diagrams of the above six formats are detailed below:

CASE I (CD_CONFIG = 0x1012)


CD-BCK

CD_LRCK Left Channel Right Channel


MSB LSB MSB LSB
CD_DATA 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

32-bit BCK, MSB First, Right Channel Low, Data latch timing high

CASE II (CD_CONFIG = 0x1003)


CD-BCK

CD_LRCK Right Channel Left Channel


MSB LSB MSB LSB
CD_DATA 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

32-bit BCK, MSB First, Left Channel Low, Data latch timing low

CASE III (CD_CONFIG = 0x0812)


CD-BCK

CD_LRCK Left Channel Right Channel Left Channel


MSB LSB MSB LSB MSB
CD_DATA 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid 15 14 13 12 11 10 9 8 7 6 5

24-bit BCK, MSB First, Right Channel Low, Data latch timing high

CASE IV (CD_CONFIG = 0x0851)


CD-BCK

CD_LRCK Left Channel Right Channel Left Channel


LSB MSB LSB MSB LSB
CD_DATA 0 Invalid 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Invalid 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Invalid 5 6 7 8 9 10 11 12 13 14 15

24-bit BCK, LSB First, Right Channel Low, Data latch timing low

CASE V (CD_CONFIG = 0x0813)


CD-BCK

CD_LRCK Left Channel Right Channel Left Channel


MSB LSB MSB LSB MSB
CD_DATA 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid 15 14 13 12 11 10 9 8 7 6 5

24-bit BCK, MSB First, Right Channel Low, Data latch timing high (Note: no C2P0 for this format)

CASE VI (CD_CONFIG = 0x0002)


CD_BCK

CD_LRCK Right Channel Left Channel Right Channel Left Channel


MSB LSBMSB LSBMSB LSBMSB LSBMSB
CD_DATA 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13

16-bit BCK, MSB First, Left Channel Low, Data latch timing high

Figure 11-1 Timing diagrams of typical CD Input Formats in Table 11-2

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Some common CD Sector Formats are presented below :

CD-DA Sector : 2352 Bytes

User Data

CD-ROM Sector : 2352 Bytes


Mode0 Sync User Data
Header
Mode2 12 2336
Min Sec Frame Mode
1 1 1 1

Scrambled

CD-ROM Sector : 2352 Bytes


Mode1 User Data
Sync Header EDC Space ECC
12 2048 4 8
Min Sec Frame Mode P-parity Q-parity
1 1 1 1 172 104

Scrambled

CD-ROM/XA Sector : 2352 Bytes


CD-I Mode 2
Sync User Data EDC ECC
Mode2-Form1 12
Header
2048 4
Min Sec Frame Mode FN CN SM CI FN CNSM CI P-parity Q-parity
1 1 1 1 1 1 1 1 1 1 1 1 172 104

Scrambled

CD-ROM/XA Sector : 2352 Bytes


CD-I Mode 2 User Data
Sync EDC
Mode2-Form2 12
Header
2324 4
Min Sec Frame Mode FN CN SM CI FN CNSM CI
1 1 1 1 1 1 1 1 1 1 1 1

Scrambled

Figure 11-2 Some Common CD Sector Formats

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13. PROGRAMMABLE I/O


The Programmable I/O (PIO) ports are general-purpose I/O ports communicate with external host or serve as interrupts for external
definable by the user. They can be used to gather external status host.
information, drive internal status out, control external devices, and

Register Name Reg Bits Description RW RST


I/O Direction for PIO[15:0]
GPIO_CFG 184 [15-0] 0: PIO is input rw 0
1: PIO is output
Set/Read PIO[15:0]
GPIO_STS 185 [15:0] Read: Current Input Value rw 0
Write: Set Output Value

Register Name Reg Bits Description RW RST

[15-9] Reserved.
GPIO_PINSEL 70 Pin Function Selection
[8-0] rw 0
Refer the Multi-Function Table for Detail Info

PIO Group: Dedicated PIO Total: 5


GPIO_PINSEL[3] 0 1
PIO[4] PIO[4] N.C.(Not Connected)
PIO[3] PIO[3] N.C.
PIO[2] PIO[2] N.C.
PIO[1] PIO[1] N.C.
PIO[0] PIO[0] N.C.

SPI Group: Peripheral Interface Signals Total: 3


GPIO_PINSEL[8] 0 1(Bit [0] should be 0)
MD MD PIO[8]
MC MC PIO[9]
ML ML PIO[10].

MISC MUX Total: 3


GPIO_PINSEL[6] 0 1
PIO[12] N.C PIO[12]
PIO[13] N.C. PIO[13]

GPIO_PINSEL[7] 0 1
AUD_XCK AUD_XCK PIO[14]

DSA Group: Peripheral Interface Signals Total: 3


GPIO_PINSEL [2:1] 00 01 10 11

DSA_DATA DSA_DATA CBUS_CCLK MDAT Reserved


DSA_STB DSA_STB CBUS_CDATA MCK Reserved
DSA_ACK DSA_ACK PIO[5] MLT Reserved

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Host Group: Host Interface, Peripheral Interface, Total: 10


GPIO_PINSEL[3] 0 1
NDATA[7] NDATA[7] PIO[4]
NDATA[6] NDATA[6] PIO[3]
NDATA[5] NDATA[5] PIO[2]
NDATA[4] NDATA[4] PIO[1]
NDATA[3] NDATA[3] PIO[0]

GPIO_PINSEL [5:4] 00 01 10 11

NDATA[2] NDATA[2] S0S1 S0S1 S0S1


NDATA[1] NDATA[1] SQDT SQDT SQDT
NDATA[0] NDATA[0] SQCK SQCK SQCK
NSTROBE NSTROBE SENSE SENS PIO[6]
NWRITE NWRITE PIO[7] SCLK PIO[7]

IR Group: Peripheral Interface Signals Total: 1


GPIO_PINSEL[0] 0 1
IR_OUT IR_OUT PIO[11]

14. IR INPUT/OUTPUT
There are two commonly used IR format, i.e., NEC and PHILIPS. normal command consists of pre-emble, address and data field.
The timing diagramming are listed below. These timing diagrams The parameters that are defined in the IR registers are plotted in
are extracted from the HT6221 / HOLTEK and SA3010 / PHILIPS. the diagram. The length of the data 1 is A1 while that of data 0 is
For the NEC format, two instruction commands are defined. One A0.
is normal command and the other is repeat command. The

pre-emble address data

A15 - A0 D7 - D0 D7 - D0

9ms 4.5ms
C D
0.56ms

0.56 1.68ms 0.56 0.56


ms ms ms

A1 A0

repeat

2.5
9ms ms

0.56
ms

E F G

Figure13-1 NEC signal format

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pre-emble address data

Start cntl A4 - A0 D5 - D0

1.778 1.778
ms ms
A1 A0

Figure13-2 PHILIPS signal format

The PHILIPS IR only as one format. The command consists of pre-emble, address and data fields. The length of data 1 and 0 are also
defined as A1 and A0.

14.1. IR Input

Register Name Reg Bits Description RW RST


Initial polarity of signal
[0] 0: negative
1: positive (normal)
Waveform type
IR_MISC 160 [1] 0: PHILIP format W 16’h001F
1: NEC format
Bit polarity
[2] 0: waveform of 1 and 0 is reversed
1: waveform of 0/1 is as WAVEFM registers
[7:0] wavfm_a
IR_WAVFM_AIS 161 W 16’h0D1A
[15:0] wavfm_a_i_sub
[7:0] Preamble C (NEC)
IR_PRE_CD_NEC 162 W 16’h366C
[15:8] Preamble D (NEC)
[7:0] RPT_E: NEC type repeat word
IR_RPT_EF_NEC 163 W 16’h1E6C
[15:8] RPT_F: NEC type repeat word
[7:0] RPT_G: NEC
IR_PRE_RPT_NEC 164 W 16’h1806
[15:8] wavfm_pre_rpt_sub
[2:0] PRE_NO: number of start and control bits.
[5:3] CNL_NO: number of control bits
IR_PRE_PHILIPS 165 RPT_TYPE: W 16’h0042
[6] 0: no repeat-word
1: with repeat-word
[7:0] STRT_PATT: start bit-pattern.
IR_PRE_PATT_PHILIPS 166 W 16’h0607
[15:8] CNT_PATT: control bit-pattern
IR_GUARD 167 GRD_ADDR (NEC) W 16’h0000
[0] 0: no guard band between address and data
1: guard band between address and data
[1] GRD_DATA (NEC)

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Register Name Reg Bits Description RW RST


0: no guard band between data and data
1: guard band between data and data
[15:8] duration of guard band between data and data
IR_ADDR_PATT 169 [15:0] Address patterns W 16’hAA55
IR_DATA_RECV 170 [7:0] Preamble received R
IR_CLK 172 W 16’d404
[3:0] # of address bits
[7:4] # of data bits
IR_ADDR_DATA_CONFIG 168 W 16’h057F
[9:8] # of data repetition
[10] POL_TOGGLE_DATA: toggle bit-polarity between data
[0] RX_OK: receive ok
IR_STATUS 171 R
[1] RPT_FLAG: receive repeat word

The register programming value for these two type are in the table.
Register NEC PHILIPS

MISC 0x001F 0x0019


IR_WAVFM_AIS 0x0D1A 0x0D15
IR_PRE_CD_NEC 0x366C X
IR_RPT_EF_NEC 0x1E6C X
IR_PRE_RPT_NEC 0x1806 X
IR_PRE_PHILIPS 0x002X 0x0002
IR_PRE_PATT_PHILIPS X X
IR_GUARD 0x0000 0x0000
IR_ADDR_DATA_CONFG 0x057F 0x0054

14.2. IR Output

Register Name Reg Bits Description RW RST

IROUT_PRE_CD 77
IROUT_RPT_EF 78
IROUT_STRT_G 79
IROUT_DATA_PER 156
IROUT_ADDR 157
IROUT_GUARD 158
IROUT_STATUS 159 read the transmission status of IR out
IROUT_DATA 69 IR data to be transmitted

The IR output is for the control of VCD 1.0 loader. The format must be NEC. There are reset value for all the programming registers.
No action by the user is required.

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15. HOST INTERFACE 15.1. Host Read Timing


The host interface consist of ten signals which are D7 - D0, and The following timing shows that the host write three bytes into
nstrobe / nwrite. The Mpeg chip is master and the host is slave. MPEG.
Whenever the host wants to access Mpeg, it has to read D0 - D7.
At this time, the nstrobe and nwrite are high. The following table data
defines the actions that the host can take after read.
nwrite
D7 - D0
nstrobe
MPEG nstrobe
Host
chip
nwrite
15.2. Host Write Timing
The following timing shows that the host read three bytes from
MPEG.
Value read Host action

00 Host access is prohibited data


01 Host may read
nwrite
02 Host may write (high)
03 Host may read or write
nstrobe

Register Name Reg. Bits Description RW RST


[15-8] Reserved
EPP_DATA 18
[7-0] EPP Data Port rw 0
EPP_STATUS 19 EPP Interface Control (Bit 14-11) Update
[15] 0: Disable rw 0
1: Enable
EPP Interface Function
[14] 0: Disable rw 0
1: Enable
Data Input Function
[13] 0: Disable rw 0
1: Enable
Data Output Function
[12] 0: Disable rw 0
1: Enable
NWRITE, NSTROBE sync mode
[11] 0: Disable rw 0
1: Enable
[10-6] Reserved.
Reset Input FIFO
[5] 0: Disable w 0
1: Enable
Reset Output FIFO
[4] 0: Disable w 0
1: Enable

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Register Name Reg. Bits Description RW RST


Input FIFO Full
[3] 0: No r 0
1: Yes
Input FIFO Empty
[2] 0: No r 1
1: Yes
Output FIFO Full
[1] 0: No r 0
1: Yes
Output FIFO Empty
[0] 0: No r 1
1: Yes

15.3. VFD Control

Register Name Reg. Bits Description RW RST


[15-13] Reserved.
[12-9] VFD Pin Status
Bit 12: CLK 1
Bit 11: STB r 1
Bit 10: Reserved.
Bit 9: Data 1
[8] VFD Interface Control
0: Disable rw 0
1: Enable
[7-6] Reserved.
[5-4] Clock Selection
0: 1.25 MHz
1: 938 KHz rw 0
VFD_CFG 177
2: 468 KHz
3: 250 KHz
[3-2] Polling Interval
0: Continuous
1: 256 us rw 0
2: 1 ms
3: 8 ms
[1] CLK Inversion Control
0: Disable rw 0
1: Enable
[0] STB Inversion Control
0: Disable rw 0
1: Enable
VFD_FUNC 178 [15-14] Reserved.
[13] Command Mode Ready r 0
[12] Polling Mode Ready r 0
[11-10] VFD Interface Status r 0

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Register Name Reg. Bits Description RW RST


00: Free
01: Process Read/Write Command
10: Process Polling
11: Reserved.
Command Type
00: Read
[9-8] 01: Write rw 0
10: Write Form 1
11: Reserved.
[7-5] Data Size in Command Mode rw 0
[4-2] Data Size in Polling Mode rw 0
Command Mode Control
[1] 0: Disable rw 0
1: Enable
Polling Mode Control
[0] 0: Disable rw 0
1: Enable
[15-8] Command 0 rw 0
VFD_CMD 179
[7-0] Command 1 rw 0
[15-8] Data Byte 0 rw 0
VFD_DAT0 180
[7-0] Data Byte 1 rw 0
[15-8] Data Byte 2 rw 0
VFD_DAT1 181
[7-0] Data Byte 3 rw 0
[15-8] Data Byte 4 rw 0
VFD_DAT2 182
[7-0] Data Byte 5 rw 0
[15-8] Data Byte 6 rw 0
VFD_DAT3 183
[7-0] Data Byte 7 rw 0

The timing diagrams below are extracted from data sheet µPD16312 / NEC. The VFD registers programming procedures are appended
to each diagram. Following the procedure, the user can generate the desired timing.

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CASE I If data continues

VFD_STB

VFD_DATA b0 b1 b2 b6 b7

VFD_CLK
1 2 3 7 8

CASE II

VFD_STB

VFD_DATA (in) b0 b1 b2 b3 b4 b5 b6 b7

VFD_CLK 1 2 3 4 5 6 7 8 1 2 3 4 5 6
Note
tWAIT
VFD_DATA (out)
b0 b1 b2 b3 b4 b5

A data read command is set. Data is read.

CASE 1: write one byte data


write VFD_CFG, 0x0110
VFD Interface enable, clock selection: 983 KHz
no CLK STB inversion
write VFD_DAT0, 0xXX00
XX = b7 b6 b5 b4 b3 b2 b1 b0(in binary)
write VFD_FUNC, 0x0102
command type: write, csize = 0
command mode control: enable => start the cycle
delay
wait until VFD_FUNC[10] == 0
write VFD_FUNC, 0x0000
command mode control: disable
cycle complete

CASE 2: write one byte data and then read one byte data
write VFD_CFG, 0x0110
VFD Interface enable, clock selection: 983 KHz
no CLK STB inversion
write VFD_DAT0, 0xXX00
XX = b7 b6 b5 b4 b3 b2 b1 b0(in binary)
write VFD_FUNC, 0x0002
command type: read, csize = 0
command mode control: enable => start the cycle
delay
wait until VFD_FUNC[10] == 0
read VFD_DAT0[15:8]
the read data is stored here.
write VFD_FUNC, 0x0000
command mode control: disable
cycle complete

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SPCA707A

16. MACRO COMMANDS


For the application of SPCA707A, programmers could access and application should issue an initialization macro command before it
modify most firmware options directly. However for most VCD issues the playback command. A generic control flow would look
playback applications the SPCA707A firmware also provides a like:
generic program interface for popular functions. The
programming interface covers most CDDA, VCD1.0, VCD1.1 and while (task_not_finished)
VCD2.0 playback functions. For example, play a CD track in A/V {
mode or read a specific CD sector. A generic navigator or /* issue playback_track macro-command */
specialized playback path can be built by utilizing the control PlayTrack(2);
interface.
/* execute the playback command until finished
The programming interface is consisted of macro commands. */
Generally they could be classified into 2 groups of functions, MediaMainLoop();
initialization functions and playback functions. An initialization
function is to setup the playback environment ready for playback, /* check result and change program flow */
and a playback function will execute the playback (or any other ------
specific operations) request. To achieve most functions, an }

These macro commands are listed below:


Classification Name Description

CONTROL Init() Initialize the system hardware and software interface


Abort() Terminate current playback task
Sync() Wait for last playback finish
Pause() Pause current playback
Freeze() Freeze video playback
Continue() Continue paused/frozen playback
PLAYBACK PlayTrack() Initialize playback of a general track
PlayTrackPreview() Initialize playback of a general track using preview (vcd 2.0 only)
PlayEntry() Initialize playback from a PSD ENTRY (vcd 2.0 only)
PlaySegment() Initialize playback from a PSD SEGMENT (vcd 2.0 only)
PlayMP3() Initialize MP3 playback
PlayRomSlide() Initialize ROM-based video-bistream playback
DisplayPreviewBackground() Initialize preview background
OSD OSD_OnOff() Turn on/off specific OSD regions
SetOsdColor() Set OSD display color
CD OPERATION ReadCD() Initialize CD reading operation
ReadCDMSF() Initialize CD reading operation (MSF addressing)
MAIN MediaMainloop() Playback main path

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MACRO MACRO

Init() Sync()

Parameter Category
None CONTROL

Description Parameter
Init() will reset system to a known state. None

Applicable Description
Always Sync() is used to wait until a locked state of system when issue
command will be safe.

Applicable
Always

MACRO MACRO

Abort() Pause()

Parameter Category
None CONTROL

Description Parameter
Abort() will terminate current playback process. None

Applicable Description
Always Pause() command stops the current program playback. After
receive this command the A/V decoder would stop decoding
incoming bitstream. If playing from CD kit, the A/V decoder also
issue CDKIT to pause.

Applicable
CDDA, VCD1.0, VCD1.1 and VCD2.0.

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MACRO MACRO

Continue() Play()

Category Category
CONTROL PLAYBACK

Parameter Parameter
None None

Description Description
Continue() undo the effect of command Pause() and Freeze(). Play() will instruct the VCD A/V decoder to prepare for LINEAR
If A/V decoder is not paused nor frozen, this command has no PLAYBACK for a program.
effect on the system.

Applicable
CDDA, VCD1.0, VCD1.1 and VCD2.0.

MACRO MACRO

Freeze() PlayTrack(Track)

Category Category
CONTROL PLAYBACK

Parameter Parameter
None Name Type Description

Description Track BYTE Specified Track number (1-99)


Freeze() will instruct the A/V decoder stop video decoding. The
Description
overall effect will look like the video program is frozen and only
PlayTrack() will instruct the VCD A/V decoder to prepare for a
audio playback carry on.
CD track. Track format will be decided from current CD format and
Applicable TOC content of this track.
Motion picture sequences within VCD1.0, VCD1.1 and VCD2.0.
Applicable
CDDA, VCD1.0, VCD1.1, VCD2.0

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MACRO

PlayTrackPreview(x, y, Track)

Category
PLAYBACK

Parameter
Name Type Description

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MACRO MACRO

PlayRomSlide(RomAddr) OSD_OnOff(OnOff)

Category Category
PLAYBACK CONTROL

Parameter Parameter
Name Type Description Name Type Description

RomAddr UINT32 Specified ROM bitstream address OnOff BYTE 0 to turn off OSD
other to turn on OSD
Description
PlayRomSlide() will instruct the VCD A/V decoder to prepare Description
for video-elementary bistream playback, where the bitstream This command OSD_OnOff()instruct microcode of the A/V
comes from ROM embedded pattern. decoder to turn OSD ON and OFF. Before switch OSD on you

Applicable should initialize OSD regions.

Always Applicable
Always

MACRO MACRO

DisplayPreviewBackground() SetOsdColor(region,color,Y,Cr,Cb)

Category Category
FRAMEBUFFER CONTROL

Parameter Parameter
None Name Type Description
Description region BYTE OSD region selected
DisplayPreviewBackground() will configure the memory 0xFF write to all OSD regions.
mapping into 9-digest PREVIEW and clear the background. After color BYTE Color index of the specified OSD region
this operation (0-3 for 4-color OSD)

Applicable Y BYTE Y component of the color (0-255)

Always Cr BYTE Cr component of the color (0-255)


Cb BYTE Cb component of the color (0-255)

Description
SetOsdColor() will change the color of a specified OSD (On
Screen Display) region according the (YCbCr) value specified.

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SPCA707A

Reference Value MACRO


Color Y Cr Cb ReadCDMSF(DST,MSF,SKIP,SIZE)
White 0xEB 0x80 0x80
Category
Yellow 0xA2 0x8E 0x2C
CD OPERATION
Cyan 0x83 0x2C 0x9C
Parameter
Green 0x70 0x3A 0x48
Name Type Description
Magenta 0x54 0xC6 0xB8
Red 0x41 0xD4 0x64 DST UINT32 Memory address pointer to store the

Blue 0x23 0x72 0xD4 result

Black 0x10 0x80 0x80 MSF UINT32 Packed Red-book MM:SS:FF CDROM
address of the starting sector to be read
SKIP UINT32 Bytes to skip before storing into memory
SIZE UINT32 Bytes to read

Description
ReadCDMSF() will try to read a specified CDROM address into a
memory portion. The memory address is assigned in RISC
memory space. After the command issued, the A/V decoder will
try to seek to the specified CDROM position and wait for the
starting sector. CDROM data is extracted from CDROM/XA
format and store to the memory position.

Applicable
Any CD format conforms to CDROM (Yellow book) or
CDROM/XA.

MACRO MACRO

SetOsdColorDirect(region,color,value) ReadCD(DST,EXT,SKIP,SIZE)

Category Category
CONTROL CD OPERATION

Parameter Parameter
Name Type Description Name Type Description

region BYTE OSD region selected DST UINT32 Memory address pointer to store the
0xFF write to all OSD regions. result
color BYTE Color index of the specified OSD region EXT UINT32 High-Sierra CDROM address of the
(0-3 for 4-color OSD) starting sector to be read
value UINT16 value of color entry SKIP UINT32 Bytes to skip before storing into memory
SIZE UINT32 Bytes to read
Description
SetOsdColorDirect() will set the color of a specified OSD (On Description
Screen Display) region according to the color value. ReadCD() acts just like ReadCDMSF(). Except that the CDROM
address is in High-Sierra CDROM format.

Applicable
see ReadCDMSF()

© Sunplus Technology Co., Ltd. 28 AUG. 21, 2001


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SPCA707A

17. ELECTRICAL SPECIFICATIONS


17.1. Operating Conditions
Table 16-1: Absolute Maximum Ratings
Symbol Parameter Rating Units

VCCKP, VCCAP Power Supply -0.3 to 3.6 V


VCC5OP, VCC5IP, VCCTVP Power Supply -0.3 to 6.0 V
TSTG Storage Temperature -40 to 125 ℃
TSOLDER Soldering Temp. (Max. Time) 240 (for 5 Sec. Max.) ℃

Table 16-2: Recommended Operating Conditions


Symbol Parameter Min. Typ. Max. Units

VCCKP, VCCAP Power Supply 3.0 3.3 3.6 V


VCC5OP, VCC5IP, VCCTVP Power Supply 4.75 5.0 5.25 V
VIN Input Voltage 0 - 5.0 V
TOPR Operating Temperature 0 - 70 ℃
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional
operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Table 16-3-1: DC Characteristics


Conditions: I/O power VDD - VSS = 5.0V, Kernel power VDD - VSS = 3.0V, VCCTVP = 3.0V, TA = 25℃, MCLK = 27MHz

Limit
Characteristics Symbol Unit Conditions
Min. Typ. Max.

I/O Operating Voltage VDD 4.5 5.0 5.5 V Kernel Voltage @ 3.34V
Kernel Operating Voltage VDD 2.8 3.0 4.0 V I/O Voltage @ 5.0V
Operating Current IOP - 280 - mA Kernel = 3.0V
Input High Level (ROM, CD, Video) VIH 2.2 - - V
Input Low Level (ROM, CD, Video) VIL - - 0.8 V
Output High I
IOH - -8.0 - mA VOH = 4.2V
(Dram, ROM, Audio, Host, Video)
Output Sink I
IOL - 8.0 - mA VOL = 0.8V
(Dram, ROM, Audio, Video)
Output Capacitance COUT - - 10 pF

Table 16-3-2
Conditions: I/O power VDD - VSS = 5.0V, Kernel power VDD - VSS = 3.0V, VCCTVP = 5.0V, TA = 25℃, MCLK = 27MHz

Limit
Characteristics Symbol Unit Conditions
Min. Typ. Max.

Input High Level (Video) VIH 2.2 - - V


Input Low Level (Video) VIL - - 0.8 V
Output High I (Video) IOH - -8.0 - mA VOH = 4.2V
Output Sink I (Video) IOL - 8.0 - mA VOL = 0.8V

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SPCA707A

17.2. AC Timing Characteristics


17.2.1. DRAM interface timing diagram

CLK
t15
t25 t26 t14
RAS_B
t8 t12 t13 t7
t6
CAS_B
t20 t28

t11 t9 t24
t10 t19
t3
DA[9:0] row addr. col. addr. col. addr. row addr. col. addr. col. addr.

t16 t17
WE_B

t4 t5
t2 t9
DD[15:0] valid valid
t1

17.2.2. DRAM interface timing table

Limit
Time Description Units
Min. Typ. Max.

t1 Read data setup time before CAS_B 5.0 10 - ns


t2 Read data hold time after CAS_B 5.0 27 - ns
t3 Row addr setup time 5.0 35 - ns
t4 Write data setup time before CAS_B low 5.0 20 - ns
t5 Write data hold time after CAS_B low 10 15 - ns
t6 RAS_B hold time after CAS_B low 24 32 - ns
t7 Read command hold time after RAS_B 24 60 - ns
t8 Read command setup time to CAS_B low 24 115 - ns
t9 Col address setup time to CAS_B low 5.0 21 - ns
t10 Col address hold time after CAS_B low 15 17 - ns
t11 Row address hold time from RAS_B low 10 35 - ns
t12 CAS_B low time 17 18 - ns
t13 CAS_B high time 17 20 - ns
t14 RAS_B high time 50 57 - ns
t15 RAS_B low time 50 500 5000 ns
t16 Write setup time to CAS_B 10 57 - ns
t17 Write command hold time from CAS_B low 24 35 - ns
t19 Col address to CAS_B high 30 35 - ns
t20 RAS_B to CAS_B delay 20 55 60 ns
t24 Col address to RAS_B high 40 55 - ns
t25 RAS_B low to CAS_B high 72 75 - ns
t26 RAS_B hold time from CAS_B precharge 48 52 - ns
t28 Read command hold time from CAS_B 0 75 - ns

© Sunplus Technology Co., Ltd. 30 AUG. 21, 2001


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SPCA707A

17.2.3. DRAM refresh timing diagram

CLK
t15 t14
RAS_B
t21 t23
t22
CAS_B

t12 t13

17.2.4. DRAM interface refresh timing table

Limit
Time Description Units
Min. Typ. Max.

t12 CAS_B low time 24 130 - ns


t13 CAS_B high time 17 20 - ns
t14 RAS_B high time 50 57 - ns
t15 RAS_B low time 72 90 5000 ns
t21 CAS_B setup time to RAS_B(refresh ) 24 35 - ns
t22 CAS_B hold time from RAS_B(refresh) 72 95 - ns
t23 RAS_B to CAS_B delay(refresh) 0 23 - ns

17.2.5. ROM read timing diagram

ROM_ADDR[17:0]

t
ROM_DATA[7:0]

17.2.6. ROM read timing table

Limit
Time Description Units
Min. Typ. Max.

t ROM_DATA ready from ROM_ADDR - 50 75 (350) ns

17.2.7. Host read timing diagram

t0 t1

nstrobe

t2 t3
data

t4
nwrite

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SPCA707A

17.2.8. Host write timing diagram

nstrobe

t5
data

nwrite

17.2.9. Host interface timing table

Limit
Time Description Units
Min. Typ. Max.

t0 nstrobe low time 20 - - ns


t1 nstrobe high time 10 - - ns
t2 data setup time 43 - - ns
t3 data hold time from nstrobe 48 - - ns
t4 nwrite delay from nstrobe 88 - - ns
t5 data hold time from nstrobe 50 - - ns

17.2.10. CD input timing for CD_BCK rising edge diagram

t1 t2
CD_BCK

CD_LRCK t3 t5

CD_DATA t4 t6

17.2.11. CD interface timing table

Limit
Time Description Units
Min. Typ. Max.

t1 CD_BCK high pulse width 100 235 - ns


t2 CD_BCK low pulse width 100 235 - ns
t3 CD_LRCK setup 10 235 - ns
t4 CD_DATA setup 10 235 - ns
t5 CD_LRCK hold 10 235 - ns
t6 CD_DATA hold 10 235 - ns

© Sunplus Technology Co., Ltd. 32 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

17.2.12. Audio interface timing diagram

AUD_XCK

AUD_BCK t1

AUD_LRCK t2

AUD_DATA t2

17.2.13. Audio interface timing table

Limit
Time Description Units
Min. Typ. Max.

t1 AUD_XCK high to AUD_BCK valid 1.0 2.0 5.0 ns


t2 AUD_BCK low to AUD_LRCK,AUD_DATA valid 1.0 2.0 5.0 ns

17.2.14. 8-bit video out timing diagram

t0 t1 t2

CLK27_OUT
t3
DATA_TV

HSYNC_IN/ t5 t7
VSYNC_IN
t4 t6

17.2.15. Video interface timing table

Limit
Time Description Units
Min. Typ. Max.

T0 CLK_OUT27 clock period 35.2 37.5 38.9 ns


T1 CLK_OUT27 clock high 16 18 20 ns
T2 CLK_OUT27 clock low 16 18 20 ns
T3 CLK_OUT27 high to DATA_TV valid - 19 20 ns
T4 CLK_OUT27 high to SYNC control low 3.0 9.0 25 ns
T5 SYNC control low to CLK_OUT27 high 3.0 30 - ns
T6 CLK_OUT27 high to SYNC control high - 9.0 10 ns
T7 SYNC control, high to CLK_OUT27 low 5.0 28 - ns

© Sunplus Technology Co., Ltd. 33 AUG. 21, 2001


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SPCA707A

17.2.16. RESET and clock signals timing table

RESET_B t1

RESET_B Signal Timing

t2
t3
CLK_OUT27 t4

CLK_OUT27 Signal Timing

17.2.17. RESET and clock signals timing diagram

Limit
Time Description Units
Min. Typ. Max.

t1 RESET_B width 250 - - ns


t2 CLK_OUT27 period 35.2 37 38.9 ns
t3 CLK_OUT27 high width 16 20 21 ns
t4 CLK_OUT27 low width 16 17 21 ns

17.3. The Relationship between Voltage (V) and the Current (mA):

400
Current (mA)

300

200

100

0
2.8 3 3.2 3.4 3.6 3.8 4
Voltage (V)

Note: Variation of Kernel voltage. I/O Voltage is @ 5.0V.

© Sunplus Technology Co., Ltd. 34 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

18. APPLICATION CIRCUITS


18.1. Application Circuit - (1)

© Sunplus Technology Co., Ltd. 35 AUG. 21, 2001


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SPCA707A

18.2. Application Circuit - (2)

© Sunplus Technology Co., Ltd. 36 AUG. 21, 2001


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SPCA707A

18.3. Application Circuit - (3)

© Sunplus Technology Co., Ltd. 37 AUG. 21, 2001


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SPCA707A

18.4. Application Circuit - (4)

(1) VCC --> digital 5V (1) GND --> digital ground


(2) VCC3 --> digital 3V (2) AGND --> audio ground
(3) PLLVCC3 --> analog 3V (3) VGND --> video ground
(4) 3.3V --> digital 3.3V
(5) AVCC --> analog 5V
(6) AVCC3 --> analog 3.3V

© Sunplus Technology Co., Ltd. 38 AUG. 21, 2001


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SPCA707A

19. PACKAGE/PAD LOCATIONS


19.1. Package Outline Dimensions

© Sunplus Technology Co., Ltd. 39 AUG. 21, 2001


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SPCA707A

20. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders. Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits
illustrated in this document are for reference purposes only.

© Sunplus Technology Co., Ltd. 40 AUG. 21, 2001


Proprietary & Confidential Version: 1.0
SPCA707A

21. REVISION HISTORY

Date Revision # Description Page

AUG. 21, 2001 0.1 Original 41

© Sunplus Technology Co., Ltd. 41 AUG. 21, 2001


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