Professional Documents
Culture Documents
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPCA707A
Table of Contents
PAGE
CD-DSP TV Encoder TV
Built-in Programmable Karaoke processor with
─ Key control for MPEG audio layer1, layer2 and layer3
SPCA707A ─ Programmable wide sound
up(optional)
Stereo
Audio DAC
Audio
Front
Panel
Function
Keys Software Drivers
─ Drivers for CD-I (green book, white book), Karaoke CD,
Figure 1-1 VCD Boom Box System Block Diagram Video CD 2.0/1.1 and Audio CD (CD-DA)
─ Preview
─ User definable features
─ RISC game software
─ ZoomPro: Programmable video Zoom-in/out
─ ImagePro: Programmable digital image processing
ROM_ADDR9
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
AUD_LRCK
AUD_DATA
PAL_NTSC
HSYNC_IN
DATA_TV0
DATA_TV1
DATA_TV2
DATA_TV3
DATA_TV4
DATA_TV5
DATA_TV6
DATA_TV7
VSYNC_IN
AUD_EMP
AUD_BCK
AUD_XCK
CD_DATA
CD_LRCK
CK27OUT
GND5OP
VCC5OP
VCCTVP
GNDIKP
VCCKP
RESET_B
VCC5IP
103
104
64
63
ROM_ADDR5
ROM_ADDR4
Bringing this pin high will put the chip in test mode.
NDATA0 105 62 ROM_ADDR3
SPCA707A
NDATA5 112 55 ROM_DATA1
NDATA6 113 54 ROM_DATA2
NDATA7
NSTROBE
114
115
53
52
ROM_DATA3
ROM_DATA4
Bringing this pin high will put the chip in bist test mode.
MD 116 51 ROM_DATA5
MC
NWRITE
117
118
50
49
ROM_DATA6
ROM_DATA7 This pin should normally be low.
VFD_DATA 119 48 DA0
VFD_CLK 120 47 DA1
VFD_STB
IR_IN
121
122
46
45
VCC5IP
DA2
RESET_B Hardware reset Input
IR_OUT 123 44 GNDIKP
DSA_ACK
DSA_DATA
124
125
126
43
42
DA3
VCCKP This signal is active low and must be active for at least 25
DSA_STB 41 DA4
VCC5OP 127 40 DA5
GND5OP 128 39 DA6
CLK27OUT clock cycles. After reset, the SPCA707A will be
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD15
DD14
DD13
DD12
DD11
DD10
DD9
DD8
RAS_B0
RAS_B1
DA9
DA8
DA7
VCCKP
GNDIKP
VCCAP
TEST_MODE
GNDAP
BIST_MODE
SCAN_ENABLE
WE_B
VCCKP
CAS_B
GNDIKP
VCC5OP
GND5OP
CLKIO
clock or be AUD_XCK divided by 8. It can be either 48 or Ack signal for DSA interface
AUD_LRCK Audio left/right clock Output Data signal for DSA interface.
This pin is used as the Left/Right data channel indicator. DSA_STB Strobe signal Bidirectional
AUD_DATA Audio data bus Output Strobe signal for DSA interface.
This pin is used as the serial audio data clocked out relative IR_IN IR input Input
to AUD_BCK. IR input pin. This input supports both NEC and Philips
AUD_EMP Emphasis control Output format IR signal.
This signal is used to control the de-emphasis circuitry of the IR_OUT IR output pin Output
audio output DACs. In CD-DA pass-through mode, this IR output pin.
output follows the state of the CD_EMP signal; when in VCD
mode, this pin follows the LSB of the emphasis field of the
MPEG-1 audio header.
STC - System Time Clock reader, as the time master, follow the synchronization guidelines
DTS - Decode Time Stamp 1). Initialize the STC to the first SCR received.
PTS - Presentation Time Stamp 2). Set the STC to run (incrementing at 90KHz).
STD - System Target Decoder (ideal decoder) 3). Maintain the STC by updating it with SCR values received.
PU - Presentation Unit 4). Video presentations are made when the video PTS==STC.
AU - Access Unit 5). Audio presentations are made when the audio PTS==STC.
5.2.1. System time clock (STC) 1). Initialize the STC to the first SCR received.
2). Set the STC to run (incrementing at 90KHz)
The System Time Clock is the main clock counter used for all time
3). Maintain the STC by updating it with Audio PTS values
reference. The STC is a 33-bit counter based on a 90kHz clock.
received.
4). Video presentations are made when the video PTS==STC.
5.2.2. System clock reference (SCR)
5). Use SRC values to determine if the DSM data rate is correct.
The System Clock Reference is a time stamp in the MPEG system
stream. The SCR value represents the time when the last byte of
the SCR field leaves the encoder. For the decoder, this value is
6. VIDEO DECODER
used to initialize the STC and for updating the STC when using
The Video Decoder is an MPEG 1 video decoder optimized for
the DSM as time master.
minimum size while conforming to ISO 11172 standard. The
module will read an MPEG 1 video stream in and continuously
5.2.3. Decode time stamp (DTS)
generate frames in external DRAM. The frames will then be
The Decode Time Stamp value represents the time when an
processed by a video processor for final display. The Video
access unit should be ready for decoding. For the Audio stream,
Decoder performs the following functions:
the DTS==PTS so it is not used. In the Video stream, the DTS
1). Huffman Decoding
for I-Frames and P-Frames are nominally equal to the PTS value
2). Dequantization
minus the number of picture periods of video reordering delay
3). Inverse Cosine Transform
multiplied by the picture period, in units of the 90KHz STC.
4). Motion Vector Generator
5). Address Generator
5.2.4. Presentation time stamp (PTS)
6). Motion Compensation
A Presentation Time Stamp represents the time at which a
presentation unit should be displayed. In the case of Audio, this
is the time when the decoder should begin the playback of an 7. VIDEO PROCESSOR
audio frame. In the case of Video, this is the time when the
The Video Processor & Output Interface is responsible for taking
corresponding video frame should be displayed.
decompressed data from memory (DRAM), and process the data
into raster (interlaced or non-interlaced) video. Some of the
5.3. Time Master
important processing functions include horizontal/vertical
A decoding system, including all of the synchronized decoders and interpolation, filtering and clipping.
the source of the coded data, must have exactly one independent
time master. The SPCA707A chip allows the microcode to use The video processing functions performed by the video processor
either the DSM or Audio block as the time master. The time include vertical interpolation, horizontal interpolation, horizontal
master selection depends on how the STC is updated. filtering, proprietary high-resolution functions and clipping
functions. Video interpolations allow for small SIF images of
MPEG video decoding to be enlarged without blocking or
discontinuity effects. The final display of the SIF image will have 7.2. Usage for 8-Bit Video Interface
smooth transitions in both horizontal and vertical directions. The SPCA707A co-operates with master-mode TV-encoders.
Horizontal filtering will also be performed to reduce any aliasing VSYNC_IN and HSYNC_IN signals come from a standard
effects. The proprietary high-resolution functions are used to TV-encoder(as in figure 5-2). The SPCA707A will lock to these
maintain quality in the 704 X 576 high resolution still image mode. reference timing and put the data onto the DATA_TV[7:0]. Data
The Clipping function can be turned on to allow for compatibility on the DATA_TV[7:0] is multiplexed data of 4_1_1 format. The
with CCIR 601 specifications. data is sequenced out (Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3..) after
HSYNC_IN. Detailed timing diagram of TV encoder interface is
Active
Video Active presented in Figure 5-3 below:
OSD
Display
Output CLK27OUT
HSYNC_IN
1-Blend DATA_TV(7:0) Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11
8. ON SCREEN DISPLAY
OSD Blend
The on screen display feature is intended to display a rectangular
area which can be a graphic or text overlay the decoded video on
Figure 5-1 Video Processor Output Mixer
the screen. There are flexible numbers of rectangular regions
that can be in a field and each region consists of a region header
7.1. Video Processor Interface and data. Host or RISC will program these headers and data
The I/O interface to the video processor is defined below: then store to the DRAM for various application purpose. OSD
HSYNC_IN Horizontal sync Input decoder reads the header and data, then interpreted as graphic
Horizontal sync signal input from TV encoder. data and overlaid with video for output to the display device.
VSYNC_IN Vertical sync Input There are headers in each region and they can give the OSD
Vertical sync signal input from TV encoder. decoder information to interpret the succeeding bit mapped data.
DATA_TV(7:0) Video out Output
These pins form the video data output bus. It contains 8.1. Link Address
multiplexed Luminance and Chrominance video data.
This address shows the address of next OSD region and OSD
PAL_NTSC PAL/NTSC control Output
decoder use it to next OSD block in the DRAM. Figure 6-1
This pin control the PAL/NTSC mode of TV encoder.
shows the linked list structure.
CLK27OUT 27 MHz clock Output
27 MHz video pixel clock output to the TV encoder signal.
OSD1
OSD1 Block
The recommended interface scheme is shown in Figure 5-1
OSDm
below:
OSDn Block
OSDn
VSYNC_IN
HSYNC_IN 8.2. Start Row Address
This address indicates the start vertical address of bitmapped data
Figure 5-2 Video Processor Interface which will be begun to display on the screen.
This parameter gives the width of the associated OSD region. AUD_LRCK Audio Left/Right clock Output
Left/Right data channel indicator.
AUD_BCK
AUD_DATA 0 15 14 1 0 15 14 1 0 15
The Audio Output Interface takes PCM data from memory (DRAM) BCK = 32 x Fs
AUD_LRCK
PCM audio data will be in alternating left/right channel format if the AUD_DATA 0 15 14 1 0 15 14 1 0 15 14
BCK = 48 x Fs
CLK
Software usage
RAS_B
CAS_B
EABYA
CLK Audio Channel Buffer
RAS_B REF0_LUMA
REF1_CHROMA
Figure 10-2 DRAM Write Timing
Reference Frame 1 - (Chroma)
BIDIR_LUMA
BF - (Luma)
CLK
RAS_B BIDIR_CHROMA
BF - (Chroma)
CAS_B
Figure 10-3 DRAM Refresh Timing Figure 10-4 DRAM Memory Map
12. CD INTERFACE
The CD interface is a simple serial interface for standard Notice that the preprocessed serial data can be routed directly to
CD-DSPs. Serial data from the CD-DSP is shifted into the the Audio output stage for CD-DA format data or stored in DRAM
SPCA707A, preprocessed by the CD interface module, then for post-processing.
written to DRAM for post-processing by the RISC processor.
Since post-processing is accomplished by the RISC processor, the The CD interface is composed of the following signals:
data stream can be in any format. For example CD-DA,
CD-ROM, CD-ROM/XA, CD-I, MPEG1 system streams, MPEG1 CD_DATA CD serial data Input
video streams and MPEG1 audio streams. Note that for the The serial data input from the CD-DSP.
CD-DA format, since no post-processing is necessary, the serial CD_LRCK CD Left/Right Clock Input
data can be routed directly to the audio DACs. CD_LRCK provides 16-bit word synchronization to the
SPCA707A and has several programmable features, such as
The RISC processor and dedicated hardware is responsible for polarity, delay and pulse mode.
the following CD data stream post-processing functions when the CD_BCK CD Bit Clock Input
data format is not CD-DA: The CD_BCK is the CD-Decoder bit clock. The SPCA707A
can accept multiple BCK rates. The CD-BCK can be set to
1). Real-time parsing for Mode 2 form 2 sectors. multiple rates as in Table 11-1.
2). Real-time parsing for Mode 1 and Mode 2 form 1 sectors
(including error correction when not decoding MPEG). The CD input format can be selected by several programmable
3). Real-time processing of Mode 0 and skipping to next sector. control bits. Six common CD data formats are presented in Table
4). Q-erasure correction, P-erasure correction and P-error check. 11-2.
1 32 MSB Right 1
2 32 MSB Left 0
3 24 MSB Right 1
4 24 LSB Right 0
5 24 MSB Right 1
6 16 MSB Left 1
Functional timing diagrams of the above six formats are detailed below:
32-bit BCK, MSB First, Right Channel Low, Data latch timing high
32-bit BCK, MSB First, Left Channel Low, Data latch timing low
24-bit BCK, MSB First, Right Channel Low, Data latch timing high
24-bit BCK, LSB First, Right Channel Low, Data latch timing low
24-bit BCK, MSB First, Right Channel Low, Data latch timing high (Note: no C2P0 for this format)
16-bit BCK, MSB First, Left Channel Low, Data latch timing high
User Data
Scrambled
Scrambled
Scrambled
Scrambled
[15-9] Reserved.
GPIO_PINSEL 70 Pin Function Selection
[8-0] rw 0
Refer the Multi-Function Table for Detail Info
GPIO_PINSEL[7] 0 1
AUD_XCK AUD_XCK PIO[14]
GPIO_PINSEL [5:4] 00 01 10 11
14. IR INPUT/OUTPUT
There are two commonly used IR format, i.e., NEC and PHILIPS. normal command consists of pre-emble, address and data field.
The timing diagramming are listed below. These timing diagrams The parameters that are defined in the IR registers are plotted in
are extracted from the HT6221 / HOLTEK and SA3010 / PHILIPS. the diagram. The length of the data 1 is A1 while that of data 0 is
For the NEC format, two instruction commands are defined. One A0.
is normal command and the other is repeat command. The
A15 - A0 D7 - D0 D7 - D0
9ms 4.5ms
C D
0.56ms
A1 A0
repeat
2.5
9ms ms
0.56
ms
E F G
Start cntl A4 - A0 D5 - D0
1.778 1.778
ms ms
A1 A0
The PHILIPS IR only as one format. The command consists of pre-emble, address and data fields. The length of data 1 and 0 are also
defined as A1 and A0.
14.1. IR Input
The register programming value for these two type are in the table.
Register NEC PHILIPS
14.2. IR Output
IROUT_PRE_CD 77
IROUT_RPT_EF 78
IROUT_STRT_G 79
IROUT_DATA_PER 156
IROUT_ADDR 157
IROUT_GUARD 158
IROUT_STATUS 159 read the transmission status of IR out
IROUT_DATA 69 IR data to be transmitted
The IR output is for the control of VCD 1.0 loader. The format must be NEC. There are reset value for all the programming registers.
No action by the user is required.
The timing diagrams below are extracted from data sheet µPD16312 / NEC. The VFD registers programming procedures are appended
to each diagram. Following the procedure, the user can generate the desired timing.
VFD_STB
VFD_DATA b0 b1 b2 b6 b7
VFD_CLK
1 2 3 7 8
CASE II
VFD_STB
VFD_DATA (in) b0 b1 b2 b3 b4 b5 b6 b7
VFD_CLK 1 2 3 4 5 6 7 8 1 2 3 4 5 6
Note
tWAIT
VFD_DATA (out)
b0 b1 b2 b3 b4 b5
CASE 2: write one byte data and then read one byte data
write VFD_CFG, 0x0110
VFD Interface enable, clock selection: 983 KHz
no CLK STB inversion
write VFD_DAT0, 0xXX00
XX = b7 b6 b5 b4 b3 b2 b1 b0(in binary)
write VFD_FUNC, 0x0002
command type: read, csize = 0
command mode control: enable => start the cycle
delay
wait until VFD_FUNC[10] == 0
read VFD_DAT0[15:8]
the read data is stored here.
write VFD_FUNC, 0x0000
command mode control: disable
cycle complete
MACRO MACRO
Init() Sync()
Parameter Category
None CONTROL
Description Parameter
Init() will reset system to a known state. None
Applicable Description
Always Sync() is used to wait until a locked state of system when issue
command will be safe.
Applicable
Always
MACRO MACRO
Abort() Pause()
Parameter Category
None CONTROL
Description Parameter
Abort() will terminate current playback process. None
Applicable Description
Always Pause() command stops the current program playback. After
receive this command the A/V decoder would stop decoding
incoming bitstream. If playing from CD kit, the A/V decoder also
issue CDKIT to pause.
Applicable
CDDA, VCD1.0, VCD1.1 and VCD2.0.
MACRO MACRO
Continue() Play()
Category Category
CONTROL PLAYBACK
Parameter Parameter
None None
Description Description
Continue() undo the effect of command Pause() and Freeze(). Play() will instruct the VCD A/V decoder to prepare for LINEAR
If A/V decoder is not paused nor frozen, this command has no PLAYBACK for a program.
effect on the system.
Applicable
CDDA, VCD1.0, VCD1.1 and VCD2.0.
MACRO MACRO
Freeze() PlayTrack(Track)
Category Category
CONTROL PLAYBACK
Parameter Parameter
None Name Type Description
MACRO
PlayTrackPreview(x, y, Track)
Category
PLAYBACK
Parameter
Name Type Description
MACRO MACRO
PlayRomSlide(RomAddr) OSD_OnOff(OnOff)
Category Category
PLAYBACK CONTROL
Parameter Parameter
Name Type Description Name Type Description
RomAddr UINT32 Specified ROM bitstream address OnOff BYTE 0 to turn off OSD
other to turn on OSD
Description
PlayRomSlide() will instruct the VCD A/V decoder to prepare Description
for video-elementary bistream playback, where the bitstream This command OSD_OnOff()instruct microcode of the A/V
comes from ROM embedded pattern. decoder to turn OSD ON and OFF. Before switch OSD on you
Always Applicable
Always
MACRO MACRO
DisplayPreviewBackground() SetOsdColor(region,color,Y,Cr,Cb)
Category Category
FRAMEBUFFER CONTROL
Parameter Parameter
None Name Type Description
Description region BYTE OSD region selected
DisplayPreviewBackground() will configure the memory 0xFF write to all OSD regions.
mapping into 9-digest PREVIEW and clear the background. After color BYTE Color index of the specified OSD region
this operation (0-3 for 4-color OSD)
Description
SetOsdColor() will change the color of a specified OSD (On
Screen Display) region according the (YCbCr) value specified.
Black 0x10 0x80 0x80 MSF UINT32 Packed Red-book MM:SS:FF CDROM
address of the starting sector to be read
SKIP UINT32 Bytes to skip before storing into memory
SIZE UINT32 Bytes to read
Description
ReadCDMSF() will try to read a specified CDROM address into a
memory portion. The memory address is assigned in RISC
memory space. After the command issued, the A/V decoder will
try to seek to the specified CDROM position and wait for the
starting sector. CDROM data is extracted from CDROM/XA
format and store to the memory position.
Applicable
Any CD format conforms to CDROM (Yellow book) or
CDROM/XA.
MACRO MACRO
SetOsdColorDirect(region,color,value) ReadCD(DST,EXT,SKIP,SIZE)
Category Category
CONTROL CD OPERATION
Parameter Parameter
Name Type Description Name Type Description
region BYTE OSD region selected DST UINT32 Memory address pointer to store the
0xFF write to all OSD regions. result
color BYTE Color index of the specified OSD region EXT UINT32 High-Sierra CDROM address of the
(0-3 for 4-color OSD) starting sector to be read
value UINT16 value of color entry SKIP UINT32 Bytes to skip before storing into memory
SIZE UINT32 Bytes to read
Description
SetOsdColorDirect() will set the color of a specified OSD (On Description
Screen Display) region according to the color value. ReadCD() acts just like ReadCDMSF(). Except that the CDROM
address is in High-Sierra CDROM format.
Applicable
see ReadCDMSF()
Limit
Characteristics Symbol Unit Conditions
Min. Typ. Max.
I/O Operating Voltage VDD 4.5 5.0 5.5 V Kernel Voltage @ 3.34V
Kernel Operating Voltage VDD 2.8 3.0 4.0 V I/O Voltage @ 5.0V
Operating Current IOP - 280 - mA Kernel = 3.0V
Input High Level (ROM, CD, Video) VIH 2.2 - - V
Input Low Level (ROM, CD, Video) VIL - - 0.8 V
Output High I
IOH - -8.0 - mA VOH = 4.2V
(Dram, ROM, Audio, Host, Video)
Output Sink I
IOL - 8.0 - mA VOL = 0.8V
(Dram, ROM, Audio, Video)
Output Capacitance COUT - - 10 pF
Table 16-3-2
Conditions: I/O power VDD - VSS = 5.0V, Kernel power VDD - VSS = 3.0V, VCCTVP = 5.0V, TA = 25℃, MCLK = 27MHz
Limit
Characteristics Symbol Unit Conditions
Min. Typ. Max.
CLK
t15
t25 t26 t14
RAS_B
t8 t12 t13 t7
t6
CAS_B
t20 t28
t11 t9 t24
t10 t19
t3
DA[9:0] row addr. col. addr. col. addr. row addr. col. addr. col. addr.
t16 t17
WE_B
t4 t5
t2 t9
DD[15:0] valid valid
t1
Limit
Time Description Units
Min. Typ. Max.
CLK
t15 t14
RAS_B
t21 t23
t22
CAS_B
t12 t13
Limit
Time Description Units
Min. Typ. Max.
ROM_ADDR[17:0]
t
ROM_DATA[7:0]
Limit
Time Description Units
Min. Typ. Max.
t0 t1
nstrobe
t2 t3
data
t4
nwrite
nstrobe
t5
data
nwrite
Limit
Time Description Units
Min. Typ. Max.
t1 t2
CD_BCK
CD_LRCK t3 t5
CD_DATA t4 t6
Limit
Time Description Units
Min. Typ. Max.
AUD_XCK
AUD_BCK t1
AUD_LRCK t2
AUD_DATA t2
Limit
Time Description Units
Min. Typ. Max.
t0 t1 t2
CLK27_OUT
t3
DATA_TV
HSYNC_IN/ t5 t7
VSYNC_IN
t4 t6
Limit
Time Description Units
Min. Typ. Max.
RESET_B t1
t2
t3
CLK_OUT27 t4
Limit
Time Description Units
Min. Typ. Max.
17.3. The Relationship between Voltage (V) and the Current (mA):
400
Current (mA)
300
200
100
0
2.8 3 3.2 3.4 3.6 3.8 4
Voltage (V)
20. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders. Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits
illustrated in this document are for reference purposes only.