Three-Phase Single-Switch Boost PFC Converter with High Input Power Factor Kai Yao1, Xinbo Ruan1,2, Senior

Member, IEEE, Chi Zou1, Zhihong Ye3

2

Aero-Power Sci-tech Center, College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China (e-mail: yaokai@nuaa.edu.cn, zouchi88@yahoo.com.cn) College of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan 430074, China (e-mail: ruanxb@mail.hust.edu.cn) 3 Lite-On Technology Power SBG ATD-NJ R&D Center, Nanjing 210019, China (e-mail: Sam.Ye@liteon.com)

Abstract Three-phase single-switch boost power-factor-correction (PFC) converter features zero-current turn-on for the switch, no reverse recovery in diode, constant frequency operation, simple control and low cost, and it is suitable for the low-to-medium power conversions. However, the input power factor (PF) is relatively low when the duty cycle is constant in the whole line cycle. This paper analyzes the operation principle of the three-phase single-switch DCM boost PFC converter, and the expressions of the input current and PF are derived, based on which, a variable duty cycle control is proposed so as to improve the PF and reduce the input current harmonics. A method of fitting the duty cycle is further proposed for simplifying the circuit implementation. Besides a higher PF and lower input current harmonics, the proposed variable duty cycle control achieves a lower output voltage ripple and a higher efficiency over the constant duty cycle control. A 3kW prototype has been built and tested in the lab, and the experimental results are presented to verify the effectiveness of the proposed method. Index Terms Power-factor-correction, Three-phase, Discontinuous-current-mode, Pulse width modulation, Variable duty cycle control.

I INTRODUCTION
Power factor correction (PFC) converters have been widely used in ac-dc power conversions to achieve high power factor (PF) and low harmonic distortion. The methods of achieving PFC can be classified into active and passive types. Compared with passive PFC converter, active one can achieve a high PF and a small size [1]. There are different topologies and control strategies for implementing active three phase PFC converters [2]. Specifically, three-phase six- switch boost PFC converter can achieve unit PF and very low harmonic distortion of the line current. The converter is mainly used in high and medium power applications due to the many number of switches, the complexity of the control and high cost [2]. Three-phase single-switch boost PFC converter operates in discontinuous current mode (DCM) to achieve PFC. Featuring zero-current turning on for the switch, no reverse recovery of diode, simple control and low cost, the converter is mainly used in medium and low power, cost-sensitive applications [3]. However, If the duty cycle

is constant in a line cycle, the average value of the inductor current in a switching cycle is not sinusoidal. The PF is low and the input current contains rich 5th and 7 th harmonics. To date, a number of techniques for the input current harmonics reduction of three-phase single-switch boost PFC converter have been proposed [4-9]. Adding the 5 th harmonic trap in the input side can reduce the 5th harmonic in the input current and improve the PF. However, the efficiency decreases as high circulating current flows in the loop consisting of the trap filter and the ac source [5]. Variable switching frequency control can reduce the input current harmonic distortion. However, the inductor and EMI filter design is a little complicated [6-7]. Injecting 6th harmonic into the duty cycle is an effective technique [4, 8-9]. The proposed 6 th harmonic injection circuit, which employs a band-pass filter, has a severe phase-shift problem and the effect is not so ideal [4]. Ref. [8] offers another solution, where the harmonic injection is realized with the out voltage ripple. The method requires complicated and expensive additional circuitry such as phase-detecting and phase-locking circuits to properly synchronize the injected signal with the input current. The solution proposed in [9] is that the duty cycle is modulated by subtracting a fraction of the ac component of the rectified input voltage from the error signal of the output voltage control loop. However, the input current harmonics distortion can not be achieved at minimum value over the input voltage range. This paper analyzes the operation principle of the three-phase single-switch boost PFC converter, based on which, a variable duty cycle control is proposed so as to improve the PF. A method of fitting the duty cycle is further proposed for simplifying the control. Besides a higher PF and lower input current harmonics, the proposed variable duty cycle control achieves a lower output voltage ripple and a higher efficiency over the constant duty cycle control. II. OPERATION P RINCIPLE OF T HREE -PHASE B OOST PFC C ONVERTER. Fig. 1 shows the main circuit of a three-phase

978-1-4244-5287-3/10/$26.00 2010 IEEE

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va o vb vc (a) switching mode 1.

Fig. 1. Main circuit of three-phase single-switch boost PFC converter.

ia ib ic

La Lb Lc
_

Vo

( b) switching mode 2. ( c) switching mode 3. Fig. 4. Equivalent circuit of switching mode 3.

single-switch boost PFC converter, where La=Lb=Lc=L. The input voltage is defined as va = Vm sin t

(1)

(3) vc = Vm sin ( t + 2 3 ) where Vm and are the amplitude and angular frequency of the input voltage.

vb = Vm sin ( t 2 3 )

(2)

(6) va L dia dt = vb L dib dt = vc L dic dt From (4) to (6), the rising rate of the inductor current is (7) dia dt = va L dib dt = vb L dic dt = vc L When Qb turns off, the inductor current reaches its peak value, which is va Dy Ts di (8(a)) iap1 = a Dy Ts = dt L vb Dy Ts di (8(b)) ibp1 = b Dy Ts = dt L vc Dy Ts di (8(c)) icp1 = c Dy Ts = dt L where D y is the duty cycle and Ts is the switching cycle. (2) Switching mode 2 When Qb turns off, Db conducts. Fig. 4(b) shows the equivalent circuit, from which it can be seen that di di (9(a)) va vb Vo = L a b dt dt

Fig. 2. Input voltage waveform.

vgs 0 ia ib ic icp1 iap1 0 t/Ts ibp2 ibp1 Dy DR1 DR2 1 icp2 t/Ts

di di (9(b)) vc vb Vo = L c b dt dt where V o is the output voltage. From (4), (5) and (9), the falling rate of the inductor current is (10(a)) dia dt = ( va Vo 3) L dib dt = ( vb + 2Vo 3) L dic dt = ( vc Vo 3) L

(10(b)) (10(c))

Fig. 3. Inductor current waveform in a switching cycle during [0, /6].

Obviously, the voltage and current meets the following: (4) va + vb + vc = 0 (5) ia + ib + ic = 0 Fig. 2 shows the input voltage waveform. A line cycle of 2 can be divided into 12 intervals. In each interval of /6, the voltage direction and relative size of the three phase input voltage is the same. Fig. 3 shows the inductor current waveform in a switching cycle. (1) Switching mode 1 When Qb turns on, D1D5D4 conducts. Fig. 4(a) shows the equivalent circuit, from which it can be seen that

ia reaches zero first, the duty cycle corresponding to this falling period is iap1 1 3va (11) DR1 = = Dy dia dt Ts Vo 3va
When ia reaches zero, ib and ic is V ( v + 2va ) Dy Ts di ibp 2 = ibp1 + b DR1Ts = o b dt Vo 3va L icp 2 = ibp 2 = Vo ( vb + 2va ) Dy Ts Vo 3va L

(12(a)) (12(b))

(3) Switching mode 3 When ia reaches zero, The equivalent circuit is shown in Fig. 4(c), from which it can be seen that

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Fig. 5. Inductor current waveform of phase a in a half line cycle.

Fig. 6 Normalized average input current waveform of phase a in a half line cycle.

Fig. 7. Relationship between the input PF and M.

di di (13(a)) vc vb Vo = L c b dt dt (13(b)) ib = ic From (13), the falling rate of the inductor current is dib di V + v v (14) = c = o b c dt dt 2L From (12) and (14), the duty cycle corresponding to this falling period of ib and ic is ibp 2 1 2Vo ( vb + 2va ) (15) DR 2 = = Dy dib dt Ts (Vo + vb vc )( 3va Vo )

k1 ( t ) = k6 ( t ) =
k2 ( t ) =

sin t

2 2 3M 3sin t + 3

3M 3sin t 1 2 M sin t + sin 2 t

(18(a))

3 M sin t + 6

(18(b))

(4) Switching mode 4 During this period, the inductor currents of three phase are all zero, the output capacitor supply the energy to the output. From Fig.3, during [0, /6], the average inductor current in a switching cycle can be derived as iap1 sin t (16(a)) ia _ av1 ( t ) = ( Dy + DR1 ) = I0 2 3M 3sin t 1 ib _ av1 ( t ) = Dy ibp1 + DR1 ( ibp1 + ibp 2 ) + DR 2 ibp 2 2 (16(b)) sin 2 t M sin ( t + 3) = I0 3M 3sin t ( M cos t )

M sin t + sin 2 t + 3 k3 ( t ) = 2 3M + 3sin t + 3 M sin t + 6 M sin t sin 2 t 3 k4 ( t ) = 5 3M 3sin t + 3 M + sin t + 6

1 2 M sin t sin 2 t + 2 3 k5 ( t ) = 5 3M + 3sin t + 3 M + sin t + 6

(18(c))

(18(d))

(18(e))

ic _ av1 ( t ) =

1 Dy icp1 + DR1 ( icp1 + icp 2 ) + DR 2 icp 2 2 1 M cos (t + 6 ) sin 2t 2 = I0 3M 3sin t ( M cos t )

(16(c))

2 Vo where I 0 = Dy

( 2 Lf s ) M

= Vo

3Vm , f s = 1/ T s is the

According to the above analysis, Fig. 5 shows the instantaneous waveform, the peak value envelope and the average value of ia. It can be seen that the shape of the peak inductor current is sinusoidal, however the shape of the average inductor current is not sinusoidal and there is distortion in it. The normalized average value of ia (with the base of I0) is plotted in Fig. 6, from which, it can be seen that the shape of the average inductor current is only dependent on M, and the bigger M is, the closer to sinusoidal the current shape is. From (1) and (17), the average input power of phase a is derived as
Pin _ a = = 1 Tline 4
Tline 4 0

va ia _ av dt

switching frequency. The operation principle of other interval is similar to that of [0, /6], the average inductor current in a switching cycle can also be derived. During [0, ], the average inductor current of phase a is n n 1 (17) t n = 1, 2, " 6 ia _ av ( t ) = kn I 0 6 6 where

2 I 0Vm 06 k1 sin tdt + 3 k2 sin td t + 2 k3 sin td t 6 3

(19)

where T line is the line cycle Substitution of (17) and (19) into the PF leads to
PF = Pin _ a Vm I a _ rms 2
2 6 0 k1 sin td t + 3 k2 sin td t + 2 k3 sin td t 6 3 =

6 0

k12 d t + 3 k22 d t + 2 k32 d t

6 3

(20)

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0.990 0.989 0.988 0.987 0.986 0.985

k1 := 0 PF

0.87

0.90

0.93

y0

0.96 0.966 0.99

Fig. 9. Surface of the input PF as the function of j1

and j2

Fig. 10. Relationship between PF and j2 when j1=0

Fig. 11. Relationship between PF and y0 when M=1.16.

'' k4 ( t ) = k 2 ( t / 3 )

where Ia_rms is the rms value of the current of phase a. According to (20), the input PF is plotted as shown in Fig. 7. It can be seen that the larger M is, the higher the PF is. When the output voltage is 750 V, the PF is only 0.971 at the input voltage of 264 VAC, the input current contains rich harmonics. New control method should be proposed for the PF improvement. III. VARIABLE D UTY CYCLE C ONTROL TO IMPROVE INPUT P OWER FACTOR A. Variable Duty Cycle for PF= 1 By observing (17), in order to achieve unity PF, the duty cycle should be variable as
n n 1 Dya ( t ) = D0 sin t / kn t n = 1, 2,"6 6 6

k5'' ( t ) = k3 ( t / 3)

k3'' ( t ) = k1 ( t / 3 )

k6'' ( t ) = k4 ( t / 3)

Fig. 8. Ideal duty cycle that ensures PF =1 .

(21)

where D o is a coefficient, which will be explained later. Substitution of (21) into (17) leads to D 2V (22) ia _ av ( t ) = 0 o sin t 2 Lf s From (1) and (22), the average input power is Tline 2 3VmVo D0 1 4 (23) Pin = 3 v t i t dt = = Po ( ) ( ) a a _ av Tline 4 0 4 Lf s From (23), D 0 can be obtained as Lf s Po (24) D0 = 2 3VmVo The ideal duty cycle which makes ib and ic sinusoidal can also be derived as
2 ' Dyb ( t ) = D0 sin t / kn 3 n n 1 t n = 1, 2, " 6 6 6

(25) (26)

2 '' n 1 n Dyc ( t ) = D0 sin t + / kn t n = 1, 2," 6 3 6 6

From (21), (25) and (26), Dya, Dyb and Dyc can be plotted, as shown in Fig. 8. As seen, the unified duty cycle which ensures the PF of three phases to be unity can not be realized. However, a certain duty cycle which enables the PF to be near unity can be expected. The coefficient j 1, j 2 and j3 are introduced here to generate the duty cycle: j1Dy _ a ( t ) + j2 Dy _ b ( t ) + j3 Dy _ c ( t ) ( 0 t / 6 ) j3 Dy _ a ( t ) + j2 Dy _ b ( t ) + j1Dy _ c ( t ) ( / 6 t / 3) j2 Dy _ a ( t ) + j3 Dy _ b ( t ) + j1Dy _ c ( t ) ( / 3 t / 2 ) (28) Dy ( t ) = j2 Dy _ a ( t ) + j1 Dy _ b ( t ) + j3 Dy _ c ( t ) ( / 2 t 2 / 3) j3 Dy _ a ( t ) + j1Dy _ b ( t ) + j2 Dy _ c ( t ) ( 2 / 3 t 5 / 6 ) j D ( t ) + j D ( t ) + j D ( t ) ( 5 / 6 t ) 3 y_b 2 y_c 1 y_a When the output voltage is 750 V and the input voltage is 264 VAC, M=1.16. From (1), (17), (20), (21), (25), (26), (28) and M=1.16, we can plot the relationship between PF and j1, j2, as shown in Fig. 9. As seen, j1=0 enables the optimal PF with a certain value of j2. When j1=0, the relationship between PF and j2 can be plotted, as shown in Fig.10, from which it can be seen that the highest PF can be obtained when j2=0.7, j3=0.3. B. The Fitting Duty Cycle The duty cycle expressed in (28) is complicated to implement because a few of multiplier, divider and square root extractor are needed, it is necessary to seek a function that fits (28), which can be more easily implemented. Take [0, /6] for example, defining y= cost, t[0, /6], the ideal duty cycle of phase b and c in this interval can be rewritten as

where k1' ( t ) = k3 ( t + / 3)
' 5

k3' ( t ) = k5 ( t + / 3 )
'' 1

' k2 ( t ) = k 4 ( t + / 3 )

' k4 ( t ) = k6 ( t + / 3 ) ' 6

(27)

k ( t ) = k1 (t 2 / 3 )

'' k ( t ) = k5 ( t + 2 / 3) k 2 (t ) = k6 (t + 2 / 3)

k ( t ) = k 2 (t 2 / 3 )

2924

Fig. 12. Curve fitting of h(0.966, M).

Fig. 14. Comparison of the input PF

Fig. 15. Normalized amplitudes of the5 th , 7 th , 11 th and 13 th harmonics

Dy _ b1 ( y ) = D0

( 1 y ( 1 y

3y
2

)( )(

3M 3 1 y 2
2

)(M y) )(M y)

(29(a))

4 y 1 y M 1 y 3My
2

Dy _ c1 ( y ) = D0

+ 3y

3M 3 1 y 2

(29(b))

3My M 1 y 2 2 y 1 y 2

vx v y vz

Based on Taylors series

+

f ( x ) = f ( x0 ) + f ' ( x0 ) ( x x0 ) 1 '' 1 2 n n f ( x0 ) ( x x0 ) + " + f ( ) ( x0 ) ( x x0 ) + " n! 2!

(30)

Reserving only the first derivative item, (28) is approximated as

Dy1_ fit ( y ) = 0.7 Dy _ b1_ fit ( y ) + 0.3Dy _ c1_ fit ( y )
' ' = 0.7 Dy _ b1 ( y0 ) + ( y y0 ) Dy _ b1 ( y0 ) + 0.3 Dy _ c1 ( y0 ) + ( y y0 ) Dy _ c1 ( y0 )

(31)

Fig. 13. Control circuit of the variable duty cycle control.

=D1 1 h ( y0 , M ) y

where D1 = 0.7 ( Dy _ b1 ( y0 ) y0 Dy' _ b1 ( y0 ) ) + 0.3 ( Dy _ c1 ( y0 ) y0 Dy' _ c1 ( y0 ) ) ,

h ( y0 , M ) =
' ' 0.7 ( y0 Dy _ b1 ( y0 ) Dy _ b1 ( y0 ) ) + 0.3 ( y0 Dy _ c1 ( y0 ) Dy _ c1 ( y0 ) ) ' ' 0.7 Dy _ b1 ( y0 ) + 0.3Dy _ c1 ( y0 )

The derivation of the fitting duty cycle of other interval is similar to that of [0, /6]. The expression of D1 and h(y0,M) of other interval is the same with [0, /6], as shown in (32) D1 1 h ( y0 , M ) cos (t ) ( 0 t / 6 ) (32) Dy _ fit (t ) = D 1 h y , M cos t / 3 ( 0 ) ( ) ( / 6 t / 2 ) 1 Substitution of (32), (17) and (1) into (20) leads to
6 1 h ( y , M ) cos ( t ) 2 k sin td t 0 1 0 2 2 3 k2 sin td t 1 h ( y0 , M ) cos (t / 3) + 6 2 + 2 k3 sin td t 1 h ( y0 , M ) cos (t / 3) 3 PF =

plot the curve of the relationship between PF and y0, as shown in Fig.11. From Fig.11 it can be seen that when y0=0.966, the maximum PF can be obtained. Substituting y0=0.966 into h(y0, M), the curve of the relationship between h(y0, M) and M can be plotted, as shown in Fig.12. As seen, when 1.16M1.74, 1 ( 2 M 1) fits well with h(0.966, M). With t[0, 2], (32) is written as D1 1 cos t / ( 2M 1) ( 0 t / 6 ) D1 1 cos t / 3 / 2 M 1 / 6 t / 2 ) ( ) ( ) ( D1 1 cos (t 2 / 3) / ( 2M 1) ( / 2 t 5 / 6 ) 1 cos (t ) / ( 2M 1) Dy _ fit (t ) = D1 ( 5 / 6 t 7 / 6 ) D 1 cos t + 2 / 3 / 2 M 1 ( ) ( ) ( 7 / 6 t 3 / 2 ) (34) 1 1 cos (t + / 3) / ( 2M 1) D1 ( 3 / 2 t 11 / 6 ) D 1 cos t / 2 M 1 ( ) (11 / 6 t 2 ) 1
vg 1 = D1 1 2M 1 3V m vg = D1 1 2V 3V o m

(33)

6 0

k12 1 h ( y0 , M ) cos (t ) d t

+ 3 k22 1 h ( y0 , M ) cos (t / 3) d t
6

1 h ( y0 , M ) cos (t / 3) + 2 k32 d t
3

(33) shows that PF depends both on M and y0. Considering the worst case of M=1.16, we substitute M=1.16 into (33) and

where vg is the rectified voltage of the input. From (34), the fitting duty cycle can be plotted as in Fig.8. The control circuit can be implemented as shown in Fig. 13. The input voltage of three phase is sensed through a differential sampler, and vA=mvg, where m is the voltage sensor gain. R 8, D7 , C1 and R 9 are the circuit to obtain the peak value of the rectified input voltage, i.e., vB = m 3 Vm. The reasonable resistance selection of the feed forward circuit can enable the voltage of C and D point to be m(2Vo 3 Vm) and m(2Vo 3 Vmvg) separately. vC, vD

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Fig. 16. Relationship between f 1 (M , t ) and t.

Fig. 17. Critical inductors over the input voltage range.

Fig. 18. Normalized instantaneous input power with constant duty cycle control and variable duty cycle control.

and the output voltage control loop error signal vEA are sent to the multiplier, and
vP = vEA m 2Vo 3Vm vg m 2Vo 3Vm

little increased, the total harmonics is decreased.

) =v

vg 1 EA 2V 3V o m

B. Reduction of the Inductor Current Ripple

Taking [0, /6] for example, in order to ensure the converter operates in DCM, the following condition should be met. (39) Dy + DR1 + DR 2 1 With constant duty cycle control, Substitution of (11) and (15) into (39), yields Dy f1 ( M , t ) 1 (40) (41) f1 ( M , t ) = M ( M cos t ) With variable duty cycle control, substitution of (34) into (40), leads to (42) D1 f 2 ( M , t ) 1 where f 2 ( M , t ) = M 1 cos t / ( 2M 1) ( M cos t ) (43)
A family curves of f1,2(M, t) over t with different M can be plotted, as shown in Fig. 16. As seen, for any M with 1.16M1.74, the maximum value of f1,2(M, t) occurs at t=0. Substitution of t=0 into (41) and (43), yields (44) f1 ( M , 0 ) = M / ( M 1) f 2 ( M , 0 ) = 2M / ( 2M 1) (45) Supposing the efficiency of the converter is 100%, i.e. Pin_a=Po/3, so (18), (19) and (34), we have
Dy = Po Lf s 3VoVm 6 k1 sin tdt + 3 k2 sin td t + 2 k3 sin tdt 0 6 3

(35)

v P is sent to the PWM comparator and compared with the saw-tooth carrier, and the desired duty cycle of (34)can be obtained. IV. ADVANTAGES OF VARIABLE D UTY CYCLE C ONTROL A. Improvement of the Input PF According to (20) and (33), the input PF with constant duty cycle control and variable duty cycle control are depicted in Fig. 14. It can be seen that the input PF is greatly improved with the variable duty cycle control. When the input voltage is 264 VAC, the PF is increased from 0.971 to 0.989. By Fourier analysis, the harmonics of the input current can be obtained as a (36) iin (t ) = 0 + an cos ( nt ) + bn sin ( n t ) 2 n =1 where 2 Tline an = iin ( t ) cos ( n t )d t ( n = 0,1, 2,) Tline 0 (37) 2 Tline bn = i t n t d t n = sin 1, 2,3 ( ) ( ) ( ) in Tline 0 Substituting (17) and (34) into (36), the harmonics of the input current with constant and variable duty cycle control, respectively, can be figured out, in which the cosine part, the even and the triple sinusoidal part are zero, i.e., an = 0 ( n = 0,1, 2,) (38) b2 n3 n = 0 ( n = 1, 2,3 ) The normalized amplitudes of the 5 th , 7 th , 11th and 13 th harmonics to the base of the fundamental component are shown in Fig. 15. It should be noted that the negative amplitude means that the corresponding harmonic has a phase of 180 . Fig. 15 illustrates that with the variable duty cycle control, the 5th and 11th harmonics of the input current is greatly reduced, the 7 th and 13 th harmonics is a

where

(46)

D1 =

Lf s Po 2 cos t k1 sin td t 6 1 0 2M 1 2 cos (t / 3) 3VoVm + 3 1 sin k td t 2 2 1 M 6 2 cos / 3 t ( ) + 2 1 sin k td t 3 2M 1 3

(47)

From (40), (44) and (46), the critical boost inductor with constant duty cycle control is obtained as

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o m 3 6 2 0 k1 sin td t + k2 sin td t + k3 sin td t Po f s M 6 3

2 3V V M 1

(48)

From (42), (45) and (47), the critical boost inductor with variable duty cycle control is obtained as
6 2 M 1 cos (t ) 2 k sin td t 1 0 2 3VoVm L + 3 2 M 1 cos t k2 sin tdt (49) 2 4 Po f s M 6 3 2 + 2 2 M 1 cos t k sin td t 3 3 3

where Vo1 and Vo2 are the output voltage ripple with constant duty cycle control and variable duty cycle control, respectively.

According to the specifications of the converter, which will be given in Section V, the critical boost inductor over the input voltage range with constant duty cycle control and variable duty cycle control are depicted in Fig. 17, from which we choose Lb 1 = 125 H and Lb 2 = 155 H. The increment of the inductor is helpful for the reduction of the peak and rms current of the inductor, switch and diode. Thus, the conduction loss of the converter can be reduced, leading to a higher efficiency. C. Reduction of the Output Voltage Ripple With the base of Po, the normalized instantaneous input power is derived as * (50) pin ( t ) = ( va ia _ av + vb ib _ av + vc ic _ av ) Po Same with (17), the expression of ib_av(t) and ic_av(t) can also be derived. Substitution of ia_av(t), ib_av(t) and ic_av(t) into (50) leads to p*in_1. Similarly, when variable duty cycle control is employed, from (17), (34) and (52), the normalized instantaneous input power is derived as p*in_2 . With the cycle of /3, the curves of p*in_1 and p*in_2 during [0, /3] are in depicted in Fig. 18. * When pin ( t ) >1, the storage capacitor Co is charged, and when
* pin ( t ) <1, Co is discharged. The energy

Fig. 19. Output voltage ripple with constant duty cycle control and variable duty cycle control.

From (51) and (52), the expressions of Vo1 and Vo2 are derived as
1 Vo1 = 2 Po p* ( t ) 1 dt 0 in _1

p* (53(b)) o o in _ 2 According to the specifications of the converter, which will be given in Section V, Vo1 and V o2 can be figured out as shown in Fig. 19. It can be seen that with variable duty cycle control, the output voltage ripple is reduced compared to constant duty cycle control. Vo 2
o 0

{ = {2 P

t2

} CV ( t ) 1 dt} C V

o o

(53(a))

V. E XPERIMENTAL VERIFICATION In order to verify the validity of the proposed variable duty cycle control, a prototype has been built and tested in the lab. The specifications of the prototype are as follows: input voltage: v in = 220V 20% /50Hz; output voltage: V o = 750 VDC; output power: P o = 3 kW; switching frequency: f s = 30 kHz. Figs. 20 and 21 show the experimental waveforms of the input voltage, input current, boost inductor current and output voltage with constant duty cycle control and variable duty cycle control at 176 VAC, 220 VAC and 264 VAC input respectively. It can be seen that compared to constant duty cycle control, the input current is close to sinusoidal shape with variable duty cycle control. Figs. 22 to 24 show the measured input PF, output voltage ripple and efficiency curve with different input voltage, from which it can be seen that the PF is improved, the output voltage ripple is reduced and the efficiency is increased with the variable duty cycle control. VI. C ONCLUSIONS The input PF of three-phase single-switch boost PFC converter is relatively low when the duty cycle is constant in

discharging C o (which equals the charged energy) in the cycle of /3 with constant duty cycle control and variable duty cycle control are
1 E1* = 2 p* ( t ) 1 dt 0 in _1

p* (51(b)) line 6 ) in _ 2 respectively, where t 1 and t2 are the time instants when * pin ( t ) crosses 1 with constant duty cycle control and
* E 2 0

{ = {2

t2

} (T ( t ) 1 dt} (T

line

6)

(51(a))

variable duty cycle control, respectively. * E1* and E2 can also be expressed as
V 1 V 1 Co Vo + o _1 Co Vo o _1 6CoVo Vo _1 2 2 2 2 E1* = Po Tline 6 PoTline V 1 V 1 Co Vo + o _ 2 Co Vo o _ 2 6CoVo Vo _ 2 2 2 2 2 * E2 = Po Tline 6 PoTline
2 2 2 2

(52(a))

(52(b))

2927

(a)

(b)

(c)

Fig. 20. Experimental waveforms of input voltage, input current, inductor current and output voltage with constant duty cycle control: (a) @ 176 VAC input; (b) @ 220 VAC input; (c) @ 264 VAC input.
va: [200 V/div] ia: [20 A/div] ia: [10 A/div] va: [200 V/div]

iLa: [20 A/div] vo: [10 V/div] Time: [2 ms/div]

iLa: [20 A/div]

vo: [10 V/div] Time: [2 ms/div]

(a)

(b)

(c)

Fig. 21. Experimental waveforms of input voltage, input current, inductor current and output voltage with variable duty cycle control: (a) @ 176 VAC input; (b) @ 220 VAC input; (c) @ 264 VAC input.

Fig. 22 Measured PF over the input voltage range.

Fig. 23. Measured output voltage ripple over the input voltage range.

Fig. 24 Measured efficiency over the input voltage range.

the whole line cycle, especially at high input voltage. Aiming at this, a variable duty cycle control is proposed so as to improve the PF and reduce the input current harmonics. A method of fitting the duty cycle is further proposed for simplifying the circuit implementation. Besides a higher PF and lower input current harmonics, the proposed variable duty cycle control achieves a lower output voltage ripple and a higher efficiency over the constant duty cycle control. REFERENCES
[1] O. Garcia, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, Power factor
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