A General Space Vector PWM Control Algorithm for Multilevel Inverters

Sanmin Wei and Bin Wu

Dept. of Electrical and Computer Engineering Ryerson University, Toronto, Canada swei@ee.ryerson.ca bwu@ee.ryerson.ca
Abstract - To solve the problem of computational complexity in multilevel inverters due to the large number of space vectors and redundant switching states, a simple and general space vector PWM algorithm is proposed. Based on this algorithm, the location of the reference voltage vector can be easily determined and the calculation of dwell times becomes very simple. More importantly, the proposed algorithm is general and can be directly applied to the cascaded H-bridge inverter of any voltage levels. In addition, a new switching sequence, Large-Small Alternation (LSA), is proposed for the minimization of total harmonic distortion. To verify the algorithms, a 7-level cascaded H-bridge inverter drive system was constructed and experimental results are provided. Keywords - Multilevel inverte; Space vector modulation; Pulse width modulation.

Fahai Li and Congwei Liu

Dept. of Electrical Engineering Tsinghua University, Beijing, China lifh@mail.tsinghua.edu.cn cwliu@mail.tsinghua.edu.cn vectors and redundant switching states [5],[7],[8]. For example, there are 343 switching states in a 7-level inverter, which correspond to 127 voltage vectors. N.Celanovic has proposed a fast SVM algorithm [5], but the dwell time calculations seem complex due to the use of Euclidean vector space representation. In addition, the selection of the switching states in the inverters of higher than three levels seems not well documented. B.S. Suh proposed a good PWM calculation method for three-level inverter [8], but it is difficult to apply it to higher level inverters. In this paper, a general space vector algorithm is proposed, which has the following features: The algorithm is very simple and effective. The location of the reference voltage vector and the dwell times of the space vectors can be calculated very easily; The generated PWM pattern contains minimal voltage harmonic content; and The proposed algorithm is general and can be used in any high-level cascaded H-bridge inverters. The details of the algorithm are discussed as follows.

I. INTRODUCTION
The research on the multilevel inverter has been receiving wide attention mainly due to its capability of high voltage operation without switching devices connected in series. In addition, with the increase of voltage levels, the inverter output contains less harmonics and will eventually approach a desired sinusoidal waveform [1]. Therefore, the multilevel inverters have been selected as a preferred power converter topology for high voltage and high power applications [2], [3]. Among all the switching algorithms proposed in the literature for multilevel converters [1]-[9], space vector modulation (SVM) seems most promising since it offers a great flexibility in optimizing switching pattern design and it is also well suited for digital implementation. The space vector modulation for more than three-level inverters is very complex due to the high number of space
0-7803-7768-0/03/$17.00 (C) 2003 IEEE

II. REFERENCE VECTOR LOCATION AND DWELL TIME

CALCULAION A typical 7-level cascaded H-bridge inverter is shown in Fig. 1, where a separate dc power supply is used for each H-bridge. Its corresponding space voltage vector diagram is illustrated in Fig. 2, in which the vectors for the 3, 5, and 9-level inverters are also illustrated. For the 7-level inverter, there are 216 small triangles and the vertex of each triangle represents a space vector, which is defined by
v V = Va e j 0 + Vb e j 2 / 3 + Vc e j 4 / 3

(1)

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V dc

Va

Vb

Vc

There are in general two problems with the use of Cartesian coordinates: a) It is quite tedious to determine which triangle the end point of the reference vector falls into; and

V dc

b) The equations for the calculation of dwell times usually change with the triangle that V is in. In other words, each triangle has its own equations for the dwell time calculation.

V dc

To solve the above-mentioned problems, the Cartesian coordinate system can be transformed to a 60 o coordinate system (shown in Fig. 4) by
V = cos V sin / 3 o o V = V cos(60 ) V sin(60 ) / 3 (3)

Figure 1. Topology of 7-level cascaded H-bridge inverter.

8 6 4 2 0 -2 -4 -6 -8

9-level 7-level

II

r where V and V are the coordinates of a space vector V in the

I

III

5-level 3-level

60 o coordinate system, and V and are its amplitude (length) and phase angle, respectively. The benefits of such a transformation will be demonstrated in the following sections. A. Fast Determination of Reference Vector Location r Assume that the reference vector V * in Fig. 4 lies in triangle EFG . To determine the location of the reference vector, the coordinates of the space vector VD, VD=int(V*) and VD =int(V*), will be used, where int( ) is a lower rounded integer

IV

VI

V
-8 -6 -4 -2 0 2 4 6 8

function, for example, int(4.6) = 4. The coordinates of VD indicate the reference vector must lie in one of the two triangles,

Figure 2. Voltage vectors of 3,5,7 and 9-level voltage source inverters.

where Va , Vb and Vc are the phase voltages of the inverter. The vectors can be divided into six major triangular sectors (I to VI), and the details of sector I is given in Fig. 3. The coordinates of each vector in the commonly used Cartesian coordinate system, Vx and Vy, can be calculated by

DEF and EFG. Based on VD, the coordinates of space vectors VE, VF and VG can be calculated by
(V E , V E ) = (V Da , V D + 1) (V F , V F ) = (V Da + 1, V D ) (V , V ) = (V + 1, V + 1) Da D G G is in DEF or EFG, the following criterion can be used:
V DEF V EFG

(4)

V x = Va (Vb + Vc ) / 2 V y = 3 (Vb Vc ) / 2

(2)

respectively. To further determine whether the reference vector

The coordinates of all the space vectors, assuming a unity dc supply voltage (i.e., Vdc = 1 per unit), can be shown in the figure as well. To reduce the voltage harmonic distortion, the reference voltage V can be synthesized by the three nearest vectors. With V lying in triangle EFG, the reference voltage can be r r approximated by vectors VE = 7 / 2 + j 3 / 2 , V F = 3 + j 3 r and VG = 4 + j 3 .

if (V + V ) (V E + V E ) if (V + V ) < (V E + V E )

(5)

The above algorithm provides a very simple means to determine the location of the reference vector quickly and accurately.

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3 ,3 3
5 ,5 3 2 2

7 ,5 3 2 2

V F TF + V E TE + VG TG = VTS V F TF + V E TE + VG TG = V TS T +T +T =T E G S F

(7)

2, 2 3
3 ,3 3 2 2

3, 2 3
5 ,3 3 2 2

4,2 3
7 ,3 3 2 2

Substituting (4) into (7), the dwell times can be calculated by

TE = (V D + 1 V )TS TF = (V D + 1 V )TS T = T T T S E F G
11 3 , 2 2

9 ,3 3 2 2

1, 3

2, 3

3, 3

G
7 2

(8)

4, 3

5, 3

V y*

V
1 2

3
2

3 2

3
2 5 2

, 3
2

9 2

, 3
2

Similarly, with the reference vector lying in DEF, the dwell times of the space vectors, V F , V E and V D , are given by
r r r

, 3
2

E Vx *
4,0 5,0 6,0

0,0 1,0 2,0 3,0

Figure 3. Space vectors in the Cartesian coordinate system (sector I).

TE = (V V D )TS TF = (V V D )TS T = T T T S E F D

(9)

0,6 0 ,5 1, 5

Assuming that V and of the reference vector in Fig. 5 are 3.8 and 20 o , the dwell times can be calculated by a) V = 2.82, and V = 1.50
2,4

0,4

1, 4

b) VD = int(2.82) = 2, VD = int(1.50) = 1 r c) V * is in EFG since ( V + V ) > (VD+VD +1)

3 ,3

0 ,3

1, 3

2 ,3

d) TE = (1 + 1 - 1.50)TS = 0.50TS,
TF = (2 + 1 -2.82)TS =0.18TS, and
4,2

F
0,2 1, 2 2,2

G
3, 2

V*
0 ,1 1,1 2 ,1

V*
3 ,1 4 ,1 5 ,1

TG = (1 - TE - TF)TS =0.32 TS.

The above example demonstrates how simple it is to

0 ,0 1, 0 2 ,0

E
3,0 4 ,0 5,0 6 ,0

determine the triangle that reference voltage falls in and to calculate the dwell times. More importantly, the algorithm has another two features: a) It is a general algorithm, which can be used for inverters with any number of voltage levels; and b) There are only two sets of equations for dwell time calculation. Compared with the Cartesian coordinate system where there are many sets of different equations for the calculation of the dwell time, the proposed algorithm is much simpler and easier for digital implementation.

V*

Figure 4. Space vectors in the 60 coordinate system (sector I).

B. Dwell Time Calculation With the reference vector in EFG, the following two equations can be established according to the commonly used volt-second balancing principle: r r r r V F TF + V E TE + VG TG = V TS TF + TE + TG = TS

(6)

where TF , TE and TG are the dwell times of the vectors r r r V F , V E and VG , respectively. Decomposing (6) into and

III. GENERAL RELATIONSHIP BETWEEN SPACE VECTORS AND

SWITCHING STATES In the multilevel inverters, a space voltage vector could be represented by more than one switching state. For instance,

axis components yields

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space vector (1,0) in Fig. 4 has six switching states composed of [2,3,3], [1,2,2], [0,1,1], [1,0,0], [2,1,1] and [3,2,2], all of which produce an output voltage with the same magnitude and phase angle. With the increase in the voltage levels, there exist more redundant switching states. It is desirable to find a general expression which describes the relationship between space vectors and their corresponding switching states for any cascade H-bridge multilevel inverters. Space vectors in the 60 coordinate system shown in Fig. 4 can be generally expressed by ( , ), where = 1, 2, , 2m, and = 1, 2, , 2m. The number m is defined by
m = (n 1) /2
o

with + = 0, it has seven switching states while for a voltage vector with + = 6, it only has one switching state. For instance, voltage vector (2,3) has two switching states: [2,0, 3] and [3,1, 2].
TABLE I. SWITCHING STATES IN SECTOR I OF A 7-LEVEL SPACE VECTOR
DIAGRAM

switching states
Va Vb Vc

+ =0 + =1 + =2 + =3 + =4 + =5 + =6

3 2 1 0 1 2 3

3 2 1 0 1

(10)

where n is the number of phase voltage levels of the inverter, which is always an odd number for the cascaded H-bridge inverter. The relationship between a space vector ( , ) and its switching states [Va, Vb, Vc] is obtained by a detailed study on all the possible states in a multilevel inverter. The results are given by

3 2 1 0 1

2 2 3 3

TABLE II.

RELATIONSHIP BETWEEN SWITCHING STATES IN VARIOUS SECTORS

Va = m, m + 1, m + 2, ..., m Vb = Va V = V a c

(11)
Sector I II III IV V VI Phase A, B , and C Example: Vector (3,1)

For a given space vector ( , ), the number of switching states n sw can be obtained by n sw = n ( + ) . Eqs. (10) and (11) are the general expressions, which can be used for any cascaded H-bridge multilevel inverters. Alternatively, for a given space vector ( , ), all of its switching state can be calculated by

Va Vb Vc Va Vb Vc

Vb Vc Va Vb Vc Va

Vc Va Vb Vc Va Vb

[1,2,3], [2,1,2], [3,0,1] [2,3,1], [1,2,2], [0,1,3] [3,1,2], [2,2,1], [1,3,0] [1,2,3], [2,1,2], [3,0,1] [2,3,1], [1,2,2], [0,1,3] [3,1,2], [2,2,1], [1,3,0]

IV. SELECTION OF SWITCHING STATES m] Vc ] (12) In the multilevel inverter, the redundant switching states increase with the voltage level. For example, the 5, 7, and 9-level inverters have the redundant states of 4, 6 and 8, respectively for zero voltage vector. In the diode clamped multilevel inverters, the redundant switching states can be utilized to balance the voltage of capacitors in the dc link. The cascaded H-bridge inverter inherently does not have this problem. In this paper, the redundancy is employed to minimize the voltage harmonic distortion.

[ Va , [ + m, [ + m + 1, [ + m + 2, [m,
..............

Vb , m, m + 1, m + 2,

m + 1] m + 2]

m , m ]

The switching states in other sectors (II to VI) can be obtained from Table I and the details are given in Table II. As an example, all the switching states calculated by (11) for a 7-level inverter are illustrated in Table I. For a space vector

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A. Definition of Mean, Small and Large Switching States Any space vectors ( , ) in Fig. 4 can be classified into the following two categories: Category 1: even vector the sum of its coordinates, + , is an even number; and Category 2: odd vector the sum of its coordinates is an odd number. It is interesting to note that the difference between the coordinates, , of an even vector is always an even number while for an odd vector, the difference between and is always an odd number. Based on (12), the mean switching state of a space vector can be calculated by
0,1 1,1 0, 2 0,3 0, 4

0, 6

0,5

1,5

1,4

2, 4

1,3

2,3

3,3

1,2

2, 2

3, 2

4, 2

2,1

3,1

4,1

5,1

T3
0 ,0 1,0 2 ,0

T4
3,0

V a _ mean = {( + m) + m} / 2 = ( + ) / 2 (13) Vb _ mean = {( m) + (m )} / 2 = ( ) / 2 V c _ mean = {( m) + (m )} / 2 = ( + ) / 2

which can be rewritten [( + ) / 2, ( ) / 2, ( + ) / 2] . For an even vector, each component of its mean switching state is an integer, and the state is implementable. For instance, space vector (1,1) in Fig. 4 has five states: [1,2,3], [0,1,2], [1,0,1], [2,1,0] and [3,2,1]. Its mean state is [1,0,1], which can be realized by the inverter with output voltages of Va = 1, Vb = 0, and Vc = 1 . However, for an odd vector where + and is an odd number, its mean state cannot be implemented since the inverter cannot produce half-level voltages. In this case, a small or large switching state can be used: small state [( + 1) / 2, ( 1) / 2, ( 1) / 2] and large state [( + + 1) / 2, ( + 1) / 2, ( + 1) / 2]. B. Effect of Switching States on Inverter Output Voltage With the use of the mean switching states, the average (equivalent) phase voltages of the inverter when the reference vector moves across sector I as shown in Fig. 5 can be calculated by

T1

T2

4, 0

5,0

6 ,0

mean switching state for even vectors large switching state for odd vectors small switching state for odd vectors

Figure 5.

Graphical representation of the proposed LSA method.

The voltage Va for a complete fundamental cycle can be reconstructed as per Table II and is given in Fig. 6(a). The dominant harmonic component in Va is the 3rd harmonic (20.67%) and the other harmonics are negligible. The line-to-line voltages of the inverter do not contain triplex harmonics, and therefore are sinusoidal. This is an ideal case, which is not achievable in practice. Similarly, with the use of large switching states only or small states only, the average inverter phase voltages are given by Va = 2V sin(60 o + ) / 3 3 o o Vb = V sin( 30 ) + V sin(60 + ) / 3 3 V = 3 c and

0 < 60 o

(15)

Va = V sin(60 o + ) / 3 o Vb = V sin( 30 ) V = V sin( 240 o + ) / 3 c

0 < 60 o

(14)

Va = 3 Vb = V cos ) + V sin( ) / 3 + 3 V = 2V sin( + 60 o ) / 3 + 3 c

0 < 60 o

(16)

respectively. The corresponding phase voltage Va is given in

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Fig. 6 (b) and (c). Obviously, the voltage contains substantial harmonic content, which are not desirable. C. Selection of Switching States To minimize the voltage harmonic distortion, the arrangement of switching states are as follows:

voltage Vb has seven voltage levels and the line-to-line voltage Vbc has 13 voltage steps, which is close to sinusoidal.
4 2 0 4 2 0 -2 -4 0 2 4 6 0 2 4 6

a) for those triangles having one even vector, select one mean switching state, one small state and one large state; and b) for the other triangles with two even vectors, select two mean states and one small or one large state alternatively when the reference vector moves along. This switching state selection rule is referred to as Large-Small Alternation (LSA) method, which gives excellent harmonic performance. Fig. 6 (d) illustrates the average inverter phase voltage, which obviously contains much less harmonics than the waveform in (b) and (c). In addition, the LSA method is simple and ease to implement. The graphical representation of the LSA method is illustrated in Fig.5. D. Switching Sequence Design The switching sequence design has to meet a number of requirements such as a) minimization of number of switchings per sampling period, b) one voltage level change per commutation of switching devices, and c) adoption of the LSA method. For example, when the reference vector lies in triangles T1, T2, T3 and T4 in Fig. 5, switching sequence and inverter output waveforms are given in Fig.7, where D, E, F and G are the vertexes (space vectors) of these triangles. The number in each column represents the switching states of a given space vector. V. EXPERIMENTS A three-phase DSP (TMS320F240) controlled 7-level cascaded H-bridge multilevel field-oriented induction motor drive system prototype was built and tested. The induction machine was rated at 3KW, 380V, 6.8A and 1420rpm. The control cycle is 200us and the flowchart of the program is shown Fig. 8. Measured inverter phase and line-to-line voltages when the induction motor operates at 1000rpm and 1450rpm are shown in Fig. 9 (a) and (b), respectively. It can be observed that the phase

-2 -4

(a) Va produced by mean states

4 2 0 -2 -4 0 2 4 6

(b) Va produced by large states only

4 2 0 -2 -4 0 2 4 6

(c) Va produced by small states only

(d) Va produced by LSA method

Figure 6. Average inverter output voltage generated by different switching state selection methods.

D 1 -1 -1
TD 2

E 2 -1 -1
TE 2

E 2 -1 -1
TE 2

D 1 -1 -1

F 1 -1 -2

E 2 -1

F 2 -1 -1

F 2 -1 -1

E 2 -1

D 2 -1 -2

va vb vc

1 -1 -2

va vb vc

2 -1 -2

-2

-2

time T F 2

TD T F 2 2

time TD 2

TE 2

TF 2
*

TF 2

TE 2

TD 2

(a)
F G 1 -1 -1
TG 2

V * lying in T1
E 2 -1 -1
TE 2
*

(b) V lying in T2
F 1 -1 -2
TF 2
E F 2
-2 -2
TF 2

E 2 -1 -1
TE 2

G 1 -1 -1
TG 2

G 2 -1
-2
TG 2
*

G 2 -1
-2
TG 2

F 2
-2 -2
TF 2

E 2
-2

va vb vc

1 -1 -2

va vb vc

2
-2 -3

-3
TE 2

time T F 2

time T E 2

(c) V lying in T3

(d) V lying in T4

Figure 7. Switching sequence and inverter output waveforms generated by the LSA method with the referece vector lying in triangles T1, T2, T3 and T4.

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start Initialization Voltages, currents and speed calculation Flux observeration Close loop calculation
200us

[5]

[6]

[7]

[8]

Space vector algorithm voltages, currents and speed measurement (AD) idle

[9]

carrierwave-based SVPWM using phase-voltage redundancies for multilevel H-bridge inverter, International Conference on Industrial Electronics, Control, and Instrumentation(IECON), Vol.1, 1999, pp324-329. N. Celanovic, and D. Boroyevich, A fast space vector modulation algorithm for multilevel three phase converters, IEEE Trans on Industry Applications, Vol.37, No.2, 2001, pp637-641. B.S. Suh, and D.S. Hyun, A New N-Level High Voltage Inversion System, IEEE Trans. On Industrial Electronics, Vol.44, No.1, 1997, pp107-115. J. Rodriguez, P. Correa, and L. Moran, A vector control technique for medium voltage multilevel inverters, Applied Power Electronics Conference and Exposition(APEC), Vol.1, 2001, pp173-178. B.S. Suh, G. Sinha, M.D. Manjrekar, and T.A. Lipo, Multilevel power conversion-an overview of topologies and modulation strategies, International Conference on Optimization of Electrical and Electronic Equipment (OPTIM), Vol.2, 1998, ppAD11-AD24. D.G. Holmes, and P.M. Brendan, Opportunities for harmonic cancellation with carrier based PWM for two level and multilevel cascaded inverters, IEEE Trans. on Industry Applications, Vol.37, No.2, 2001, pp574-582.

stop

Figure 8. Flowchart of the DSP program.

VI. CONCLUSIONS A simple and general space vector PWM algorithm has been proposed in this paper. To facilitate the design and digital implementation of the space vector algorithm, all the space vectors are transformed from the commonly used Cartesian coordinate system to a 60 coordinate system. The proposed algorithm substantially simplifies the calculation of space vectors and their corresponding dwell times. Based on the proposed algorithm, a new switching pattern, referred to as Large-Small Alternation (LSA), for the cascaded H-bridge multilevel inverters has been developed. The LSA algorithm features easy implementation and more importantly, minimum harmonic content in the inverter output voltage. The most important aspect of the proposed algorithms lies in their generality. They can be used in any high-level cascaded H-bridge inverters. These algorithms are verified through computer simulations and experiments.
(a) 1000rpm Top Trace: Vb, 300V/div; Bottom Trance: Vbc, 300V/div; Time: 10ms/div

[1]

[2]

[3]

[4]

L. Yiqiao, and C.O. Nwankpa, A new type of STATCOM based on cascading voltage source inverters with phase-shifted unipolar SPWM, IEEE Trans. on Industry Applications, Vol.35, No.5, 1999, pp1118-1123. L. Li, C. Dariusz, and Y. Liu, Multilevel space vector PWM technique based on phase-shift harmonic suppression, Applied Power Electronics Conference and Exposition(APEC), Vol.1, 2000, pp535-541. M.L. Tolbert, and F.Z. Peng, Multilevel Converters for Large Electric Drives, IEEE Trans. On Industry Applications, Vol.35, No.1, 1999, pp36-44. D.W. Kang, Y.H. Lee, B.S. Suh, C.H. Choi, and D.S. Hyun, A

(b) 1450rpm Top Trace: Vb, 300V/div; Bottom Trance: Vbc, 300V/div; Time: 5ms/div Figure 9. Experimental wavefors of a 7-level cascaded H-bridge based drive operating at different motor speeds.

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