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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Tunable High-Q N-Path Band-Pass Filters: Modeling and Verication

Amir Ghaffari, Student Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE, Michiel C. M. Soer, Student Member, IEEE, and Bram Nauta, Fellow, IEEE

AbstractA differential single-port switched-RC N-path lter with band-pass characteristic is proposed. The switching frequency denes the center frequency, while the RC-time and duty cycle of the clock dene the bandwidth. This allows for high-Q highly tunable lters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the lter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and veried via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the lter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves lter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The lter has a constant 3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, dBm and the noise gure is 35 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power). Index TermsBand-pass lter, CMOS, cognitive radio, commutated capacitors, frequency translated lter, high linearity, high-Q, inductorless lter, linear periodically time variant circuit, LPTV, N-path lter, software-dened radio, tunable lter.

Fig. 1. Architecture of an N-path lter [5] (p and q are the mixing functions and T is the period of the mixing frequency).

I. INTRODUCTION

N software-dened radio (SDR) and cognitive radio transceivers, programmability is not only desired in the digital back-end, but also for analog front-end functions. A major challenge for such radios is the realization of an RF band-pass lter, with tunable center frequency over a wide frequency span. For cognitive radio applications in the TV-bands, relatively few and rather narrow spectral holes may exist between strong incumbent TV transmitter signals [1]. To reject the strong signals in order to avoid blocking of the receiver, such a lter should have very high linearity, high compression point but also very high for 10 MHz bandwidth around 500 MHz). Q (e.g. Although off-chip passive lters provide these properties, integrated CMOS alternatives are highly desired for reasons of

Manuscript received September 02, 2010; revised January 14, 2011; accepted January 21, 2011. Date of publication April 05, 2011; date of current version April 22, 2011. This paper was approved by Guest Editor Yuhua Cheng. This work was supported by the Dutch Technology Foundation STW, Applied Science Division of NWO and the Technology Program of the Ministry of Economic Affairs (project 08081). The authors are with the University of Twente, CTIT Institute, IC Design Group, 7500 AE Enschede, The Netherlands (e-mail: a.ghaffari@utwente.nl). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/JSSC.2011.2117010

size and cost. On-chip LC lters can be implemented but with limited tuning range and low Q, especially below 1 GHz where the achievable Q of on-chip inductors is poor and coils take large area. Q-enhanced techniques [2][4] can improve lter quality factor but degrade linearity and noise. Thus alternative tunable lters without inductors are highly wanted. Inductor-less tunable lters based on periodically time variant networks have been addressed in literature under different names such as N-path lters, sampled data lters, commutated capacitors, etc. [5][11]. Discrete-time switched capacitor N-path lters are probably best known [8], but here we focus on their continuous-time predecessors. Fig. 1 shows identical a block diagram of an N-path lter composed of linear time-invariant (LTI) networks with impulse response and 2 frequency mixers (or modulators), driven by time/phase shifted versions of the clock and . The time , where is the peshift between two successive paths is riod of the mixer clock. If the LTI networks exhibit a low-pass characteristic around DC, the mixing results in a band-pass around the mixing frequency. Simply put, the input signal is down-converted to baseband, ltered by the LTI network and . The center then up-converted again to the original band of frequency is determined by the mixing frequency, insensitive to lter component values. A high mixing frequency combined with a narrow low-pass lter bandwidth allows for a very high lter Q. While time-continuous N-path lters have been proposed for kHz operating frequencies in the 1960s [6], they seem to have been largely forgotten until recently. CMOS technology now allows N-path lters to work at TV-band RF frequencies [9], [10] and even above 1 GHz [11]. In [9] an 8-path single-ended structure is used, and in [10] we proposed a differential 4-path lter

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Fig. 3. Single port differential 4-path lter. Fig. 2. (a) Switched-RC N-path lter. (b) Single port, single ended N-path lter. (c) Multiphase clocking. (d) Typical (in-band) input and output signal.

combined with a broadband off-chip transformer. In [11] the differential 4-path lters are applied in a quad-band SAW-less receiver. This paper aims to model and verify N-path lter performance. Using linear periodically time-variant (LPTV) analysis, exact expressions for the frequency response of differential N-path lters are derived. In [7] state-space analysis was used to derive the steady state and transient response for a single-ended N-path lter, which is however not directly applicable to our differential architecture. We will derive one set of equations that characterizes ltering but also possible imperfections like harmonic folding, noise and the effects of the clock phase imbalance and mismatch. Moreover, an equivalent RLC tank circuit will be derived to approximate N-path lter behavior around the center frequency. Finally, we will verify the model via extended experimental results compared to [10]. In Section II, we will derive the differential N-path lter architecture starting from Fig. 1 and then analyze its transfer function in Section III. Section IV presents basic characteristics of the differential N-path lter. Its chip implementation is discussed in Section V and Section VI covers the measurement and verication versus the model. II. N-PATH FILTER We will now derive the differential N-path lter from Fig. 1, where we aim for a high-linearity implementation using MOS-switches as passive mixers, and RC low-pass lters [see Fig. 2(a)]. Furthermore we will try to develop some intuitive understanding of the lter behavior. A. Single Ended Switched RC N-Path Filter Fig. 2(c) shows a multi-phase clocking scheme for the switches with non-overlapping on-times. Thus no charge exchange between capacitors can occur. For this reason and since a resistor is a memory-less element, it can be shared by all paths and shifted in front of them [Fig. 2(b)]. Moreover, if the clocks for the rst and second set of switches are identical, the rst set can also implement the function of the second set. becomes then available between the shared resistor and

switches. Fig. 2(b) shows the resulting single-port single-ended N-path lter ( is both input and output port). If we would use the capacitor voltages as outputs, the circuit behaves as a highly linear multiphase passive mixer [12], [13]. To intuitively understand the lter behavior of Fig. 2(b) it is useful to model it as a two-step process: 1) the input signal experiences down-conversion and low-pass ltering passing through the switches to the capacitors; 2) the same switches up-convert the ltered capacitor voltages to the output node. Another way to understand the ltering is to realize that at any moment one and only one capacitor is connected to the output node. If we assume that the time constant , the output voltage will be the average of the input voltage over the time that the capacitor looks at . If the frequency of is equal to the switching frequency, a particular capacitor will periodically observe the same part of the input waveform during every period. As each capacitor sees another part, the result is a staircase approximation of , see Fig. 2(d) (4-path example). In fact, the capacitors experience a steady DC voltage and, in rst order approximation, conduct no current. If the input frequency deviates from the clock frequency the signal portion seen by a capacitor will travel over the period and the capacitors experience an AC voltage (with ). Thus the capacitors conduct current while switches are on and the average voltages on the capacitors becomes closer to zero. Consequently signals at input frequencies below or above the switching frequency will be suppressed with an amount depending on the offset from the switching frequency, on-time of the switch and RC time. B. Differential Switched RC N-Path Filter If we repeat the analysis for input signals around the harmonics of the clock frequency, we also nd non-zero average values. This ts to the comb-like characteristic of N-path lters [5], i.e., its repetitive selectivity around harmonics of the switching frequency. The differential architecture of Fig. 3 aims to cancel the even harmonic responses. Each path is differential-in and differential-out, but contains one grounded capacitor connected to two anti-phase driven switches. A 4-phase 25%-duty-cycle clock provides all required clocks (see Fig. 3). Now, for input signals around the even harmonics of the clock

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frequency, no net charge is stored on the capacitors in steady state and no up-converted signal appears at the output. III. ANALYSIS To model the behavior of the N-path lter quantitatively, we will now apply LPTV state space analysis [14], [15] to derive the exact shape of the transfer function of a differential N-path lter. A. State Space Analysis of LPTV Circuits For an LPTV network which is periodic with the frequency , the output spectrum is related to the input spectrum as [16] (1) represents the shifted version of the input where spectrum to account for frequency translation (mixing), while describes the spectral shaping (ltering) properties of an LPTV network. To simplify analysis, we make two assumptions: 1) the switches are ideal, i.e., their off-impedance is innite and on-impedance is zero; 2) switching occurs instantaneously. The time interval is divided into portions ( is the number of the states) and each portion identied by can be represented as , and (see Fig. 4). During each interval there is no change in the state of the switches and the network turns to an LTI system. The state equations for interval can be written as (2) is the input vector, the state vector and where the output vector. If we dene and to be equal to the input and output respectively during the th interval, and zero otherwise, the state equations in (2) can be reformulated as [14]
Fig. 4. Time intervals for the state space analysis.

calculated by reforming the state equations to a set of difference equations at the switching moments. Consequently the relation between the input and the output will be of the form (5) The input spectrum can be represented as a summation of sinusoidal signals. As a result the innite summation in (3) takes the form

(6) By applying (6) to (3) and taking the Fourier transform, the spectrum of the state vector becomes

(3) has been used to add the In (3) the Diracs delta function effects of the initial conditions to the equations at the beginning of an interval, while subtracting it at the intervals end. Then the output is the sum of all responses from states in the system: (4) Since we are interested in the spectrum of the output of the system we need to take the Fourier transform from (4). It can be shown [15] that if we apply a complex exponential as input, the output state at discrete moments can be

(7) where is the length of the th time interval (see Fig. 4) and is an identity matrix. B. Analysis of the Differential Single Port N-Path Filter We will apply the analysis procedure described in the previous part to derive the output spectrum of the differential N-path lter. Although Fig. 3 illustrates a 4-path architecture, analysis is done for a general differential N-path system. At any moment two capacitors are connected to the differential output through two switches, which are activated with the same phase of the input clock. The resulting time-domain output signal is the superposition of the signals from different capacitors

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Assuming the output voltage is following the voltage on capacitor during interval , based on (8) the Fourier transform of the output can be found as

(10)
Fig. 5. Differential single path circuit and the clock phases for the switches.

at different moments without any overlap. Since there is no interaction between capacitor voltages, the analysis of the simple network illustrated in Fig. 5 sufces, where just one path is illustrated with its timing diagram for the switches. The state equations for this circuit are

The output spectrum is the superposition of contributions for paths, and taking into account the phase shifts between all the contributions the complete output spectrum can be found as

(8) where is the voltage on the capacitor in Fig. 5. If one of the two switches is on, the output voltage will track the voltage on the capacitor. When switches are off, the voltage on the capacitor will be held, but will not affect the output. Hence, the output spectrum contribution will be calculated in the track-mode. As the capacitor will deliver either ( on) or ( on), this contribution is . As a result, and in (7) should be dened from either the rst or the third equation in (8), depending on which switch is on. As a result, according to (8) for and : , where is dened as the 3 dB bandwidth of a single low-pass lter with resistor and capacitor (see Fig. 5). Applying as the input in the state equations in (8) and also assuming that and , we can nd in (6) for as

(11) where for each path (see Fig. 5). According to (11) is composed of components generated by the paths. We will now derive lter characteristics from (11). IV. CHARACTERISTICS OF A DIFFERENTIAL N-PATH FILTER A. Filtering and Harmonic Folding Back Effects For an ideal N-path lter we assume , where is the duty cycle of the multiphase clock. Analysis of (11) shows that is undened for , but we can take the limit of when approaches continuously to zero to nd . Moreover, in deriving (11) we assumed (non-overlapped switching). When , there are periodic time intervals that all the switches are off and the output signal is tracking the input signal (instead of the voltages on the capacitors). The output spectrum contribution generated due to this fact is not considered in (11). In order to include this effect in , the factor should be

(9)

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Fig. 6. Theoretical and simulated curve for , and pF.

at

MHz for

Fig. 7. around the switching frequency for a 4-path lter. This determines the folding back from odd harmonics of the switching frequency MHz .

added to the part which is derived from (11) by taking the limit for to zero. The nal result becomes

(12) Although (12) includes the clock duty cycle effect in the output spectrum, in an ideal N-path lter: . In (12) represents the desired ltering characteristic without any frequency translation. for a 4-path lter with the values of , , pF and MHz is shown in Fig. 6. In Fig. 6 the comparison between the theoretical transfer function from (12) and the simulated results applying Spectre RF PSS-PAC is shown, which t completely on top of each other. Fig. 6 shows band-pass ltering around the switching frequency, for this case with 1.8 dB insertion loss. However, there are also response peaks around odd harmonics of the switching frequency, related to repetitive poles in the denominator of (12). Thanks to the differential architecture, peaking around even harmonics does not occur. From (11) we see that for where and is zero for other values of . Thus the lter not only shows a comb-lter characteristic, but also folding back from input frequencies around to the desired band around . The strongest terms which result in down-conversion in a 4-path lter are shown in Fig. 7. For instance, renders non-zero , modeling folding from and to (both with frequency shift ). For an 8-path architecture the rst folding back will happen from . In general, increasing the number of paths will increase the distance between and the rst folded component around . Often, a low-pass pre-lter will be needed in front of the N-path lter to sufciently suppress harmonic folding. For radio receiver applications, the pre-lter requirements depend on specic blocker scenarios. In fact the folded back power from blockers to the desired band and the amount of degradation in

Fig. 8. N-path lter with switch resistance.

the sensitivity of the receiver must be acceptable. Note that the implementation of a low-pass pre-lter is likely to be feasible, because it does not need to be tunable. In the proposed differential N-path lter, second harmonic folding is cancelled which relaxes the pre-lter transition band. Moreover, increasing can relax the pre-lter transition band requirements. B. The Effect of the Switch Resistance In order to include the effect of the switch resistance in our analysis, we consider the model shown in Fig. 8. Since in the architecture illustrated in Fig. 3, at any moment just two of the switches are on, the model in Fig. 8 includes two switch resistances in front of an ideal N-path lter with zero switch resistances. Employing (11) with , the transfer function from to can be easily found. Using superposition of the and contributions we nd

(13) is set to zero in (13) it returns to the previous form If of (11). Switch resistance can have strong impact on the maximum achievable rejection in N-path lters. To understand this, consider the frequency transfer function including the switch resistance effect for : (14)

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Fig. 9. Switch resistance effect on the maximum rejection of a 4-path lter , pF, MHz, ). (

According to (14), close to the switching frequency the effect of the switch resistance is not signicant ( term is close to 1 and dominates). But for frequencies further away from the switching frequency, where is close to zero, the rst term often dominates and the output can be approximated as . Thus, the maximum lter rejection is limited by the switch resistance, as exemplied by Fig. 9 for the same 4-path lter used for Fig. 6 but now with added. As a conclusion, in order to increase the maximum rejection of the lter, the switch resistance should be very small with respect to the source resistance . C. Harmonic Selectivity in an N-Path Filter In this section we will discuss the selectivity in the harmonics of the switching frequency both in an analytical and intuitive way. Around lter response peaks the lter becomes high-ohmic. To quantify the selectivity around the harmonics of the switching frequency, we approximate (12) for , for odd , resulting in

Fig. 10. (a) Harmonic selectivity comparing the 4-path lter of Fig. 6 with an 8-path lter with the same total capacitance. (b) Odd harmonic selectivity for (eqn.(15)). (c) Waveforms intuitively different number of paths and illustrating 3rd harmonic selectivity and 3rd harmonic folding (down-mixing to ) for a 4-path lter. from

sees the sine-wave for 3/4 of a period. The output after integration is a square wave with frequency , which contains both the fundamental and the third harmonic, illustrating that both harmonic selectivity and harmonic folding occurs. Similar signals can be drawn for a larger number of paths. Doing so, we can observe that for more paths, i.e., greater number of time slots in Fig. 10(c), there is less time to cancel the positive parts of a signal with the negative parts during the integration taking place on each individual capacitor . Larger leads to less attenuation of harmonics at the output [Fig. 10(b)], but less folding back since the staircase approximation in Fig. 2(d) resembles the actual input signal better. D. Input Impedance of an N-Path Filter

(15) where and is the duty cycle of each clock phase. As an example, if we substitute and and , then , i.e., 1.8 dB insertion loss in the pass-band, which ts to Fig. 6. According to (15) increasing N will reduce the insertion loss. As an example, for an 8-path system the insertion loss becomes 0.4 dB. Equation (12) was used to produce Fig. 10(a), comparing a 4-path and 8-path lter with a xed total amount of capacitance. This gure suggests that the lter attenuation around harmonics is reduced by increasing the number of paths. To understand this fact better, notice that the achievable rejection of the lter at the odd harmonics of the switching frequency can be approximated by (15). Assuming ideal clocking (substitute in (15)) the suppression at the harmonics is solely dened by the number of paths. Fig. 10(b) shows the calculated harmonic rejection applying (15). In most cases indeed harmonic suppression decreases by increasing the number of paths, but there are a few exceptions [see Fig. 10(b)]. To get some intuitive insight how harmonic rejection and harmonic folding occurs, we added Fig. 10(c). It shows the time signals for a sine-wave with a frequency of applied to the 4-path lter of Fig. 2(b). Each of the capacitors now

Now by applying (14) and (15) we can derive simple expressions for the input impedance of the N-path lter in Fig. 8 at the switching frequency, its odd harmonics and for frequencies far away from the peak points in Fig. 9. It will be shown that these impedances are all resistive. The effect of the switch resistance can easily be taken into account by substituting (15) in (14) to nd an approximate equation for . To nd the equivalent input impedance of the N-path system we dene . As a result, . For a 4-path system ( , ) we nd (16) Equation (16) predicts that at the switching frequency the input impedance of the N-path system is resistive, which is similar to a tank circuit at the resonance frequency. For , (16) corresponds to the energy conservation based derivation in [12], but (16) can also be used for other values of . For frequencies far away from the switching frequency and its odd harmonics, using (14) we again nd purely resistive input impedance: (17)

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Fig. 11. (a) Effects of increasing and decreasing of the clock duty cycle. (b) Insertion loss changes due to the duty cycle reduction.

For an ideal system (17) reduces to . Intuitively this can be understood because the capacitors act like a short circuit for . We can conclude that for the switching frequency, the N-path lter has high impedance (16) and for frequencies far away from the switching frequency, it renders small impedance (17). Later, in Section IV-F, we will apply derivations in (15)(17) to derive a simple RLC model for the N-path lter. In Section V, (16) also will be applied to dene the required conditions for input power matching. E. The Effect of the Duty Cycle of the Clock When the duty cycle of the multiphase clock is smaller than , all switches are off periodically for some time and the output signal of the N-path lter simply tracks the (unloaded) input signal. Applying (12) for a 4-path architecture, the lter shape for a duty cycle is illustrated in Fig. 11(a). Comparing to the ideal case , notice from (17) that reducing the duty cycle from results in higher input impedance for the frequencies far away from the switching frequency and its odd harmonics, which translates to less rejection. On the other hand the reduced duty cycle decreases pass-band insertion loss, as predicted by (12) and also (15) [see Fig. 11(b)]. Note that the degradation of the maximum rejection is much more than the reduction in the pass-band loss. As mentioned in Section III, our analysis does not include the case for which two switches can be on at the same time, resulting in undesired charge sharing between capacitors. Fig. 11(a) also shows simulation results for two overlapping clock cases: 1) and , resulting in complete destruction of the lter shape; 2) , , where the switch resistance still limits the charge sharing between capacitors and some ltering remains, but with large insertion loss. F. RLC Model, Bandwidth and Quality Factor Around , the lter transfer function as shown in Fig. 6 resembles that of a high-Q tank circuit. Now we want to quantify this similarity and nd an equivalent RLC model that predicts the quality factor and bandwidth for the N-path lter. Although (11) encompasses a repetitive pattern of poles and zeros, we are mostly interested in poles which occur close to the switching frequency. Equating the denominator of in (12) to zero to nd the poles, we nd ,

Fig. 12. Equivalent RLC circuit model for the N-path lter.

, indeed odd harmonics of . In order to make a narrowband approximation, we just consider the poles close to the switching frequency, which are and set these poles equal to the poles of the transfer function of Fig. 12, which is shown in (18): (18) As a result, and in the RLC model can be found as (19a) (19b) in the RLC model is already derived in (16) The value of for a 4-path system with for the switching frequency. Note that and are independent of , in contrast to . However, the term in the denominator of (19b) can be non-negligible compared with . Thus, the maximum in the transfer function can be slightly shifted to higher frequencies, which also ts with the N-path lter response. For this shift is negligible. To verify the validity of the RLC model, consider a 4-path lter with and pF. Employing (16) and (19), we nd pF, nH, and . The comparison between the RLC model and the exact transfer function in Fig. 13 shows a nearly perfect match around the switching frequency. Applying the RLC model, we can nd the bandwidth as . Intuitively this can be understood considering that in Fig. 5 the resistor value charging the capacitor is and the capacitor sees this resistor value for a fraction of the period, i.e., the effective resistor is . Therefore, the 3 dB bandwidth becomes times the low-pass lter bandwidth dened by . Finally, for a 4-path system and . Thus, we see that the bandwidth not only depends on the

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Fig. 13. Comparison of the transfer of the RLC model with the full N-path lter model (11).

Fig. 14. Image and second harmonic rejection with phase error in the driving clock phases.

RC value for each path, but also on the duty cycle of the clock. Comparing a 4-path and an 8-path lter using identical capacitors in each path, the 8-path lter has half the bandwidth of the 4-path lter. If we keep the total amount of capacitance equal, then the bandwidth will not differ by increasing the number of paths [see Fig. 10(a)]. In this paper, we exploit a 1:2 transformer to increase the source resistance, as seen by the lter, and hence reduce the bandwidth and increase the Q of the lter. A further increase in capacitor area can provide even lower bandwidth and higher Q. Notice that as we discussed intuitively in Section II, the RC in each path of an N-path lter is performing integration on the input signal, when the corresponding switch is on. In contrast to a sampling system, there is no need for the voltage to settle during one on-time of the switch. Thus, the choice of the capacitor size is independent of the switching frequency and can be solely determined based on the desired bandwidth. G. Imbalance Multiphase Clocking and Mismatch in the Paths Next, consider what happens if there is mismatch between paths or if clocking signals deviate from the ideal situation. With mismatch, we can expect that even-order terms are no longer perfectly cancelled and extra frequency components show up. As an example, , which was 0 for an ideal N-path system, can be non-zero around the desired band. According to (11), this renders an image response (e.g., conversion from to ) and also folding back from signals around to . As we use large valued integrated capacitors (10 s of pF), good matching is possible and therefore we focus on quantifying clock phase errors. We model clock pulse width variations in the multiphase clocks and apply (11), considering unequal pulse widths. Fig. 14 shows the calculated image suppression and folding back from . According to Fig. 14, one degree of phase error will result in 42 dB of image rejection and 45 dB suppression of second harmonic folding. H. Noise Most output noise power is due to the thermal noise of the source and switch resistances, where noise folding from around harmonics of should be incorporated. As the switches do not carry DC current, the icker noise of the switches can be neglected. At any moment two switches are in the on-state (see Fig. 3) and since noise contributions of the switches are not

Fig. 15. The model for noise calculation. (a) Source noise. (b) Switch resistance noise.

correlated, we can use the model in Fig. 15, similar to Fig. 8. As the input impedance around according to (16) is signicantly larger than , the noise voltage source has a much higher transfer to than has, which is benecial for the noise gure. Relation (13) between the input and output spectrum of an LPTV system can also be applied to random signals. For Fig. 15(a), we can nd , the thermal noise due to :

(20) The rst term accounts for the noise power, which appears at the output without any frequency translation, and the second part accounts for noise folding, where is the frequency-shifted version of the noise power generated by . Note that in (20) can be calculated by applying in (11). To calculate the output noise power due to switch resistance, we consider Fig. 15(b). Similar to the previous case, the frequency transfer from to can be calculated from (11) with . Then, by applying the procedure described in Section IV-B, the transfer function from to can be derived. Finally, for the circuit in Fig. 15(b), we nd

(21)

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Fig. 16. Micrograph of the 65 nm CMOS chip.

Again, the rst part inside the second parenthesis in (21) corresponds to the noise power without frequency translation. Since is close to 1 around the switching frequency for an N-path lter (e.g., 0.81 for a 4-path architecture), the contribution of the rst part is very small. The second part in (21) is the noise folding term and turns out to be almost negligible. For example, in a 4-path architecture with and , the noise at the output due to switch resistance is approximately 2% of the total noise at the output. Finally, the noise factor can be calculated as . For a 4-path differential lter with , , the calculated noise gure from (20) and (21) is 0.92 dB, which is mainly caused by the noise folding of noise coming from the source resistance . V. IMPLEMENTATION OF A 4-PATH DIFFERENTIAL FILTER A 4-path differential single-port lter is realized in 65 nm standard CMOS technology (see Fig. 16). The block diagram of the lter is illustrated in Fig. 17. Capacitors of 66 pF are realized with NMOS transistors, at 720 mV gate bias, to achieve large capacitance density with good linearity. NMOS switches of are driven by a 25% duty cycle 4-phase clock. The clock phases are capacitively coupled to the gates of the switches, which are biased at 950 mV DC voltage to provide full 1.2 V swing on the gate-source nodes of the switches. This swing insures the maximum achievable linearity for switches with xed sizes. Increasing switch size will improve linearity and decrease the switch resistance. However, larger switch size also means larger parasitic capacitors, affecting the frequency range and clock leakage and also requiring more clock power to drive the switches. An off-chip wideband (501000 MHz, Mini-Circuits JTX-410T) RF transformer serves as a balun for single-to-differential conversion. Moreover, it increases the impedance level seen by the switched-capacitor circuit, increasing lter Q without a signicant degradation in its noise. The architecture in Fig. 17 also has an extra resistor to provide input power matching to 50 . To nd the required conditions for power matching, we will use (16). Neglecting switch resistance, looking into the IC can be written as , where is the driving impedance seen by the IC (see Fig. 17). Then the required value for to provide matching can be found as . For the value for becomes 322 . In practice, the insertion loss of the transformer is non-negligible and in our case it was actually sufcient to implement . In the general case, an equivalent total resistance according to the derived value is needed for good .

Fig. 17. Filter architecture including a balun and buffer amplier for measurements.

Fig. 18. Multiphase clock generator.

The simplied block diagram of the quadrature clock generator with low phase error [17] is shown in Fig. 18. A master clock (CLK) at 4 times the switching frequency is applied from off-chip. A ip-op based divider divides the input clock by four, while an AND gate between node A and B generates a 25% clock. Finally, a shift register implemented with transmission gate ip-ops produces 4-phase clocks to drive the switches. These clocks are then capacitively coupled to the gates of the switches after buffering. VI. MEASUREMENT RESULTS AND COMPARISON An external differential high input impedance buffer amplier is added in the circuit of Fig. 17 to be able to measure with 50 equipment without loading the output of the lter. We utilized Agilent ATF-54143 HEMT transistors to make an amplier with high linearity and low noise in order to have minimum inuence on the measurement results. Measurement results show that the tunable lter in Fig. 17 works from 100 MHz up to at least 1 GHz. Fig. 19 shows measurement results and compares them to a simulation employing an ideal transformer and for MHz, while also including a bond-wire inductance estimate. The buffer amplier gain is de-embedded in all experiments, but the transformer effects are included. Considering the fact that in Fig. 17 is 123 ,

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Fig. 20. Folding back from harmonics at MHz (measured and calculated with (11); even harmonics ideally are fully cancelled).

Fig. 19. Frequency transfer and

at

MHz.

, and NMOS capacitors have the value of approximately 66 pF (simulated value), then according to Section IV-E the bandwidth is calculated as 36 MHz. The measured value for the bandwidth is 35 MHz, which renders a Q ranging from 3 to 29 for ranging between 0.1 and 1 GHz. As derived in Section IV-F the bandwidth of an N-path lter for a given is a function of the RC-time of the lter. Any variation of and will hence result in lter bandwidth deviations from the designed value. While changes of are due to PVT variations, the effective resistance seen by the lter for radio receiver application depends on the effective antenna impedance, which may show signicant deviations. As a result, a capacitor tuning scheme might be needed to keep the bandwidth xed over RC variations. The extra switches needed to add or remove capacitors can have larger size than the main clocked switches, since the capacitive switch parasitics can be absorbed in the wanted capacitance. Moreover, these switches will be static (that is, they do not consume dynamic power). Thus, the maximum rejection of the lter will hardly be affected, nor its noise or linearity. Close to the input is matched to 50 for a narrow band, simplifying the design of a preceding band-pass or low-pass lter to mitigate the harmonic folding problem. The maximum lter rejection is limited by non-zero switch resistance and impedance . Applying (17) and considering a 4-path architecture and for frequencies far away from the switching frequency, input impedance can be approximated as two times the switch resistance . The maximum rejection, , can then be estimated as (22) Thus, increasing by applying the transformer not only results in less bandwidth and hence an increased Q, but also larger maximum achievable lter rejection. More attenuation can also be achieved using wider switches at the cost of clock driver power. In the implemented architecture, , , resulting in dB. Measurement results render 16 dB (Fig. 19). The difference is likely due to the effect of the non-zero rise and fall times of the clock, reducing in an effective duty cycle below 25%. According to (17),

Fig. 21. Measured in-band image rejection for

1 GHz.

this results in larger input impedance and hence a smaller maximum rejection. Fig. 19 also illustrates the frequency selectivity around odd harmonics of the switching frequency. A rejection of 10 dB is found around . Other harmonic responses are lower than the maximum attenuation (16 dB) posed by the switch resistance and parasitics of the board, and are not observable in the measurement results. Fig. 20 compares the calculated and measured values for folding back from all of the harmonics of up to 15th. In this measurement the switching frequency is taken to be 100 MHz and we have removed the transformer and applied a microwave hybrid with wider frequency band in order to remove the bandwidth limitation from the transformer. For odd harmonics, the deviation between measurement and calculated results is due to band limitation imposed by the parasitics of the input of the chip. Even-order harmonics are rejected ideally, but mismatch and clock errors limit the rejection. Fig. 20 shows that spectral aliasing from even harmonics is better than 60 dB. Measurement results of the in-band image rejection are presented in Fig. 21 and prove to be better than 50 dB. The differential architecture also reduces the power leakage from the switching clock to the RF input. In Fig. 17, the rising and falling edges of the clock mainly produce a common-mode signal, which is suppressed by the common-mode rejection of the transformer. At the RF input, a clock leakage power or LO radiation of 62 dBm was measured over the whole band. This is lower than the 57 dBm spurious domain emission limit for frequencies below 1 GHz, as specied by FCC part 15 [18]. Moreover, if a pre-lter is deployed before the N-path lter, the leaked power at harmonics of the switching clock will be suppressed. Note also that in a cognitive radio application, the

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Fig. 24. Measured and simulated noise gure: case 1simulation of the unmatched 4-path lter without the transformer and matching resistor; case 2simulation with ideal transformer and matching resistor included; case 3measurement of the setup in Fig. 17; case 4the effect of the stray inductance of the transformer is included in the simulation of case 2. Fig. 22. Frequency transfer and at between 0.1 and 1 GHz.

TABLE I COMPARISON WITH OTHER DESIGNS

Fig. 23. Measured minimum IIP3 for

1 GHz.

fundamental LO leakage constitutes self-interference. Monte Carlo simulation of process and mismatch variations predict 78 dBm clock leakage in the worst case (100 runs), which suggests that other factors like coupling between wires and substrate may dominate the LO leakage. Better layout may provide less leakage due to coupling. The exible tuning capability of the lter is illustrated in Fig. 22 for swept from 100 MHz up to 1 GHz. In-band proves to be better than 10 dB and the voltage transfer characteristic exhibits a maximum of 2 dB pass-band attenuation over the entire tuning range. Due to parasitics of the transformer and PCB, some peaking occurs at 100 and 200 MHz center frequencies. The main frequency limitations of the current design are related to the clocking circuit and transformer. Wider frequency ranges are possible by improving the clocking circuit and removing the transformer for on-chip applications. The implemented 4-phase clock generator consumes between 2 mW and 16 mW ( 1 GHz, 4 GHz). The rest of the circuit is free of dissipation from the supply. Around the switching frequency, the N-path lter has high input impedance ( in a 4-path lter). Thus, not much current ows through the lter and one might intuitively expect good linearity, certainly for large switch-overdrive voltages ( 800 mV). Fig. 23 shows IIP3 measurement results where the worst value within the 3 dB bandwidth is reported. It is always better than 14 dBm. As derived in Section IV-H, the noise gure of a 4-path lter without transformer and matching resistance is 0.9 dB, which ts to SpecreRF transistor-level simulation results in Fig. 24, case 1. For the architecture in Fig. 17 that we have applied for

the measurement, assuming an ideal 1:2 transformer, the value of in (20) and (21) becomes equal to (see Fig. 17). Considering unity voltage gain for the matched input and calculating the noise power from (20) and (21), a noise gure of 3 dB is calculated, again equal to simulation (Fig. 24, case 2). In Fig. 24, measurement results (the buffer amplier noise gure is de-embedded) are shown as case 3, which shows an increasing trend of noise gure at high frequencies. Simulations show that stray inductance in the transformer and PCB lines lead to an increment of noise gure at high frequencies. Modeling the stray inductance in the secondary of the transformer, in Fig. 17 should be replaced by an impedance which increases with frequency. In this case, the noise generated by the switch resistances at the output node can no longer be neglected, resulting in a noise power increasing with frequency. In Fig. 24, case 4, the simulation of an ideal transformer with matching resistance and 8 nH stray inductance in series with the secondary winding of the transformer is shown. Fitting a coupled inductor model with nite coupling factor to a 50 MHz1 GHz bandwidth transformer indicates that such inductance values are in the realistic range.

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In Table I, the design is compared with two other on-chip lters, one using Q-enhancement [4] and the other an 8-path lter [9], clearly illustrating benets in tuning range, linearity, and noise. In [9], the achieved Q is increased signicantly by increasing source resistance and also increasing the total capacitance value without providing matching. Inserting a resistor deteriorates the noise gure signicantly. Reactive impedance transformation as employed in this paper ensures a low noise gure. VII. CONCLUSION In this paper, an integrated tunable band-pass lter based on N-path periodically time-variant networks is analyzed, implemented, and measured. The proposed differential 4-path architecture provides a high-Q inductorless lter with a decade tuning range (0.11 GHz). The availability of high-quality switches in CMOS technology offers high linearity ( 14 dBm) and compression point (2 dBm). According to theory and measurement, the architecture can have low noise as well (theoretically close to 1 dB for the unmatched case, 3 dB for the matched case). A drawback of N-path ltering is the harmonic folding associated with their time-variant nature. To suppress folding products, a low-pass pre-lter can be used, which however does not need to be tunable. In the proposed differential N-path lter, second harmonic folding is cancelled, which relaxes the pre-lter transition band. Further transition band extension is possible using higher . As N-path lters outperform most receivers in terms of compression point and IIP3, they are one of the few options compatible with CMOS integration to protect receivers against strong blockers. We believe that their extreme tunability by a digital clock and their high linearity and compression point are attractive assets for software-dened or cognitive radio applications. ACKNOWLEDGMENT The authors would like to thank G. Wienk and H. de Vries for their helpful assistance and Z. Ru and M. Oude Alink for valuable discussions. The authors also thank NXP for chip fabrication. REFERENCES
[1] M. Nekovee, Cognitive radio access to TV white spaces: Spectrum opportunities, commercial applications and remaining technology challenges, in Proc. IEEE Symp. New Frontiers in Dynamic Spectrum, Apr. 2010, pp. 110. [2] W. B. Kuhn, A. Nobbe, D. Kelly, and A. W. Orsborn, Dynamic range performance of on-chip RF bandpass lters, IEEE Trans. Circuits Syst. II, vol. 50, no. 10, pp. 685694, Oct. 2003. [3] X. He and W. B. Kuhn, A 2.5-GHz low-power, high dynamic range, self-tuned Q-enhanced LC lter in SOI, IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 16181628, Aug. 2005. [4] B. Georgescu, I. G. Finvers, and F. Ghannouchi, 2 GHz Q-enhanced active lter with low-passband distortion and high dynamic range, IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 20292039, Sep. 2006. [5] L. E. Franks and I. W. Sandberg, An alternative approach to the realization of network transfer functions: The N-path lters, Bell Sys. Tech. J., vol. 39, pp. 13211350, Sep. 1960. [6] L. E. Franks and F. J. Witt, Solid-state sampled data band-pass lters, presented at the 1960 IEEE Solid-State Circuits Conf., Philadelphia, PA, Feb. 1960.

[7] Y. Sun and I. T. Frisch, A general theory of commutated networks, IEEE Trans. Circuit Theory, vol. CT-16, no. 4, pp. 502508, Nov. 1969. [8] M. B. Ghaderi, J. A. Nossek, and G. C. Temes, Narrow-band switched-capacitor bandpass lters, IEEE Trans. Circuits Syst., vol. CAS-29, no. 8, pp. 557572, Aug. 1982. [9] A. El Qualkadi, M. El Kaamouchi J. M., Paillot , D. V. Janvier, and D. Flandre, Fully integrated high-Q switched capacitor bandpass lter with center frequency and bandwidth tuning, in IEEE RFIC Symp. Dig., 2007, pp. 681684. [10] A. Ghaffari, E. A. M. Klumperink, and B. Nauta, A differential 4-path highly linear widely tunable on-chip band-pass lter, in IEEE RFIC Symp. Dig., 2010, pp. 299302. [11] A. Mirzaei, A. Yazdi, Z. Zhou, E. Chang, P. Suri, and H. Darabi, A 65 nm CMOS quad-band SAW-less receiver for GSM/GPRS/EDGE, in IEEE VLSI Symp. Dig., 2010, pp. 179180. [12] B. W. Cook, A. Berny, and A. Molnar, Low-power 2.4-GHz transceiver with passive RX front-end and 400-mV supply, IEEE J. SolidState Circuits, vol. 41, no. 12, pp. 27572766, Dec. 2006. [13] M. C. M. Soer, E. A. M. Klumperink, Z. Ru, F. E van Vliet, and B. Nauta, A 0.2-to-2.0 GHz CMOS receiver without LNA achieving 11 dBm IIP3 and 6.5 dB NF, in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 222223. [14] T. Strm and S. Signell, Analysis of periodically switched linear circuits, IEEE Trans. Circuits Syst., vol. CAS-24, no. 10, pp. 531541, Oct. 1977. [15] M. C. M. Soer, E. A. M. Klumperink, P. T. de Boer, F. E. van Vliet, and B. Nauta, Unied frequency domain analysis of switched-series-RC passive mixers and samplers, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp. 26182631, Oct. 2010. [16] B. Leung, VLSI for Wireless Communication. Englewood Cliffs, NJ: Prentice-Hall, 2002. [17] Z. Ru, N. A. Moseley, E. A. M. Klumperink, and B. Nauta, Digitally enhanced software-dened radio receiver robust to out-of-band interference, IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 33593375, Dec. 2009. [18] FCC 47 CFR Part 15, Oct. 1, 2009. Amir Ghaffari (S10) was born in Oroumieh, Iran, in 1980. He received the B.S. degree (cum laude) in electrical engineering from University of Oroumieh in 2002, and the M.S. degree from Iran University of Science and Technology, Tehran, Iran, in 2006. He is currently pursuing the Ph.D. degree at the IC design group of the University of Twente, Enschede, The Netherlands. His research focuses on the analog CMOS frontends for cognitive radio applications.

Eric A. M. Klumperink (SM06) was born on April 4, 1960, in Lichtenvoorde, The Netherlands. He received the B.Sc. degree from HTS, Enschede, The Netherlands, in 1982. After a short period in industry, he joined the Faculty of Electrical Engineering of the University of Twente, Enschede, The Netherlands, in 1984, participating in analog CMOS circuit design and research. This resulted in several publications and a Ph.D. thesis, in 1997 (Transconductance Based CMOS Circuits). In 1998, he started as an Assistant Professor at the IC Design Laboratory and participated in the MESA+ Research Institute. His research focus changed to RF CMOS circuits, especially for wireless and wireline communication. During AprilAugust 2001, he extended his RF expertise during a sabbatical at the Ruhr Universitaet Bochum, Germany, in the group of Prof. U. Langmann and Prof. H. M. Rein. Since 2006, he has been an Associate Professor, teaching analog and RF IC electronics courses. He participates in the CTIT Research Institute, guiding Ph.D. and M.Sc. projects related to RF CMOS circuit design with focus on cognitive radio, software-dened radio, and beamforming. In 2006 and 2007, he served as a Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, in 2008 and 2009 for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I, and since 2011 for IEEE JOURNAL OF SOLID-STATE CIRCUITS. He holds several patents and has authored and co-authored more than 120 international refereed journal and conference papers. Dr. Klumperink was a co-recipient of the ISSCC 2002 and the ISSCC 2009 Van Vessem Outstanding Paper Award.

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Michiel C. M. Soer (S09) was born in Schoonhoven, The Netherlands, in 1984. He received the M.Sc. degree (cum laude) in electrical engineering from the University of Twente, Enschede, The Netherlands, in 2007. He is currently working towards the Ph.D. degree at the Integrated Circuit Design group at the same university. His research interests include mixers, discrete time systems, and phased arrays in CMOS.

Bram Nauta (F08) was born in Hengelo, The Netherlands, in 1964. In 1987, he received the M.Sc degree (cum laude) in electrical engineering from the University of Twente, Enschede, The Netherlands. In 1991, he received the Ph.D. degree from the same university on the subject of analog CMOS lters for very high frequencies. In 1991, he joined the Mixed-Signal Circuits and Systems Department of Philips Research, Eindhoven, The Netherlands, where he worked on high-speed AD converters and analog key modules. In 1998, he returned to the University of Twente, as a full Professor heading the IC Design group, which is part of the CTIT Research Institute. His current research interest is high-speed analog CMOS circuits. He is also a part-time consultant in industry, and in 2001 he co-founded Chip Design Works. His Ph.D. thesis was published as a book: Analog CMOS Filters for Very High Frequencies (Springer, 1993). Prof. Nauta received the Shell Study Tour Award for his Ph.D. work. From 1997 until 1999 he served as Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, ANALOG AND DIGITAL SIGNAL PROCESSING. After this, he served as Guest Editor, Associate Editor (20012006), and from 2007 to 2010 as Editor-in-Chief for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is a member of the technical program committees of the IEEE International Solid State Circuits Conference (ISSCC) where he has the role of European Chair, the European Solid State Circuits Conference (ESSCIRC), and the Symposium on VLSI Circuits. He is a co-recipient of the ISSCC 2002 and 2009 Van Vessem Outstanding Paper Award. He has served as a Distinguished Lecturer of the IEEE and an elected member of IEEE SSCS AdCom. He is an IEEE fellow.