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EXPERIMENT 7: HAZARDS AND GLITCHES

PURPOSE The purpose of this experiment is to consider the effect of glitches, caused by hazards, in asynchronous sequential circuits. In synchronous sequential circuits, most of the glitches that may occur do not cause problems because they occur in the part of the clock cycle where they do not affect the flip-flops. (In order for this to be the case, the length of clock period must be of proper length.) However, in asynchronous sequential circuits (such as the internal operation of clocked flip-flops) glitches can affect signals on the feedback loops and cause the circuit to enter an incorrect state. HAZARDS IN ASYNCHRONOUS SEQUENTIAL CIRCUITS Assume that a Boolean function, F, can be expressed as a sum of two product terms, F1 and F2. Both these terms might be functions of the same logical variable, A, the value of which is changing. Let the value of A before the change be denoted by A and, after the change, by A*. Consider the expressions: F(A) = F1(A) + F2(A) F(A*) = F1(A*) + F2(A*) A static-1 hazard exits if F1(A)=0 and F2(A)=1, but F1(A*)=1 and F2(A*)=0. In other words, if the value of the Boolean expression F before and after the change is 1, but the 1 is caused by two different product terms that change due to the change in A. In the circuit implementing F, the gate and wire delays may be such that F1 and F2 are simultaneously 0. This will cause F to become 0 for a short time, in which case, the static-1 hazard in the function results in a glitch in the circuit. In general, a hazard is the possibility of an unwanted transient (spike or glitch). In a particular circuit implementing the function, a glitch may or may not occur depending the actual delays in the circuit. An example of a hazard in an asynchronous sequential circuit is given in Example 1. Example 1: The circuit shown in Figure 7.1 illustrates a hazard in an asynchronous sequential circuit. Also, it illustrates the use of a Karnaugh map for identifying a static-1 hazard. (In this notation y is the present state and Y is the next state.) The timing diagram in Figure 7.1(c) is supported by the following discussion: Assume at t=0-, X1X2y = 111; Since Y=X1X2' + X2y = 1.0 + 1.1 = 1, the circuit is stable. Then at t=0, X2 changes from 1 -> 0; 7.1

Then at Then at

t=t1, Y= 1.0 + 0.1 = 0 because the X2y gate changes first. t=2*t1+t2, Y=1.1 + 0.1 = 1

Figure 7.1 An Example Sequential Circuit Containing a Hazard. Two-level AND-OR circuits that contain static-1 hazards can be easily identified from a Karnaugh map of their function. The Karnaugh map pattern is characterized by groupings of 1s 7.2

corresponding to product terms of the function that are adjacent but not overlapped (see Figure 7.1(b)). (It is assumed that only single input change occurs; hence, only adjacent 1s are considered.) Note that the two map groupings independently cover two cells, but the two groupings do not overlap. This shows that the 1 -> 0 transition of the changing variable is a hazard and may generate a glitch. Such a glitch in the next-state function of an asynchronous sequential circuit may cause the circuit to enter the incorrect state. In this example circuit, a glitch during the transition X1X2y = 111 to 101 cannot cause the circuit to enter the wrong state (y = 0), but the transition X1X2y = 101 to 111 might cause the circuit to change to state y = 0. (Examine the transition table to see why this is the case.) A static-1 hazard can be eliminated by adding products to the function (AND gates to the circuit) that cover the adjacent 1-cells. Figure 7.2 shows how a "cover term" can be added that eliminates the hazard of the above example.

Figure 7.2 How to Eliminate a Hazard. There are basically three types of hazards: (1) Static hazard: the possibility of a single momentary transient in an output signal of a combinational circuit that should have remained static in response to an input change. These are further divided into static-0 and static-1 hazards. (Note that the combinational logic can be part of a sequential circuit and the resulting glitches can cause incorrect state changes as the preceding example illustrates.) (2) Dynamic hazard: the possibility of multiple changes in an output signal of a combinational circuit that should change only once in response to an input change. (3) Essential hazard: the possibility of an incorrect state transition in an asynchronous sequential circuit caused by input changes propagating to different feedback loops (next-state variables) with different delays.

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In two-level combinational logic, dynamic hazards cannot exist and static hazards can always be eliminated by the addition of gates. However, an essential hazard is unique to asynchronous circuits and its existence depends upon the structure of the state (transition) table of the circuit. An essential hazard does not depend upon the implementation of the transition table; hence, an essential hazard cannot be eliminated by adding gates or other manipulations of the next-state logic. However, the effects of essential hazards can be eliminated by adjusting the delays in the feedback loops of the circuit; in general, this requires adding inertial delays in the feedback loops so that no state variable changes until an input change has propagated to all the next state variables. Example 2: An asynchronous circuit with output changing on each rising edge of its input (clock).

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Figure 7.3 Design Development for the Binary Toggle Circuit Note that Y1 would contain a static-1 hazard if the y1y2 product were not included in its expression. Similarly, Y2 would contain a static-1 hazard if the product y1y2 were not included. With these terms included, Y1 and Y2 are free of static and dynamic hazards. The timing diagram shown in Figure 7.4 demonstrates the sequential behavior of the toggle circuit defined under the assumption that all gate delays are equal.

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Figure 7.4 A Timing Diagram for the Binary Toggle Circuit Now the delay of the NOT gate which is connected to CLK(H) (NOT gate A) is increased to 7t. The effects of an essential hazard can be seen. Figure 7.5 shows that y1's response to the risingedge of CLK is delayed by seven delay units, and because of this added delay the circuit is cycled from a->b->c->d (stable) without stopping at state b for each rising each of CLK. With the circuit starting in state a (00), the change in CLK to 1 causes y2 to change to 1 and the circuit should be stable in state b (01). However, because of the large delay in the inverter A, CLK(L) is still 1 and the gate with inputs CLK(L) and y2 forces y1 to change to 1. The circuit is now in state c (11). This change in y1 feeds back to the y2 logic causing it to change back to 0 and the circuit ends up in stable state d (10). This is the effect of an essential hazard when the response of a feedback loop to an input change is excessively delayed in comparison to other feedback loops. Its effect can be eliminated by equalizing the delays in the feedback loops. In this example an inertial delay is needed in the y2 feedback loop. The delay must be an inertial delay rather than a pure delay so that the temporary change is filtered out.

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Figure 7.5 A Timing Diagram Illustrating an Essential Hazard Effect Caused by Excessive Delay in an Inverter. Note that when all gates have the same delay the circuit can operate normally. This suggests that circuits which are prone to misbehavior due to essential hazards need not always be cast aside as bad. You need only use worst case delay analysis to determine if an essential hazard is going to be a problem. PROBLEMS WITH SYNCHRONOUS CIRCUITS 1. Metastability The metastable state is the condition that is roughly defined as "half SET and half RESET". In other words, both outputs are at the threshold voltage level, as shown in Figure 7.6.

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Figure 7.6 An Illustration of the Output in its Metastable Condition Induced by a "Runt" Pulse. Metastability can occur if the setup or hold time of a synchronous device is violated. The setup time is violated if a data or control input does not stabilize enough time prior to the active clock edge. The hold time is violated if a data or control input does not remain stable long enough time after the active clock edge. The output of a device in metastability can be in a nonlogical state (as illustrated above) or the device can be unresponsive to clock inputs for many propagation delay times. The remedy to prevent metastability from occurring is: Use only one clock in a system, do not communicate asynchronously, and design completely synchronously adhering to the setup and hold time requirements of all synchronous devices. 2. Clock Skew Clock skew is the time shift in the arrival of the triggering edge of the system clock to various flip-flops caused by delay introduced by buffer devices and the propagation delay of conducting paths (wires). Skew is of particular importance when shift register operation is involved. For example, there are many times when one memory device (destination device) is intended to load the output of another driving device (source device) on the active edge of the clock, when this same active edge is in turn changing the output of the source device (see Figure 7.7). If clock skew delays the loading of the destination device for a period of time greater than it takes to change the present output of the source device, incorrect data is loaded into the destination device. The clock skew causes the data input to the destination device to be unstable during the SETUP and HOLD time period of the destination device. The delay in the clock drivers (buffers) 7.9

and in the wires connecting them to the flip-flops must be adjusted so that this does not happen in order to assure reliable operation.

Figure 7.7 An Example of the Missed Data Caused by Clock Skewing

*Source: William I. Fletcher "An Engineering Approach To Digital Design"

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PRELAB 1. An asynchronous sequential circuit has the next state equation Q+ = AB + Aq where A and B are inputs, Q is the present state, and Q+ is the next state of the circuit. a) Draw the logic diagram for the circuit using NAND gates and inverters, if needed. (The circuit must match the equation as given.) b) Construct the transition table for the circuit. c) Analyze the circuit to determine if it contains combinational logic hazards. (Assume only one input, A or B, can change at a time.) Determine whether these hazards could cause glitches for some combination of gate delays and whether the glitches could cause the circuit to make an incorrect state transition. d) Using typical to maximum LS NAND and inverter gate delays, determine what combination of delays could result in incorrect operation. 2. Breadboard the circuit from 1 above. (Note that in the procedure below you are asked to insert two inverters in series in different paths of the circuit to lengthen the glitches and, also, to modify the circuit so that it is free of glitches. You may want to breadboard the circuit so that these modifications are easy.)

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PROCEDURE Before performing the procedures listed below, read the report section of the experiment to assure you make all required measurements and record all required data. When creating a circuit, use the Motorola library. A. Static Hazard In Asynchronous Circuits 1. Simulate the circuit from Part 1 of the Prelab to demonstrate the possibility of glitches and incorrect state transition. For each case add two inverters in series in the proper path to length the glitch or cause the incorrect state transition. 2. Print the resulting timing diagrams. 3. Modify the circuit to eliminate the hazard and simulate the new circuit using the same delays to observe its behavior. (The modified circuit must still use NAND gates and inverters, if needed.) 4. Print the resulting timing diagram. 5. Use your breadboard of the original circuit (with the extra two inverters) to measure the length of each the glitch and observe the incorrect state transition using the pulse generator and the oscilloscope. B. Essential Hazard In Asynchronous Circuits 1. Simulate the circuit in 7.3(f) so as to observe the erroneous effect of the essential hazard. 2. Set the delay of all gates to 2 units and print out the corresponding timing diagram. 3. Set the delay of NOT gate A to 14 units and print out the corresponding timing diagram.

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EXPERIMENT 7--HAZARDS AND GLITCHES FINAL REPORT

I. Hazards In Asynchronous Sequential Circuits a). Draw the circuit of Part 1 in the Prelab.

b). Plot the corresponding timing diagrams in the space below. Indicate on the timing diagram where the glitch occurred and what causes the glitch to occur.

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c). Draw the modified circuit that eliminates the hazard in the space below.

d). Plot the timing diagrams corresponding to above circuit in the space below and explain why the glitches disappeared.

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e). Sketch the glitches obtained in part A.5.

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f). Do the sizes of the glitches correspond to your predicted value? Why or why not?

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II. Essential Hazard In Asynchronous Circuits a). Redraw the circuit in 7.3(f) in the space below.

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b). Plot the timing diagram corresponding to above circuit (when all gates have the same delay). How does the state of the circuit relate to positive edges of the clock?

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c). Sketch the timing diagram when delay of NOT gate A is increase by 7 times. Explain why the timing diagram looks as it does. Does it realize the function it is supposed to realize?

d) Suppose the circuit is started in the state y1y2 = 11 with CLK = 0, and then CLK is changed to 1. If the inverter delay is 7 times the other gate delays, will the circuit change to the correct next state (10) or will it change to state 01? Explain your answer.

**Attach the timing diagrams from procedures A and B to your report. III. Conclusion Why is the design of asynchronous sequential circuits more difficult than the design of synchronous (clocked) sequential circuits? In view of this difficulty, why does anyone design asynchronous sequential circuits?

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