ST. JOSEPH COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF ELECTRONIC AND COMMUNICATION ENGINEERING LESSON PLAN Faculty Name: B.N.

SIVA PRASANNA KUMAR Subject Name: Digital Electronics Year / Sem : II/III AIM
To learn the basic methods for the design of digital circuits and provide the fundamental concepts used in the design of digital systems.

Designation: Branch:

Lecturer ECE

Subject code: EC2203

OBJECTIVES
To introduce basic postulates of Boolean algebra and shows the correlation between Boolean expressions To introduce the methods for simplifying Boolean expressions To outline the formal procedures for the analysis and design of combinational circuits and sequential circuits To introduce the concept of memories and programmable logic devices. To illustrate the concept of synchronous and asynchronous sequential circuits UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 9 Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of Duality - Boolean expression - Minimization of Boolean expressions Minterm Maxterm - Sum of Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditions - Quine-McCluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR- Implementations of Logic Functions using gates, NANDNOR implementations Multi level gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics Tristate gates. UNIT II COMBINATIONAL CIRCUITS 9 Design procedure Half adder Full Adder Half subtractor Full subtractor - Parallel binary adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/Subtractor - BCD adder Binary Multiplier Binary Divider - Multiplexer/ Demultiplexer decoder - encoder parity checker parity generators code converters - Magnitude Comparator. UNIT III SEQUENTIAL CIRCUITS 9 Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application table Edge triggering Level Triggering Realization of one flip flop using other flip flops serial adder/subtractorAsynchronous Ripple or serial counter Asynchronous Up/Down counter - Synchronous counters Synchronous Up/Down counters Programmable counters Design of Synchronous counters: state diagram- State table State minimization State assignment - Excitation table and maps-Circuit implementation - Modulon counter, Registers shift registers - Universal shift registers Shift register counters Ring counter Shift counters - Sequence generators. UNIT IV MEMORY DEVICES 9 Classification of memories ROM - ROM organization - PROM EPROM EEPROM EAPROM, RAM RAM organization Write operation Read operation Memory cycle - Timing wave forms Memory decoding memory expansion Static RAM Cell-Bipolar RAM cell MOSFET RAM cell Dynamic RAM cell

Programmable Logic Devices Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA, PAL. UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS 9 Synchronous Sequential Circuits: General Model Classification Design Use of Algorithmic State Machine Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits Incompletely specified State Machines Problems in Asynchronous Circuits Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG. TEXT BOOKS 1. M. Morris Mano, Digital Design, 3rdEdition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003. 2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rdEdition., Vikas Publishing House Pvt. Ltd, New Delhi, 2006 REFERENCES 3. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006 4. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002. 5. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003. 6. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6thEdition, TMH, 2003. 7. William H. Gothmann, Digital Electronics, 2ndEdition, PHI, 1982. 8. Thomas L. Floyd, Digital Fundamentals, 8thEdition, Pearson Education Inc, New Delhi, 2003 9. Donald D.Givone, Digital Principles and Design, TMH, 2003. UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

Session Date No. 1. 10.7.13 2. 3. 4. 5. 6. 7. 8. 9. 11.7.13 12..7.13 16.7.13 16.7.13 17.7.13 18.7.13 19.7.13 23.7.13

Topics to be covered Introduction to Digital Electronics, Boolean postulates and laws, De-Morgans Theorem. Principle of duality, Minimization of expressions using Boolean laws. Minterm, Maxterm, Sum of Products (SOP), Product of Sums (POS). Minimization of expressions using Karnaugh map-3&4 variable K-map. 5-variable K-map, K-map with dont care conditions. Quine-McCluskey method of minimization. Truth table, symbol and expressions of AND, OR, NOT, NAND, NOR, ExOR and Ex NOR. Implementation of logic function using Universal gates, Multi level-output gate implementations. Characteristics of TTL and CMOS Logic, Tristate gates.

Ref 1 1 1 1,5 1,5 2,5 2 1,2,5 1

Page.No. 1-33to40 1-40to43 1-44to51 1-64to82 5-120-129 1-64to82 5-129-135 2-67to72 5-149-164 2-77to89 1-82-89 2-99to110 5-173-195 1-410-427

Teaching Method BB BB BB BB BB BB BB BB BB,OHP

UNIT II

COMBINATIONAL CIRCUITS

Session No. 10 11 12 14 15 16 17 18 19
UNIT III

Date 23.7.13 24.7.13 25.7.13 26.7.13 30.7.13 30.7.13 31.7.13 1.8.13 2.8.13

Topics to be covered Design of half adder and full adder. Design of half subtractor, full subtractor and parallel binary adder/subtractor. Disadvantages of parallel adder carry look ahead adder. Design of serial adder/subtractor and BCD adder. Binary multiplier and binary divider. Design and implementation of Multiplexer and Demultiplexer. Encoder and decoder.Odd, Even: Parity generators and checker. Code converters. 2-bit, 4-bit Magnitude comparator.

Time 1 2 2 2 2 2 2 2 2

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SEQUENTIAL CIRCUITS

Session No. 20 21 22 23 24 25 26 27 28 29 30
UNIT IV

Date 6.8.13 6.8.13 7.8.13 8.8.13 9.8.13 13.8.13 13.8.13 14.8.13 16.8.13 20.8.13 20..8.13

Topics to be covered Latches, Characteristic table and equation of SR, JK, D and T flip flop. Level triggering and edge triggering of flip flop. Conversion of one flip flop to other flip flops Realizations of one flip flop using other flip flops, Master-Slave flip flop. Asynchronous: ripple counter, Up/Down counter. Synchronous: Up/Down counters, Programmable counters. State diagram, minimization and State assignment. Excitation table and maps. Design of Modulo-n counter. Shift registers, SISO, SIPO, PISO, PIPO Universal shift register Ring counter and shift counter. Design of sequence generators.

Time 2 2 2 1,2 2 1,2 2 2,8 2,8 2 2

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Teaching Method BB BB BB BB BB BB BB BB,OHP BB,OHP BB,OHP BB

MEMORY DEVICES

Session No. 31 32 33 34 35 36 38 39 40

Date 21.8.13 22.8.13 23.8.13 27.8.13 27.8.13 28.8.13 29.8.13 30.8.13 3.9.13

Topics to be covered Classification of memories- ROM, RAM ROM Organisation - PROM, EPROM, EEPROM. RAM organization, - Write and Read operation, Memory cycle and Timing wave forms. Memory decoding and memory expansion. Static RAM Cell, Bipolar RAM cell Dynamic RAM Cell and MOSFET RAM cell. Introduction to Programmable Logic Devices. Implementation of combinational logic circuits using PLA. Implementation of combinational logic circuits using ROM, PLA, PAL Implementation of combinational logic circuits using PAL. Field Programmable Gate Arrays (FPGA).

Time 2 2 2,8 2 2 2 2 2 2

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Teaching Method BB BB BB BB BB BB BB BB BB,OHP

UNIT V

SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS

Session No. 41 42 43 44 45 45 46 47 48

3.9.13 3.9.13 4.9.13 5.9.13 6.9.13 10.9.13 10.9.13 11.9.13 12.9.13 13.9.13

Topics to be covered General sequential Model Classification and design of synchronous sequential circuit. Analysis of Synchronous Sequential circuit. Algorithmic State Machine. Design of fundamental mode Incompletely specified State Machines Design of Pulse mode - Incompletely specified State Machines Problems in Asynchronous Circuits - Hazards and types of hazards. Design of Hazard free Switching circuits. Design of Combinational and Sequential circuits using Verilog. Design of Combinational and Sequential circuits using Verilog.

Time 2 2 2,9 2,4 2,4 2 2,9 10

Ref 2-453to469 2-453to469 2-469to493 9-444to490 2-495to506 4-442to470 2-507to519 4-442to470 2-520to525 2-525to528 9-561to575 10-148-157

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10 10-148-157

STAFF INCHARGE

HOD

PRINCIPAL