Fpga Lab Manual - Student

BUGHAW ELECTRONIC SOLUTIONS AND TECHNOLOGIES, INC.
CPLD/FPGA Laboratory Manual

Using the MAX II Starter Kit
Preface
This laboratory manual is aimed at undergraduate students taking up Computer Engineering, Computer Science, Electronic and Communications Engineering or other related courses. However, this manual may also be used by instructors as reference. The users of this manual are assumed to have basic knowledge of Verilog Hardware Description Language or Verilog HDL. However, references and on-line tutorials for Verilog HDL are widely available. Thus, learning Verilog HDL will be quite easy. Exercises in this laboratory manual are built on from previous exercises. Thus, before proceeding on to the next exercise, students must be familiar with the previous exercises. Also, the level of complexity of the exercises increases as one proceeds through the laboratory manual. In each exercise, there are questions that need to be answered first before proceeding with the exercise. However, answers to these questions are located at the back of the laboratory manual. Moreover, the complete Verilog HDL source codes for all the exercises as well as pictures or videos of the expected results are included in the CD, which will be given to the instructor.
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2008 BEST, Inc. All Rights Reserved
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................4 Minimum System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 GFEC Max II Starter Kit Component view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 Notations and Conventions ............... 6 .................................
Altera Quartus II 7.0 Web Edition Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Kit Exercise 1 Introduction to the Max II Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ................................. ..................................
Exercise 2 Controlled LED . . . . . . . . . . . . . . 25 Exercise 3 Blinking LEDs . . . . . . . . . . . . . . . 26
Exercise 4 LED Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Exercise 5 LED Operation Using a Push Button . . . . . . . . . . . . . 31 Exercise 6 7-segment LED Display (I) . . . . . . . . . . . . . . 33 .................
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Exercise 7 7-segment LED Display (II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Exercise 8 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

40 Exercise 9 Counter With Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Exercise 10 PC to Max II Via RS232 . . . . . . . . . . . . . . 46 Additional Projects . . . . . . . . . . . . . . 49 ..........................
........................................ .....................................
Answers to questions . . . . . . . . . . . . . . . 50
Appendix A .......................................................... . . . 52 Appendix B .......................................................... . . . 60
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Introduction
The Max II Starter Kit emulation board is specifically designed for Altera Max II device family. It can be used by designers interested in simulating and synthesizing programmable logic circuits in their applications. The emulation board is based on the EPM1270T144C5E5 CPLD device. It provides 1270 logic elements (LEs), 116 I/O lines, and 8-Kbit user Flash Memory. Moreover, it also provides a few peripherals for your digitallogic designs.
Minimum System Requirements
Pentium III (400 MHz or faster) based computer, running one of the following operating systems: Microsoft Windows 2000 or Microsoft Windows XP 1.5 GB free hard disk space 256 MB RAM 4
parallel and serial ports LAN card
GFEC Max II Starter Kit

A. Component view
1 8
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5 4 2 33
1. 4 Digital seven segment LED Displayers (DS1) 2. 8-bit DIP Switches (SW6) 3. 4 Push Buttons (SW1 SW4) 4. 8 LEDs (D1 D8) 5. 16 MHz oscillator 6. UART Connector (J8) 7. 4 Extension I/O Connectors (J1 / J2 / J3 / J4) 8. DC Input Connector 9. JTAG 5x2 Header Connector 10. 44 Pin PLCC Socket for MPU (8051)
9 7 6
Note: Please refer to Appendix A for a detailed explanation of each component. Warning: Please note that the extension I/O voltage on this emulation board can only receive up to 3.3V. If by mistake you end up burning the EPM1270T144C5 CPLD, you can buy a new device and re-solder the new CPLD onto the board. B. Set up 5
1. Connect one side of the download cable to the JTAG 5x2 header connector on the emulation board and the other side to the parallel port of the CPU.
2. Connect the AC adapter to the DC input connector on the emulation board.
Notations and Conventions

This section provides an explanation of the notations that will be used throughout this manual.

Codes to be written are in Courier New font. Folder directories and file names are also written in Courier New font. Boldface font may indicate a series of buttons and menus to access or some notes and hints. Words enclosed by the less than and greater than sign (< >) are keys in your keyboard (e.g. <Tab>) while words enclosed in double quotation marks ( ) may be an option that needs to be selected. Boldface greater than sign (>) indicates a series of buttons or menus to access. The file naming conventions in this module consists of the word exercise concatenated with the exercise number (e.g. exercise1 for the first exercise). Most of the exercises in this manual build on from 6
the previous ones thus; it is good practice to save each exercise in different file names.
Altera Quartus II 7.0 Web Edition Installation

This will guide you through the installation process of the Integrated Development Environment (IDE) that will be used throughout the exercises. 1. Open the CD that comes with this manual and double-click on the file named 70_quartus_free.exe (the icon is shown in the figure below). The InstallShield Wizard should pop up and it will direct you to the installation menu.
2. Click Next to continue installation
3. Select the I accept the terms of the license agreement option and click Next.
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4. Type in your name and press <Tab> on the keyboard. Next, type in the name of your school or company.
5. After entering the needed information, click Next.
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6. This is the default location where the program will be installed. Click Next.
7. This is the default folder name where all the needed files will be saved. 9
Click Next.
8. Select the Complete option and click Next.
9. This shows the complete setting of the installation. Click Next. 10

10. Yes.
Wait for the installation to end. If this dialog box appears, click
11. Installation has completed. You have the option to view the readme.txt or to launch Quartus immediately. This is done by clicking the button beside the option. After selecting the desired option/s, click
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Finish. 12. After installing Quartus II 7.0, apply for a license from Altera. Open your internet browser (e.g. Internet Explorer, Mozilla Firefox, etc.) and go to http://www.altera.com/support/licensing/lic-index.html. 13. Click Get Licenses > Quartus II Web Edition Software License.
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14.
Fill in the needed information and click Sign in.
15. Click Start (as shown in the left figure below). Click Run and enter <cmd>. Then, click OK.
16. Type in <ipconfig /all> and copy the Network Interface Card (NIC) number
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17. Enter your Network Interface Card (NIC) number that you have copied in the previous step. Choose the Yes and Academic options. Then, click Continue.
18. Open your email account and download the license file to C:\altera\70\quartus and rename it to license.dat.
19.
Navigate to the Desktop and double-click on the Quartus icon.
20. Upon opening of Quartus, a dialog box appears that asks you to enter your license. Select Specify valid license file option and click OK.
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21.
In the main menu, click on Tools > License Set up.
22. Click on the drop down menu located at the right and navigate to the directory C:\altera\70\quartus. Select the license file license.dat and click Open.
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23. Click OK to finish the set up and installation of Quartus II 7.0 Web Edition.
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Exercise 1 Introduction to the Max II Starter Kit

A. Objectives This exercise aims to familiarize the student with the basic operation of the Max II Starter Kit (M2SK) and the Quartus II 7.0 Web Edition Integrated Development Environment (IDE). By the end of this exercise, the student should be able to know the basic functionalities of the IDE and he/she will already be able to design Verilog programs that can control the different peripherals of the M2SK. B. Instructions Creating A Project 1. Navigate to the Desktop and double-click the Quartus II 7.0 Web Edition icon. This will open up the IDE.
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2. Create a new project by selecting File > New Project Wizard. This will guide you in creating your project.
3. A dialog box will pop up, click Next. 4. Another dialog box will pop up asking for your working directory. The working directory is where all of your projects will be saved. Type C:\FPGAprojects\exercise1 for the working directory and exercise1 for both the project name and the top-level design entity. Click Next. Note: The module name should exactly match the name of the toplevel design entity. It is case sensitive.
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5. A warning dialog box will then appear stating that the directory you typed does not exist. Click Yes. The directory that you have specified will automatically be created for you. Click Next. 6. Select the device to be used from the drop down list. Click Max II.
7. From the list of devices, choose EPM1270T144C5. Click Next.
8. Click Next. 9. Click Finish to complete the creation of the new project. Creating A Program File 19
10. Select File > New or press <Ctrl+N> to create a new blank file. A dialog box will pop up asking you the type of file you want to create. Select Verilog HDL file. Click OK.
11. Save (File > Save As...) this new file as exercise1.v. Make sure that the Add File To Project check box below is selected.
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12. Type the following code on the exercise1.v panel (ignore the numbers on the left side).
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 module exercise1 (clk, rst, led); input clk, rst; reg [7:0] state; output [7:0] led; assign led = state; always @ (posedge clk) if (rst == 0) state <= 8'b11111111; else state [0] <= 0; endmodule
Code Explanations Line No. Explanations 1 Words in blue are reserved words. Any Verilog program starts with the reserved word module <module_name>. In this example, the module is named exercise1. After declaring the module name, the port declaration follows. For this module, it has the following ports: clk, rst, led. Input ports Output ports data type (state: 8 bits) Output ports led will have the value of state This block is executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 (pin 23 of the EPM1270T144C5) is pushed down. If yes, all the 8 bits of state is 1. As a result, all the 8 LEDs (pins 1-8 of the EPM1270T144C5) are turned off. If not, state [0] or the least significant bit (LSB) of state is set to 0. As a result, one of the LEDs lights up. Signifies the end of the module
3 4 5 7 9-13
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13. Save your file by pressing <Ctrl+S> or select File > Save in the main menu. 21
Pin Assignments Quartus II provides a few methods to specify pins. One of them is to use the menu option Assignments > Pins to specify the pins individually while the other is to use a Tcl script, wherein this will be the one used throughout the succeeding exercises. 14. Create a new Tcl script file, File > New. A dialog box will pop up asking you the type of file you want to create. Select Other files > Tcl Script. Click OK. 15. Save (File > Save As...) this new file as pin_assign.tcl.
16. Type the following code on the pin_assign.tcl panel (ignore the numbers on the left side). port names
Note: The port names written in the Tcl script file should match with the port names written in the program file. Moreover, see the appendix to read in more detail the pin assignments of the other peripherals. 17. Type source pin_assign.tcl in the TCL console box located inside
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Quartus. Press <Enter> to finish the pin assignments. Program Compilation 18. Perform compilation by selecting in the main menu Processing > Start Compilation or clicking on the icon as shown below to compile your file.
19. Wait for the compilation to finish. When the compilation is successful, click OK.
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Program Download 20. Check if the Max II Starter Kit is turned on and connected to your PC. 21. Open Programmer by selecting in the main menu Tools > Programmer.
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22. Select exercise1.pof and check Program/Configure. Click Start.
23. Once the program has finished downloading, you will be able to see the results immediately on your board.
C. What To Expect The D1 LED in the Max II Starter Kit (M2SK) should light up and when you press SW1, which is the reset (rst), the D1 LED in the M2SK would be turned off. SW1
lights up D. Summary In this exercise, you have learned how to create Verilog HDL files and Tcl script files using the Quartus II 7.0 Web Edition IDE. Moreover, you have also learned to access and control the D1 LED on the Max II Starter Kit (M2SK). 25
Exercise 2 Controlled LED

A. Objectives This exercise aims to design a Verilog program that controls the D1 LED with the use of a push button specifically, the SW2 push button. When SW2 is pressed and D1 LED is turned off, D1 LED will light up. However, when SW2 is pressed and D1 LED is lit up, D1 LED will be turned off. Note: D1 LED is low-enabled. B. Questions

What is the meaning if the LED is low-enabled? What pin in the Max II Starter Kit is designated to the SW2 push button?
C. Instructions 1. Create a new project and save it to the working directory C:\FPGAprojects\exercise2 and name your current project as exercise2. 26
2. Create a new Verilog HDL file and save it as exercise2.v. 3. Modify your exercise1.v code so that the D1 LED is controlled by a push button that is, when the push button is pressed and D1 LED is turned off, D1 LED will light up. However, when the push button is pressed and D1 LED is lit up, D1 LED will be turned off. Type in your code on the exercise2.v panel and save. 4. Compile your file and edit the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to include the pin assignment for SW2. Copy the new Tcl file to the directory where your current project is saved. 5. Download your program to the M2SK and see what happens. D. Summary In this exercise, you have learned how to access and control the D1 LED of the Max II Starter Kit (M2SK) with the use of a push button.
Exercise 3 Blinking LEDs

A. Objectives This exercise aims to design a Verilog program that controls the blinking of all the LEDs (D1 to D8) in the Max II Starter Kit (M2SK). The LEDs should blink every half a second or 0.5 seconds at the same time. Note: The system clock (clk), pin 18 of the EPM1270T144C5, is 16 MHz. There should be a reset (rst) assigned to SW1 or pin 23 of the EPM1270T144C5. The switch is low when pushed down but at default, it is normally high. Also, the D1-D8 LEDs are low-enabled. B. Questions

What pins in the Max II Starter Kit are designated to D1-D8 LEDs? How are you going to set the blinking interval for 0.5 seconds (i.e. the LED blinks for every 0.5 seconds)?
C. Sample Code 27
// This code lets the D1 LED blink for every 0.5 seconds that is, D1 LED is on for 0.5 seconds and off for the next 0.5 seconds. 1 module exercise3 (clk, rst, led); 2 3 input clk, rst; 4 reg [7:0] state; 5 reg [23:0] counter; 6 output [7:0] led; 7 8 assign led = state; 9 10 always @ (posedge clk) 11 if (rst == 0) 12 counter <= 0; 13 else if (counter == 8000000) 14 counter <= 0; 15 else 16 counter <= counter+1; 17 18 always @ (posedge clk) 19 if (rst == 0) 20 state <= 8'b11111111; 21 else if (counter == 8000000) 22 state [0] = ~state [0]; 23 24 endmodule
D. Code Explanations Line No. Explanations 1 Words in blue are reserved words. Any Verilog program starts with the reserved word module <module_name>. In this example, the module is named exercise3. After declaring the module name, the port declaration follows. For this module, it has the following ports: clk, rst, led. Input ports Output ports data type (state: 8 bits, counter: 24 bits) Output ports led will have the value of state This block is executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, counter is set to 0, if not, the value of counter is checked. If the condition is satisfied that is, if counter is equal to 8000000, then, counter is set to 0. If not, counter is incremented. 28
3 4-5 6 8 10-16
18-22
This block is also executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, all the bits of state have the value of 1, as a result, all the 8 LEDs are turned off. If not, the value of counter is checked. If the condition is satisfied that is, if counter is equal to 8000000, state [0] or the least significant bit (LSB) of state is set to the inverse of the previous vale of state [0]. As a result, the value of state [0] changes every 0.5 seconds and the D1 LED lights up for 0.5 seconds and then, it is turned off for 0.5 seconds. Note: Why 8000000? The frequency of the oscillator is 16MHz that is, 16000000 cycles per second. If each transition should only take 0.5 s then, the counter should be set at 16000000/2 or 8000000 before the next transition.
24 E. Instructions
Signifies the end of the module
1. Create a new project and save it to the working directory C:\FPGAprojects\exercise3 and name your current project as exercise3. 2. Create a new Verilog HDL file and save it as exercise3.v. 3. Modify the sample code given above so that not only the D1 LED lights up but all the 8 LEDs and also, all the LEDs blink every 0.5 seconds. Type in your code on the exercise3.v panel and save. Hint: Not only the least significant bit (LSB) of state changes its value but all the 8 bits of state. 4. Compile your file and edit the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to include the pin assignments for D1-D8 LEDs. Copy the new Tcl file to the directory where your current project is saved. 5. Download your program to the M2SK and see what happens. F. Summary In this exercise, you have learned how to access and control the D1-D8 29
LEDs of the M2SK. In the succeeding exercises, you will be asked to output a certain pattern of the LEDs in the M2SK.
Exercise 4 LED Pattern

A. Objectives This exercise aims to design a Verilog program that outputs the pattern below using the LEDs. D1 D4 D5 - D8
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The transition interval for each set is 0.5 seconds. A colored dot means that the corresponding LED lights up. Note: The system clock (clk), pin 18 of the EPM1270T144C5, is 16 MHz. There should be a reset (rst) assigned to SW1 or pin 23 of the EPM1270T144C5. The switch is low when pushed down but at default, it is normally high. Also, the D1-D8 LEDs are low-enabled. B. Questions

What are the uses of case statements in Verilog? Is it necessary to provide a default in case statements?
C. Instructions 1. Create a new project and save it to the working directory C:\FPGAprojects\exercise4 and name your current project as exercise4. 2. Create a new Verilog HDL file and save it as exercise4.v. 3. Modify your exercise3.v code so that the 8 LEDs will output a certain pattern as described above. Type in your code on the exercise4.v panel and save. Hint: Use case statements to output the sequential LED pattern. 4. Compile your file and copy the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to the directory where your current project is saved. 5. Download your program to the M2SK and see what happens. D. Summary In this exercise, you have learned how to output a certain pattern of the LEDs in the M2SK.
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Exercise 5 LED Operation Using a Push Button

A. Objectives This exercise aims to design a Verilog program that outputs the pattern below using the LEDs. D1 D4 D5 - D8
The transition from one set to another is controlled by a push button SW2 32
(pin 24 of the EPM1270T144C5). A colored dot means that the corresponding LED lights up. Note: The system clock (clk), pin 18 of the EPM1270T144C5, is 16 MHz. There should be a reset (rst) assigned to SW1 or pin 23 of the EPM1270T144C5. The switch is low when pushed down but at default, it is normally high. Also, the D1-D8 LEDs are low-enabled. B. Questions

What is a switch bounce? What are possible ways to remedy this problem?
C. Instructions 1. Create a new project and save it to the working directory C:\FPGAprojects\exercise5 and name your current project as exercise5. 2. Create a new Verilog HDL file and save it as exercise5.v. 3. Modify your exercise4.v code so that the LED transition is controlled by a push button. Type your code on the exercise4.v panel and save. 4. Compile your file and copy the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to the directory where your current project is saved. 5. Download your program to the M2SK and see what happens. C. Summary In this exercise, you have learned how to access and control the LEDs using a push button. In the succeeding exercises, you will be asked to output data into the digital display or the 7-segment LEDs.
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Exercise 6 7-Segment LED Display (I)

A. Objectives This exercise aims to design a Verilog program that outputs the letter F to the seven segment display in the Max II Starter Kit (M2SK). B. Questions

Is the segment pin in the 7-segment LED display low-enabled or highenabled? What does it mean? What pins in the Max II Starter Kit are designated to the 4 7-segment LEDs?
C. Sample Code
// This code outputs the number 4 to one of the digital displays of the M2SK. 1 2 3 4 5 6 module exercise6 (clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp); input clk, rst; reg [3:0] state; reg [6:0] number; output m1, m2, m3, m4, a, b, c, d, e, f, g, dp;
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7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
parameter number4 = 7'b1001100; assign {m1, m2, m3, m4} = state; assign {a, b, c, d, e, f, g} = number; assign dp = 1; always @ (posedge clk) if (rst == 0) state <= 4'b0000; else state <= 4'b0001; always @ (posedge clk) if (rst == 0) number <= 7'h7f; else number <= number4; endmodule
D. Code Explanations Line No. Explanations 1 Words in blue are reserved words. Any Verilog program starts with the reserved word module <module_name>. In this example, the module is named exercise6. After declaring the module name, the port declaration follows. For this module, it has the following ports: clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp Note: m1 m4 (four digital displays) a, b, c, d, e, f, g, dp (each LED in the 7segment display including the dot point) 3 4-5 6 8 Input ports Output ports data type (state: 4 bits, number: 7 bits) Output ports Assigns the 7-segment display of the numbers
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Assigns the values of the 4 bits of state to m1-m4 35
respectively 11 12 Assigns the values of the 7 bits of number to a, b, c, d, e, f, g, dp respectively Assigns the value of 1 to dp Note: Since the LEDs are low-enabled, assigning the value of 1 to dp means that this specific LED is turned off all the time This block is executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, all the bits of state have the value of 0, as a result, the 4 digital displays are inactive. If not, the LSB of state is set or its value is equal to 1. As a result, one of the digital displays is active. This block is also executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, all the bits of number have the value of 1, as a result, all the LEDs in the 7segment display are turned off. If not, number4 is assigned to number thus; the number 4 is displayed to the active digital display.
14-18
20-24
26 E. Instructions
Signifies the end of the module
m1 m3 m2 m4
1. Create a new project and save it to the working directory C:\FPGAprojects\exercise6 and name your current project as exercise6. 2. Create a new Verilog HDL file and save it as exercise6.v. 3. Modify the given sample code above wherein instead of displaying the number 4, the letter F will be displayed. Type in your code on the exercise6.v panel and save. 4. Compile your file and edit the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to include the pin assignments 36
for the four 7-segment LEDs. Copy the new Tcl file to the directory where your current project is saved. 5. Download your program to the M2SK and see what happens. F. Summary In this exercise, you have learned how to output numbers and letters to the digital display of the M2SK.
Exercise 7 7-Segment LED Display (II)

A. Objectives This exercise aims to design a Verilog program that outputs the numbers letters bESt to the seven segment display in the Max II Starter Kit (M2SK). B. Questions
Is the common pin in the 7-segment LED display low-enabled or highenabled? What does it mean?
C. Sample Code
// This code outputs the numbers 1 to 4 in the 4 digital displays of the M2SK. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module exercise7 (clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp); input clk, rst; reg [3:0] state; reg [23:0] counter; reg [6:0] number; output m1, m2, m3, m4, a, b, c, d, e, f, g, dp; parameter parameter parameter parameter number1 number2 number3 number4 = = = = 7'b1001111; 7'b0010010; 7'b0000110; 7'b1001100;
assign {m1, m2, m3, m4} = state; assign {a, b, c, d, e, f, g} = number; assign dp = 1;
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
always @ (posedge clk) if (rst == 0) counter <= 0; else if (counter == 100000) counter <= 0; else counter <= counter+1; always @ (posedge clk) if (rst == 0) state <= 4'b0000; else if (counter == 100000) case (state) 4b0000: state <= 4'b0001; 4b0001: state <= 4'b0010; 4b0010: state <= 4'b0100; 4b0100: state <= 4'b1000; 4b1000: state <= 4'b0000; default: state <= 4'b0000; endcase always @ (posedge clk) if (rst == 0) number <= 7'h7f; else case (state) 4b0001: number <= number1; 4b0010: number <= number2; 4b0100: number <= number3; 4b1000: number <= number4; default: number <= 7'h7f; endcase endmodule
D. Code Explanations Line No. Explanations 1 Words in blue are reserved words. Any Verilog program starts with the reserved word module <module_name>. In this example, the module is named exercise7. After declaring the module name, the port declaration follows. For this module, it has the following ports: clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp Note: m1 m4 (four digital displays) a, b, c, d, e, f, g, dp (each LED in the 7segment display including the dot point) 38
3 4-6 7 9-12
Input ports Output ports data type (state: 4 bits, counter: 24 bits, number: 7 bits) Output ports Assigns the 7-segment display of the numbers 1-4
14 15 16
Assigns the values of the 4 bits of state to m1-m4 respectively Assigns the values of the 7 bits of number to a, b, c, d, e, f, g, dp respectively Assigns the value of 1 to dp Note: Since the LEDs are low-enabled, assigning the value of 1 to dp means that this specific LED is turned off all the time This block is executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, counter is set to 0, if not, the value of counter is checked. If the condition is satisfied that is, if counter is equal to 100000, then, counter is set to 0. If not, counter is incremented. This block is also executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, all the bits of state have the value of 0, as a result, the 4 digital displays are inactive. If not, the value of counter is checked. If the condition is satisfied that is, if counter is equal to 100000, a case statement follows wherein the 4-bit value of state is checked and a new value of state is assigned. This controls what digital display is enabled that is, if state [0] is set to 1, the digital display assigned to m4 is active. If state [1] is set to 1, the digital display assigned to m3 is active. If state [2] is set to 1, the digital display assigned to m2 is active. If state [3] is set to 1, the digital display assigned to m1 is active.
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26-37
39
39-49
This block is also executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, all the bits of number have the value of 1, as a result, all the LEDs in the 7segment display are turned off. If not, a case statement follows wherein the 4-bit value of state is checked and the corresponding 7-segment display of a number is assigned that is, for the m4 display, the number 1 is assigned. For m3, the number 2 is assigned, for m2, the number 3 and for m1, the number 4 is assigned.
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m4 m3 m2 Signifies the end of the module
m1
E. Instructions 1. Create a new project and save it to the working directory C:\FPGAprojects\exercise7 and name your current project as exercise7. 2. Create a new Verilog HDL file and save it as exercise7.v. 3. Modify the given sample code above wherein each digital display should output one letter as shown in the figure below instead of the numbers 1 to 4. Type in your code on the exercise7.v panel and save.
4. Compile your file and copy the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to the directory where your current project is saved. 5. Download your program to the M2SK and see what happens. F. Summary In this exercise, you have learned how to access and control the four 40
digital displays and its corresponding 7-segment LEDs. You also have learned how to output numbers and letters to the digital display of the M2SK.
Exercise 8 Counter
A. Objectives This exercise aims to design a Verilog program that outputs 0000 to 9999 to the seven segment display in the Max II Starter Kit (M2SK) with a 0.1 second interval. B. Questions
How are you going to set the counting interval at 0.1 seconds?
C. Sample Code
// This code outputs the counting of numbers from 0 to 9 at a 1 second interval in the digital display of the M2SK. 1 2 3 4 5 6 7 8 9 10 module exercise8 (clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp); input clk, rst; output m1, m2, m3, m4; output a, b, c, d, e, f, g, dp; reg [23:0] counter; reg [19:0] state; reg [7:0] number;
41
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
assign {m1, m2, m3, m4} = state; assign {a, b, c, d, e, f, g} = number; assign dp = 1; parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter number1 number2 number3 number4 number5 number6 number7 number8 number9 number0 = = = = = = = = = = 7'b1001111; 7'b0010010; 7'b0000110; 7'b1001100; 7'b0100100; 7'b0100000; 7'b0001111; 7'b0000000; 7'b0000100; 7'b0000001;
always @ (posedge clk) if (rst == 0) counter <= 0; else if (counter == 16000000) counter <= 0; else counter <= counter+1; always @ (posedge clk) if (rst == 0) state <= 4'b0000; else state <= 4'b0001; always @ (posedge clk) if (rst == 0) number <= number0; else if (counter == 16000000) case (number) number0: number <= number1; number1: number <= number2; number2: number <= number3; number3: number <= number4; number4: number <= number5; number5: number <= number6; number6: number <= number7; number7: number <= number8; number8: number <= number9; number9: number <= number0; default: number <= number0; endcase endmodule
D. Code Explanations Line No. Explanations 1 Words in blue are reserved words. Any Verilog 42
program starts with the reserved word module <module_name>. In this example, the module is named exercise8. After declaring the module name, the port declaration follows. For this module, it has the following ports: clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp Note: m1 m4 (four digital displays) a, b, c, d, e, f, g, dp (each LED in the 7segment display including the dot point) 3 4-5 7-9 11 12 13 Input ports Output ports Output ports data type (state: 4 bits, counter: 24 bits, number: 7 bits) Assigns the values of the 4 bits of state to m1-m4 respectively Assigns the values of the 7 bits of number to a, b, c, d, e, f, g, dp respectively Assigns the value of 1 to dp Note: Since the LEDs are low-enabled, assigning the value of 1 to dp means that this specific LED is turned off all the time Assigns the 7-segment display of the numbers 0-9 This block is executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, counter is set to 0, if not, the value of counter is checked. If the condition is satisfied that is, if counter is equal to 16000000, then, counter is set to 0. If not, counter is incremented. Note: Why 16000000? This is because the frequency of the oscillator is 16MHz that is, 16000000 cycles per second. If each transition should only take 1 s then, the counter should be set at 16000000.
15-24 26-32
43
34-38
This block is also executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, all the bits of state have the value of 0, as a result, the 4 digital displays are inactive. If not, the value of counter is checked. If the condition is satisfied that is, if counter is equal to 16000000, a new value of state is set, which enables one of the 7-segment LEDs to be active specifically, the m4 digital display.
40-56
m4 m3 m2 m1 This block is also executed for every positive edge of the clock. First, it checks whether rst is 0 or sw1 is pushed down. If yes, the number 0 is displayed. If not, the value of counter is checked. If the condition is satisfied that is, if counter is equal to 16000000, a case statement follows wherein the value of number is checked and a new value of number is assigned, which is displayed in the active 7-segment LED. Signifies the end of the module
58
C. Instructions 1. Create a new project and save it to the working directory C:\FPGAprojects\exercise8 and name your current project as exercise8. 2. Create a new Verilog HDL file and save it as exercise8.v. 3. Modify the sample code given above wherein the 4 digital displays will output the counting of numbers from 0000 to 9999. The 7-segment LED display of the different numbers is shown in the figure below. Type in your code on the exercise8.v panel and save.
44
4. Compile your file and copy the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to the directory where your current project is saved. 5. Download your program to the M2SK and see what happens. D. Summary In this exercise, you have learned how to control the output of the four digital displays. In the succeeding exercises, you will be asked to control the output with the use of push buttons and a switch.
Exercise 9 Counter with Controls

A. Objectives This exercise aims to design a Verilog program that outputs 0000 to 9999 to the seven segment display in the Max II Starter Kit (M2SK) with a 0.1 second interval when the DIP1 switch (pin 22 of the EPM1270T144C5) is off. When the DIP1 switch is on, the output number will increment by 1 if SW3 (pin 27 of the EPM1270T144C5) is pressed and it will decrement by 1 if SW4 (pin 28 of the EPM1270T144C5) is pressed. B. Questions

How can you tell if the DIP1 switch on the M2SK is on or not? Where is the SW3 and SW4 of the M2SK located? What pins in the Max II Starter Kit are assigned to SW3 and SW4?
C. Instructions 1. Create a new project and save it to the working directory C:\FPGAprojects\exercise9 and name your current project as exercise9. 45
2. Create a new Verilog HDL file and save it as exercise9.v. 3. Modify your exercise8.v code so that when the DIP1 switch is off, the result is similar to that in the previous exercise. However, if the DIP1 switch is on, the output in the digital display will increment by 1 if SW3 is pressed and it will decrement by 1 if SW4 is pressed. Type in your code on the exercise9.v panel and save. 4. Compile your file and edit the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to include the pin assignments for SW3 and SW4. Copy the new Tcl file to the directory where your current project is saved. 5. Download your program to the M2SK.
D. Test your program After you have downloaded the program, you will be able to see the start of the counting from 0000 to 9999 on the digital display. This is because at default, the DIP1 switch is off. Turning the switch on will stop the counting. Press SW3 and the count should increment. Press SW4 and the count should decrement. SW3 SW4 E. Summary In this exercise, you have learned how to control the output of the four digital displays with the use of push buttons and a switch.
46
Exercise 10 PC to MAX II via RS232

A. Objectives This exercise aims to design a Verilog program that communicates to a personal computer (PC) via the RS232 protocol. You have the option to make a PC program or use the HyperTerminal to send data to the Max II kit. The Verilog program should display data or message serially using the four seven (7) segment display of the Max II Starter Kit (M2SK). Implement different baud rates selectable using the DIP switches. B. Questions

What is the ASCII code? What are the hexadecimal values of 1? 2? 3? 4? 5? b? E? S? T? What pin in the Max II Starter Kit is assigned to receive data in the UART connector?
C. Instructions 1. Create a new project and save it to the working directory 47

C:\FPGAprojects\exercise10 exercise10.
and
name
your
current
project
as
2. Create a new Verilog HDL file and save it as exercise10.v. 3. Type in your code on the exercise10.v panel and save. (refer to the sample code given in the Appendix B) 4. Compile your file and edit the Tcl source file (pin_assign.tcl) that you have written in the previous exercise to include the pin assignments for the UART connector. Copy the new Tcl file to the directory where your current project is saved. 5. Download your program to the M2SK.
Hyperterminal Connection 6. Go to Start > All Programs > Accessories > Communication > HyperTerminal
7. Type in your name. Click OK.
48
8. Select COM1 connection. Click OK.
9. Type in the COM1 properties. Choose None for Flow Control. Click OK.
10. Start typing in your keyboard and see the output in the digital display of the M2SK.
49
D. Test Your Program Once you pressed any character in your keyboard, you will be able to see the hexadecimal value of the ASCII character that you have typed in the two rightmost digital displays of the M2SK. Once you entered in another character or a new character, the previous value would be shifted to the left and it will be shown in the two leftmost digital displays of the M2SK while the new hexadecimal value will be shown in the two rightmost digital displays of the M2SK. E. Summary In this exercise, you have learned how to display data in the four 7segment displays of the Max II Starter Kit via RS232.
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BUGHAW ELECTRONIC SOLUTIONS AND TECHNOLOGIES, INC.

CPLD/FPGA Laboratory Manual

Exercise 2 Controlled LED . . . . . . . . . . . . . . 25 Exercise 3 Blinking LEDs . . . . . . . . . . . . . . . 26

Exercise 7 7-segment LED Display (II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Exercise 8 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Appendix A .......................................................... . . . 52 Appendix B .......................................................... . . . 60

Minimum System Requirements

2008 BEST, Inc. All Rights Reserved

parallel and serial ports LAN card

GFEC Max II Starter Kit

2. Connect the AC adapter to the DC input connector on the emulation board.

Notations and Conventions

2008 BEST, Inc. All Rights Reserved

Altera Quartus II 7.0 Web Edition Installation

2. Click Next to continue installation

5. After entering the needed information, click Next.

8. Select the Complete option and click Next.

9. This shows the complete setting of the installation. Click Next. 10

Fill in the needed information and click Sign in.

Navigate to the Desktop and double-click on the Quartus icon.

In the main menu, click on Tools > License Set up.

Exercise 1 Introduction to the Max II Starter Kit

7. From the list of devices, choose EPM1270T144C5. Click Next.

22. Select exercise1.pof and check Program/Configure. Click Start.

Exercise 2 Controlled LED

Exercise 3 Blinking LEDs

Signifies the end of the module

Exercise 4 LED Pattern

Exercise 5 LED Operation Using a Push Button

Exercise 6 7-Segment LED Display (I)

Assigns the values of the 4 bits of state to m1-m4 35

2008 BEST, Inc. All Rights Reserved

Signifies the end of the module

Exercise 7 7-Segment LED Display (II)

m4 m3 m2 Signifies the end of the module

Exercise 9 Counter with Controls

Exercise 10 PC to MAX II via RS232

C. Instructions 1. Create a new project and save it to the working directory 47

7. Type in your name. Click OK.

8. Select COM1 connection. Click OK.

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