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INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE
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ABSTRACT
To explore integrated solar energy harvesting as a power source for low power systems, an array of energy scavenging photodiodes (SOLAR CELLS) are used to harvest the solar energy with the maximum efficiency. Photodiodes are used to detect the direction of the maximum radiation. They are used to turn the solar cells to that direction to harvest the solar energy. The solar panels automatically turn to the right direction when the intensity changes. The resultant energy is then stored and hence can be utilized for future uses as well. The battery is used instead of the capacitor to store the energy. The project aims at the making the system autonomous and selfreliant as far as the power utilization is concerned. Since the sun is a renewable source of energy and readily available throughout, the kit becomes independent relying completely on the solar energy.
The low power design is useful while supplying power to the wireless sensor nodes whose energy requirement is low. Tests have been conducted in the visible region of light to see the resolution of the photodiodes and the amount of turn to the solar panels as well. The harvesting is situational as well. On sun-obstructed days, not as much energy may be stored but the panels will make use of whatever light energy is present.
ELECTRONICS AND COMMUNICATION,MVJCE
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2. PROJECT OVERVIEW
THE emerging application of wireless sensor networks continues to drive the need for ultra low power system design. Wireless sensors can enable a variety of applications including interactive environments for medicine, environmental monitoring networks, military target tracking, and detection of chemical and biological weapons. In many of these wireless systems, the power source is a bottleneck that limits system lifetime and performance, adds manufacturing cost, and increases system volume and maintenance expenditures. Delivering power to wireless sensor network nodes is a significant System design challenge. Solar energy harvesting has been proposed to extend the lifetime of these networks beyond the limitations which have been previously imposed by batteries. Prior works have successfully demonstrated powering wireless systems through discrete photovoltaic cells together with separate energy storage devices using board level designs. To reduce system cost and volume it is desirable to integrate energy harvesting and storage with data acquisition, data processing, and communication circuits. Recent advances in very low power signal processing architectures for sensors has created the opportunity to use CMOS photodiodes, similar to those used in digital cameras, for solar energy harvesting. Moreover, the increase in interconnect capacitance as CMOS processes scale provides an opportunity to store the harvested energy without requiring battery materials to be integrated on-chip. This paper describes an array of photodiodes, modeled after a passive-pixel imager, integrated together with storage capacitors in a commodity CMOS process. Also described is the potential of this approach to increase the lifetime of wireless sensor nodes. Fig. 1 shows a block diagram of a typical wireless sensor node, which is powered by a combination of energy scavenging and battery technology. The system consists of sensors that can observe the environment, an analog-to-digital converter (ADC) that can quantize the analog signal from the sensors, a digital signal processing (DSP) core that can analyze and encode the quantized data
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and a transceiver (RF) so that the node can transmit and receive information. Light energy is converted to electrical energy through a photodiode and mechanical vibrations are converted to electrical energy by an electromechanical transducer [4]. A multiplexer (mux) is used to switch between energy sources. The systems energy gathering ability will depend on environmental conditions, which can change over time. Hence, the scavenged energy needs to be regulated before being used by these functional blocks. In general, these types of systems work on very low duty cycles, where the sensor node will be in a rest state for the majority of the time. Periodically, the sensor node will wake up, take a snapshot of the environment measured by its sensors, perform its computations, and transmit any data before returning back to the rest state. Each of the functional blocks shown in Fig. 1 has its own power requirement. Previous work has shown that efficient ADCs and DSPs can achieve average power levels in the sub-milliwatt range. However, low power ADCs usually suffer from diminished power supply rejection. Minimizing the voltage ripple on the power supply for the ADC is important for maintaining accuracy. The RF block typically requires significantly more peak power than the other system blocks, and the DSP has the most relaxed supply ripple requirements due to the robustness (large noise margin) of the digital circuitry. For Low duty cycles, the average power for the system can be under 5microwatts.
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3.1 BLOCK DIAGRAM (SIMULATION)
Figure 1.1
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3.2 BLOCK DIAGRAM (IMPLEMENTATION)
Figure 1.2
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3.3 Project Module /requirement

o Hardware Module o Software Module
Hardware Module
Photo Diode ADC0804 Spartan 3/Spartan 3E ULN2003A Stepper motor Solar cells 12v battery
Software Module
1. Getting knowledge in vhdl 2. Tools to be used:
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For, Simulation Synthesis & Implementation Model Sim 6.2c Xilinx ISE 9.1i
Implementation
For FPGA based implementation, the FPGA Details are,
Manufacturer Family FPGA Series
Xilinx Spartan 3/Spartan 3E XC3S1003TQ144/XC3S250EPQ208
Language to be used
VHDL
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4.1 FPGA POWER SUPPLY
Figure 2.1
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4.2 FPGA KIT CIRCUIT
Figure 2.2
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4.3 OVERALL CIRCUIT DIAGRAM
Figure 2.3
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5.1 DC MOTOR FORWARD REVERSE CONTROL
Figure 3.1
Circuit working Description

This circuit is designed to control the motor in the forward and reverse direction. It consists of two relays named as relay1, relay2. The relay ON and OFF is controlled by the pair of switching transistors. A Relay is nothing but electromagnetic switching device which consists of three pins. They are Common, Normally close (NC) and normally open (NO). The common pin of two relay
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is connected to positive and negative terminal of motor through snubber circuit respectively. The relays are connected in the collector terminal of the transistors T2 and T4. When high pulse signal is given to either base of the T1 or T3 transistors, the transistor is conducting and shorts the collector and emitter terminal and zero signals is given to base of the T2 or T4 transistor. So the relay is turned OFF state. When low pulse is given to either base of transistor T1 or T3 transistor, the transistor is turned OFF. Now 12v is given to base of T2 or T4 transistor so the transistor is conducting and relay is turn ON. The NO and NC pins of two relays are interconnected so only one relay can be operated at a time. The series combination of resistor and capacitor is called as snubber circuit. When the relay is turn ON and turn OFF continuously, the back emf may fault the relays. So the back emf is grounded through the snubber circuit. When relay 1 is in the ON state and relay 2 is in the OFF state, the motor is running in the forward direction. When relay 2 is in the ON state and relay 1 is in the OFF state, the motor is running in the reverse direction.
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5.2 Analog-to-Digital Converter (ADC)
ADC0803/0804 CMOS 8-bit A/D converters What Is an ADC? Mixed-Signal Device Analog Input Digital Output
Because the Analog-to-Digital Converter (A/D Converter or ADC) has both analog and digital functions, it is a mixed-signal device. Many of us consider the ADC to be a mysterious device. It can, however, be considered very simply to be the instrument that it is: a device that provides an output that digitally represents the input voltage or current level. Notice I said voltage or current. Most ADCs convert an input voltage to a digital word, but the true definition of an ADC does include the possibility of an input current. An ADC has an analog reference voltage or current against which the analog input is compared. The digital output word tells us what fraction of the reference voltage or current is the input voltage or current. So, basically, the ADC is a divider. The Input/Output transfer function is given by the formula indicated here. If you have seen this formula before, you probably did not see the G term (gain factor). This is because we generally consider this to be unity. However, National Semiconductor has introduced ADCs with other gain factors, so it is important to understand that this factor is present.
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What, Exactly, Does an Analog to-Digital Converter Do?

Here is an example of a 3-bit A/D converter. Because it has 3 bits, there are 23 = 8 possible output codes. The difference between each output code is VREF / 23. Assuming that the output response has no errors, every time you increase the voltage at the input by 1 Volt, the output code will increase by one bit. This means, in this example, that the least significant bit (LSB) represents 1 Volt, which is the smallest increment that this converter can resolve. For this reason, we can say that the resolution of this converter is 1.0V because we can resolve voltages as small as a volt. Resolution may also be stated in bits. Note that if you reduce the reference voltage to 0.8V, the LSB would then represent 100mV, allowing you to measure a smaller range of voltages (0 to 0.8V) with greater accuracy. This is a common way for our customers to get better precision from a converter without buying a more expensive, higher resolution converter. The Resolution of an A/D converter is the number of output bits it has (3 bits, in this example).
Figure 3.2
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FEATURES
Compatible with most processors. Differential inputs. 3-State outputs. Logic levels TTL and MOS compatible Can be used with internal or external clock Analog input range 0 V to VCC Single 5 V supply Guaranteed specification with 1 MHz clock
APPLICATIONS
Transducer-to-processor interface Digital thermometer. Digitally-controlled thermostat. Microprocessor-based monitoring and control systems.
Output = 2n x G x AIN / VREF

n = # of Output Bits (Resolution) G = Gain Factor (usually 1) AIN = Analog Input Voltage (or Current) VREF (IREF) = Reference Voltage (or Current)
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5.3 Field Programmable Gate Array (FPGA)

Prompted by the development of new types of sophisticated field-programmable devices (FPDs), the process of designing digital hardware has changed dramatically over the past few years. Unlike previous generations of technology, in which board-level designs included large numbers of SSI chips containing basic gates, virtually every digital design produced today consists mostly of high-density devices. This applies not only to custom devices like processors and memory, but also for logic circuits such as state machine controllers, counters, registers, and decoders. When such circuits are destined for high-volume systems they have been integrated into high-density gate arrays. However, gate array NRE costs often are too expensive and gate arrays take too long to manufacture to be viable for prototyping or other low-volume scenarios. For these reasons, most prototypes, and also many production designs are now built using FPDs. The most compelling advantages of FPDs are instant manufacturing turnaround, low start-up costs, low financial risk and (since programming is done by the end user) ease of design changes. The market for FPDs has grown dramatically over the past decade to the point where there is now a wide assortment of devices to choose from. A designer today faces a daunting task to research the different types of chips, understand what they can best be used for, choose a particular manufacturerss product, learn the intricacies of vendor -specific software and then design the hardware. Confusion for designers is exacerbated by not only the sheer number of FPDs available, but also by the complexity of the more sophisticated devices. The purpose of this paper is to provide an overview of the architecture of the various types of FPDs. The emphasis is on devices with relatively high logic capacity; all of the most important commercial products are discussed. Before proceeding, we provide definitions of the terminology in this field. This is necessary because the technical jargon has become somewhat inconsistent over the past few years as companies attempted to compare and contrast their products in literature.
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EVOLUTION OF PROGRAMMABLE LOGIC DEVICES

The first type of user-programmable chip that could implement logic circuits was the Programmable Read-Only Memory (PROM), in which address lines can be used as logic circuit inputs and data lines as outputs. Logic functions, however, rarely require more than a few product terms, and a PROM contains a full decoder for its address inputs. PROMS are thus an inefficient architecture or realizing logic circuits, and so are rarely used in practice for that purpose. The first device developed later specifically for implementing logic circuits was the Field-Programmable Logic Array (FPLA), or simply PLA for short. A PLA consists of two levels of logic gates: a programmable wired AND-plane followed by a programmable wired OR-plane. A PLA is structured so that any of its inputs (or their complements) can be ANDed together in the AND -plane; each AND-plane output can thus correspond to any product term of the inputs. Similarly, each ORplane output can be configured to produce the logical sum of any of the AND-plane outputs. With this structure, PLAs are well-suited for implementing logic functions in sum-of-products form. They are also quite versatile, since both the AND terms and OR terms can have many inputs (this feature is often referred to as wide AND and OR gates).When PLAs were introduced in the early 1970s, by Philips, their main drawbacks were that they were expensive to manufacture and offered somewhat poor speed-performance. Both disadvantages were due to the two levels of configurable logic, because programmable logic planes were difficult to manufacture and introduced significant propagation delays. To overcome these weaknesses, Programmable Array Logic (PAL) devices were developed. As Figure 1 illustrates, PALs feature only a single level of programmability, consisting of a programmable wired ANDplane that feeds fixed OR-gates. To compensate for lack of generality incurred because the OROutputs plane is fixed, several variants of PALs are produced, with different numbers of inputs and outputs, and various sizes of OR-gates. PALs usually contain flip-flops connected to the OR-gate outputs so that sequential circuits can be realized. PAL devices are important because when introduced they had a profound effect on digital hardware design, and also they are the basis for some of the newer, more sophisticated architectures that will be described shortly. Variants of the basic PAL architecture are featured in several other products known by different acronyms. All small PLDs, including PLAs, PALs, and PAL-like devices are grouped into a single category
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called Simple PLDs (SPLDs), whose most important characteristics are low cost and very high pin-to-pin speed-performance. As technology has advanced, it has become possible to produce devices with higher capacity than SPLDs. The difficulty with increasing capacity of a strict SPLD architecture is that the structure f the programmable logic-planes grow too quickly in size as the number of inputs is increased. The only feasible way to provide large capacity devices based on SPLD architectures is then to integrate multiple SPLDs onto a single chip and provide interconnect to programmably connect the SPLD blocks together. Many commercial FPD products exist on the market today with this basic structure, and are collectively referred to as Complex PLDs (CPLDs). CPLDs were pioneered by Altera, first in their family of chips called Classic EPLDs, and then in three additional series, called MAX 5000, MAX 7000 and MAX 9000. Because of a rapidly growing market for large FPDs, other manufacturers developed devices in the CPLD category and there are now many choices available. All of the most important commercial products will be described in Section 2. CPLDs provide logic capacity up to the equivalent of about 50 typical SPLD devices, but it is somewhat difficult to extend these architectures to higher densities. To build FPDs with very high logic capacity, a different approach is needed. The highest capacity general purpose logic chips available today are the traditional gate arrays sometimes referred to as Mask-Programmable Gate Arrays (MPGAs). MPGAs consist of an array of pre-fabricated transistors that can be customized into the users logic circuit by connecting the transistors with custom wires. Customization is performed during chip fabrication by specifying the metal interconnect, and this means that in order for a user to employ an MPGA a large setup cost is involved and manufacturing time is long. Although MPGAs are clearly not FPDs, they are mentioned here because they motivated the design of the user-programmable equivalent: Field- Programmable Gate Arrays (FPGAs). Like MPGAs, FPGAs comprise an array of uncommitted circuit elements, called logic blocks, and interconnect resources, but FPGA configuration is performed through programming by the end user. An illustration of a typical FPGA architecture appears in Figure 2. As the only type of FPD that supports very high logic capacity, FPGAs have been responsible for a major shift in the way digital circuits are designed.
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FPGA SPARTAN 3
Figure 3.3
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5.4 SPARTAN 3-E
Manufacturer: Order Code: Manufacturer Part No:
XILINX 1605856 XC3S100E-4TQG144C
Figure 3.4
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DESCRIPTION
FPGA,SPARTAN-3E,2150CELLS, 144TQFP No. of Macrocells:2160 Operating Temperature Range:0C to +85C No. of Pins:144 Case Style: TQFP Max Operating Temperature:85C Min Temperature Operating:0C Base Number:3 Logic IC Base Number:3S100 Logic IC Family: CMOS Logic IC Function: FPGA Max Supply Voltage:1.26V Min Supply Voltage:1.14V Termination Type: SMD Frequency:572MHz I/O Interface Standard: LVCMOS, LVTTL, HSTL, SSTL, True LVDS, RSDS, mini-L No. of I/O Lines:108 Programmable Logic Type: FPGA
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Figure 3.5 shows the Spartan-3E Sample Pack board block diagram, which includes the following components and features: 100,000-gate Xilinx Spartan-3E XC3S100E FPGA in a 144-Thin Quad Flat Pack package (XC3S100E-TQ144)
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o 2,160 logic cell equivalents o Four 18K-bit block RAMs (72K bits) o Four 18x18 pipelined hardware multipliers o Two Digital Clock Managers (DCMs) 32Mbit Intel StrataFlash A 40-pin expansion connection port to gain access to the Spartan-3E FPGA Four 6-pin expansion connector ports to extend and enhance the Spartan-3E Sample Pack o Compatible with Digilent, Inc. peripheral boards o http://www.digilentinc.com/products/Peripheral.cfm 7 Light Emitting Diodes (LEDs) 50MHz Crystal Oscillator Clock Source Power Regulators
Clock Source
The Spartan-3E Sample Pack board has a Linear Technology LTC6905 Crystal Oscillator set to 50MHz. Use the 50MHz clock frequency as is or derive other frequencies using the FPGAs Digital Clock Managers (DCMs).
Power Switch
The Spartan-3E Sample Pack board has a push button power switch. Pressing the power switch will alternately power on or power off the board.
Multi-Use Switch
A multi-use push button switch is used in the default board designs to enable MultiBoot Depressing the switch generates a Logic High on the associated FPGA pin.
LEDs
The Spartan-3E Sample Pack board has 7 individual surface-mount LEDs located to the left of the FPGA. The LEDs are labeled LD7 through LD1 and are laid out in an H pattern to mimic a Die used in a Dice game.
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5.5 ULN 2003A

DESCRIPTION
The ULN2001A, ULN2002A, ULN2003 and ULN2004A are high voltage, high current darlington arrays each containing seven open collector darlington pairs with common emitters. Each channel rated at 500mA and can withstand peak currents of 600mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. The four versions interface to all common logic families ULN2001A General Purpose, DTL, TTL, PMOS, CMOS ULN2002A 14-25V PMOS ULN2003A 5V TTL, CMOS ULN2004A 615V CMOS, PMOS These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal print heads and high power buffers. The ULN2001A/2002A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper lead frame to reduce thermal resistance. They are available also in small outline package (SO-16) as ULN2001D/2002D/2003D/2004D.
PIN DIAGRAM
Figure 3.6
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Table 1.1
Figure 3.7
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DESCRIPTION
SEVEN DARLINGTONS PER PACKAGE OUTPUT CURRENT 500mA PER DRIVER (600mA PEAK) OUTPUT VOLTAGE 50V INTEGRATED SUPPRESSION DIODES FOR INDUCTIVE LOADS OUTPUTS CAN BE PARALLELED TTL/CMOS/PMOS/DTL COMPATIBLE . FOR HIGHER CURRENT
INPUT PINNED OPPOSITE OUTPUTS TO SIMPLIFY LAYOUT
ULN2001A General Purpose, DTL, TTL, PMOS, CMOS These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal print heads and high power buffers. The ULN2001A are supplied in 16 pin plastic DIP packages with a copper lead frame to reduce thermal resistance.
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5.6 LDR
Light dependent resistor is a resistor whose resistance decreases with increasing incident light intensity. It can also be referred to as a photoconductor. A light dependent resistor is a small, round semiconductor. Light dependent resistors are used to re-charge a light during different changes in the light, or they are made to turn a light on during certain changes in lights. One of the most common uses for light dependent resistors is in traffic lights. The light dependent resistor controls a built in heater inside the traffic light, and causes it to recharge over night so that the light never dies. Other common places to find light dependent resistors are in: infrared detectors, clocks and security alarms.
Identification
A light dependent resistor is shaped like a quarter. They are small, and can be nearly any size. Other names for light dependent resistors are: photoconductors, photo resistor, or a CdS cell. There are black lines on one side of the light dependent resistor. The overall color of a light dependent resistor is gold. Usually other electrical components are attached to the light dependent resistor by metal tubes soldered to the sides of the light dependent resistor.
Function
The main purpose of a light dependent resistor is to change the brightness of a light in different weather conditions. This can easily be explained with the use of a watch. Some watches start to glow in the dark so that it is possible to see the time without having to press any buttons. It is the light dependent resistor that allows the watch to know when it has gotten dark, and change the emissions level of the light at that time. Traffic lights use this principle as well but their lights have to be brighter in the day time.
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Considerations
Light dependent resistors have become very useful to the world. Without them lights would have to be on all the time, or they would have to be manually adjusted. A light dependent resistor saves money and time for any creation that needs a change in light. Another feature of the light dependent resistor is that it can be programmed to turn on with changes in movements. This is an extremely useful feature that many security systems employ. Security would be harder without light dependent resistors.
Expert Insight
It is possible to build a light dependent resistor into an existing light circuit. There are many electrical plans that outline how to install one. Usually the sign for a light dependent resistor on these plans is marked by a rectangle with two arrows pointing down to it. This shows the placement of the light dependent resistor in the circuit so that it will work properly. Usually only an electrician can build new circuits, however.
Benefits
There are many great benefits to light dependent resistors. They allow less power to be used in many different kinds of lights. They help lights last much longer. They can be trigged by several different kinds of triggers, which is very useful for motion lights and security systems. They are also very useful in watches and cars so that the lights can turn on automatically when it becomes dark. There are a lot of things that light dependent resistors can do.
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Figure 3.8 LDRs or Light Dependent Resistors are very useful especially in light/dark sensor circuits. Normally the resistance of an LDR is very high, sometimes as high as 1000 000 ohms, but when they are illuminated with light resistance drops dramatically.
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Figure 3.9 This is an example of a light sensor circuit : When the light level is low the resistance of the LDR is high. This prevents current from flowing to the base of the transistors. Consequently the LED does not light.
However, when light shines onto the LDR its resistance falls and current flows into the base of the first transistor and then the second transistor. The LED lights. The preset resistor can be turned up or down to increase or decrease resistance, in this way it can make the circuit more or less sensitive.
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5.7 SOLAR CELLS

SOLAR cells or photovoltaic cells are in fact large area semiconductor diodes that convert sunlight into electrical current to produce usable power.
Figure 3.10
where
Iph is photo current in ampere, Is is reverse saturation current in
ampere(approximately 10-8/square meter), V is diode voltage in volt, and m is diode ideality factor (m = 1 for ideal diode). Thermal voltage can be calculated with the following equation :
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where VT is thermal voltage; its value about 25mV at 25C k is Boltzmanns constant. The value of Boltzmann's constant is approximately 1.3807 x 10-23 joules per kelvin (J K-1). T is temperature in kelvin and q is charge of electron which value is 1.6 x 10-19 coulombs.
Table 1.2
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6. SOFTWARE LANGUAGE: VHDL
HISTORY
VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details. The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest area, lowest power consumption, highest clock speed, or other requirements. VHDL borrows heavily from the Ada programming language in both concepts (for example, the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly typed and is not case sensitive. There are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor, in order to directly represent operations which are common in hardware. VHDL also allows arrays to be indexed in either direction (ascending or descending) because both conventions are used in hardware, whereas Ada (like most programming languages) provides ascending indexing only. The reason for the similarity between the two languages is that the Department of Defense required as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada.
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The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string. A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector. The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc. Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules. In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions. Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions. In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should
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improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions. In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was approved by REVCOM in September 2008.
DESIGN
VHDL is a fairly general-purpose language, and it doesn't require a simulator on which to run the code. There are many VHDL compilers, which build executable binaries. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements. VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as Xilinx ISE or Altera Quartus) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software (such as ModelSim) which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be
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defined correctly. For example, for clock input, a loop process or an iterative statement is required. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behavior, working together at the same time). VHDL is a Dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip. In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations. A simple AND gate in VHDL would look something like this: -- (this is a VHDL comment) -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all; -- this is the entity entity ANDGATE is port (
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IN1 : in std_logic; IN2 : in std_logic; OUT1: out std_logic); end ANDGATE; architecture RTL of ANDGATE is begin OUT1 <= IN1 and IN2; end RTL; While the example above may seem very verbose to HDL beginners, one should keep in mind that many parts are either optional or need to be written only once. And generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the std_logic type might at first seem to be an overkill. One could easily use the built-in bit type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL. In the examples that follow, you will see that VHDL code can be written in a very compact form. However, the experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability. Another advantage to the verbose coding style is the smaller amount of resources used when programming to a Programmable Logic Device such as a CPLD[citation needed].
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Synthesizable constructs and VHDL templates

VHDL is frequently used for two different goals: simulation of electronic designs and synthesis of such designs. Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC. Many FPGA vendors have free (or inexpensive) tools to synthesize VHDL for use with their chips, where ASIC tools are often very expensive. Not all constructs in VHDL are suitable for synthesis. For example, most constructs that explicitly deal with timing such as wait for 10 ns; are not synthesizable despite being valid for simulation. While different synthesis tools have different capabilities, there exists a common synthesizable subset of VHDL that defines what language constructs and idioms map into common hardware for many synthesis tools. IEEE 1076.6 defines a subset of the language that is considered the official synthesis subset. It is generally considered a "best practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal for non-standard constructs.
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7.1 SOFTWARE PERSPECTIVE: SIMULATION
7.1.1 ADAPTIVE ALGOL

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.isehs_package.all; entity adaptive_algol is port ( clk : reset start c1 c2 c3 c4 error done wt1 wt2 wt3 wt4 ); end; architecture beh of adaptive_algol is signal s1,s2,s3,s4:integer ; signal cnt:integer:=0; constant no_samples:integer:=4; constant mu:integer:=2; begin
in std_logic; : in std_logic; : in std_logic; : in integer ; : in integer ; : in integer ; : in integer ; : : : : : : in integer ; out std_logic; out integer ; out integer ; out integer ; out integer
process(clk,reset) begin if reset='1' then

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s1<=0; s2<=0; s3<=0; s4<=0; wt1<=conv_integer(r2b(0.25845585871497279,8)); wt2<=conv_integer(r2b(0.47861860958757552,8)); wt3<=conv_integer(r2b(0.47861860958757552,8)); wt4<=conv_integer(r2b(0.25845585871497279,8)); cnt<=0; done<='1'; elsif clk'event and clk='1' then if cnt<no_samples-1 then s1<=s1 + (c1 * error); s2<=s2+ (c2 * error); s3<=s3+ (c3 * error); s4<=s4+ (c4 * error); cnt<=cnt+1; else wt1<=s1 * mu; wt2<=s2 * mu; wt3<=s3 * mu; wt4<=s4 * mu; cnt<=0; s1<=0; s2<=0; s3<=0; s4<=0; done<='1'; end if; end if; end process; end;
7.1.2 ADC
library ieee; use ieee.std_logic_1164.all; use work.isehs_package.all; entity adc is
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port
( );
adc_in : adc_out
in real; : out std_logic_vector(7 downto 0)
end; architecture rtl of adc is begin adc_out end; <= r2b(adc_in,8);
7.1.3 BATTERY
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.isehs_package.all;
entity battery is port(
clk reset voltage_out
: : :
in std_logic; in std_logic; out real range -1.0 to +1.0
);
end; architecture beh of battery is component pn generic( port (
seed:std_logic_vector(7 downto 0):="11100001"); clk : in std_logic; reset : in std_logic; start :in std_logic; pn_out: out std_logic_vector(7 downto 0)
); end component; signal start:std_logic:='1'; signal noise:std_logic_vector(7 downto 0); signal vge:real:=1.0;
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begin
dut_noise:pn generic map("11100001") port map( clk=>clk,reset=>reset,start=>start,pn_out=>noise); voltage_out<=vge * b2r(noise);
end;
7.1.4 FILTER
-- -------------------------------------------------------------
--- Discrete-Time FIR Filter (real) -- -------------------------------- Filter Structure : Direct-Form FIR -- Filter Length : 4 -- Stable : Yes -- Linear Phase : Yes (Type 2) --Fs=50 M --Fpass=3 M --Fstop=4M -- ------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_signed.all;
use work.isehs_package.all; ENTITY filter IS PORT( clk clk_enable reset filter_in
: IN std_logic; : IN std_logic; : IN std_logic; : IN std_logic_vector(7 downto 0);
coeff1 : std_logic_vector(7 downto 0) := r2b(0.25845585871497279,8); coeff2 : std_logic_vector(7 downto 0) := r2b(0.047861860958757552 ,8); coeff3 : std_logic_vector(7 downto 0) := r2b(0.047861860958757552 ,8);
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coeff4 : std_logic_vector(7 downto 0) := r2b(0.25845585871497279,8); c3,c1,c2,c4:out std_logic_vector(7 downto 0); done : out std_logic; filter_out : OUT std_logic_vector(7 downto 0) ); END; -----------------------------------------------------------------Module Architecture: fir4 ---------------------------------------------------------------ARCHITECTURE rtl OF filter IS component mult port( clk:in std_logic; A : in std_logic_vector(7 downto 0); B : in std_logic_vector(7 downto 0); Y : out std_logic_vector(15 downto 0) ); end component; component sum port( clk:in std_logic; A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0); Y : out std_logic_vector(15 downto 0) ); end component; -- Local Functions -- Type Definitions TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF std_logic_vector(7 downto 0); -- Constants -- CONSTANT coeff1 r2b(0.25845585871497279,8); -- CONSTANT coeff2 r2b(0.047861860958757552 ,8); -- CONSTANT coeff3 r2b(0.047861860958757552 ,8); -- CONSTANT coeff4 r2b(0.25845585871497279,8);
: std_logic_vector(7 downto 0) := : std_logic_vector(7 downto 0) := : std_logic_vector(7 downto 0) := : std_logic_vector(7 downto 0) :=
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-- Signals SIGNAL delay_pipeline : delay_pipeline_type(0 TO 3) := ("00000000","00000000","00000000","00000000"); SIGNAL product4 SIGNAL product3 SIGNAL product2 SIGNAL product1 SIGNAL sum1 SIGNAL sum2 SIGNAL sum3 SIGNAL output_register : std_logic_vector(15 downto 0):=(others=>'0'); : std_logic_vector(15 downto 0):=(others=>'0'); : std_logic_vector(15 downto 0):=(others=>'0'); : std_logic_vector(15 downto 0):=(others=>'0'); : std_logic_vector(15 downto 0):=(others=>'0'); : std_logic_vector(15 downto 0):=(others=>'0'); : std_logic_vector(15 downto 0):=(others=>'0'); : std_logic_vector(15 downto 0):=(others=>'0');
signal fout_msb,fout_lsb:std_logic_vector(7 downto 0);
BEGIN
PROCESS (clk, reset) BEGIN IF reset = '1' THEN delay_pipeline(0 TO 3) <= (others=>(OTHERS => '0')); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0) <= filter_in; delay_pipeline(1 TO 3) <= delay_pipeline(0 TO 2); c1<=coeff1; c2<=coeff2; c3<=coeff3; c4<=coeff4; END IF; END IF; END PROCESS; -------------------------------------------------------------------m1:mult port map(clk,delay_pipeline(3),coeff4,product4); m2:mult port map(clk,delay_pipeline(2),coeff3,product3); m3:mult port map(clk,delay_pipeline(1),coeff2,product2);
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m4:mult port map(clk,delay_pipeline(0), coeff1,product1); --------------------------------------------------------------------s1:sum port map(clk,product1(15 downto 0),product2(15 downto 0),sum1); s2:sum port map(clk,sum1 ,product3(15 downto 0),sum2); s3:sum port map(clk,sum2,product4(15 downto 0),sum3); ---------------------------------------------------------------------
PROCESS (clk, reset) BEGIN IF reset = '1' THEN output_register <= (others=>'0'); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN output_register <= sum3; done<='0'; END IF; END IF; END PROCESS;
filter_out <= output_register(14 downto 8) & '0';
END rtl;
7.1.5 MULTIPLEXER
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all;
entity mult is port( clk:in std_logic; A : in std_logic_vector(7 downto 0); B : in std_logic_vector(7 downto 0); Y : out std_logic_vector(15 downto 0)) ;
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end; architecture beh of mult is signal beh_y:std_logic_Vector(15 downto 0); begin process(clk) begin if clk'event and clk='1' then y<=a * b; end if; end process; end;
7.1.6 NCO
library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all;
--library exemplar; use work.exemplar_1164.all;
entity nco is port (i,q :OUT real range -1.000000 to 1.000000; K_IF_FREQ_RX :real ; sclk,reset: in std_logic); end;
--library exemplar; use work.exemplar_1164.all ; LIBRARY IEEE ; USE IEEE.MATH_REAL.ALL ; architecture nco_beh of nco is
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function vec2real(a:std_logic_vector) return real is variable x,y: real range 0.0 to 1048576.0; begin x:= 0.0 ; for i in 0 to a'length-1 loop if a(i) ='0' then y:=0.0; else y:=1.0; end if; x:= x + (y * (2.0 ** i)); end loop; return(x); end vec2real;
--constant K_IF_FREQ_RX : real :=2000000.0; ---62500 constant system_clock : real := 50000000.0; signal K_freq_tuning_word_RX : integer;-- := integer( (K_IF_FREQ_RX/system_clock)* 2.0**32 );
signal inc_reg : std_logic_vector(31 downto 0):=(others=>'0'); signal phase_reg ,p_offset : std_logic_vector(31 downto 0); signal phase_acc,Phase_out : std_logic_vector(32 downto 0); signal inc_reg32 : std_logic_vector(31 downto 0):=(others=>'0'); signal phase_acc_msb : std_logic_vector(19 downto 0); signal phase_ri : real:=0.0; signal q1,i1:real range -1.000000 to 1.000000;
begin
K_freq_tuning_word_RX <=integer((K_IF_FREQ_RX/system_clock)* 2.0**32 ); inc_reg <= (Int2evec(K_freq_tuning_word_RX ,32)); inc_reg32 <= inc_reg; process(sclk,reset) variable perr : std_logic_vector(31 downto 0);
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begin if reset= '1' then phase_acc <= (others =>'0'); phase_reg <= (others =>'0'); phase_out <= (others =>'0'); p_offset <= (others =>'0'); elsif sclk'event and sclk='1' then phase_acc <= (phase_acc + inc_reg32); phase_out <= phase_acc + p_offset; end if; end process;
phase_acc_msb <= (phase_out(31 downto 12)); -- 20 bit phase_ri <= vec2real(phase_acc_msb); q <= (-1.0 * sin((phase_ri / 1048576.0 )*2.0*3.14)); i <= (cos((phase_ri / 1048576.0 )*2.0*3.14)); --end; q<=r2b(q1,8); i<=r2b(i1,8);
7.1.7 OPTICAL SENSOR

entity optical_sensor is port( clk reset voltage_out end;
: : :
);
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architecture beh of optical_sensor is component nco port (i,q :OUT real range -1.000000 to 1.000000; K_IF_FREQ_RX :real ; sclk,reset: in std_logic); end component;
component pn generic( port (
); end component; signal start:std_logic:='1'; signal noise:std_logic_vector(7 downto 0); signal sine:real range -1.0 to +1.0; begin
dut_nco:nco port map (i=>open,q=>sine,K_IF_FREQ_RX=>f,sclk=>clk,reset=>reset); dut_noise:pn generic map("11100001") port map( clk=>clk,reset=>reset,start=>start,pn_out=>noise); voltage_out<=sine * b2r(noise);
end;
7.1.8 POWER REGULATOR

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use work.isehs_package.all;
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entity power_regulator is port ( clk : in std_logic; reset : in std_logic; vin : in std_logic_Vector(7 downto 0); vout : out std_logic_Vector(7 downto 0); desired : in std_logic_Vector(7 downto 0) ); end;
architecture rtl of power_regulator is component adaptive_algol port ( clk : reset start c1 c2 c3 c4 error done wt1 wt2 wt3 wt4 ); end component; component filter PORT( clk clk_enable reset filter_in
in std_logic; : in std_logic; : in std_logic; : in integer; : in integer; : in integer; : in integer; : : : : : : in integer; out std_logic; out integer; out integer; out integer; out integer
: IN std_logic; : IN std_logic; : IN std_logic; : IN std_logic_vector(7 downto 0);
coeff1 : std_logic_vector(7 downto 0) := r2b(0.25845585871497279,8); coeff2 : std_logic_vector(7 downto 0) := r2b(0.047861860958757552 ,8); coeff3 : std_logic_vector(7 downto 0) := r2b(0.047861860958757552 ,8); coeff4 : std_logic_vector(7 downto 0) := r2b(0.25845585871497279,8); c3,c1,c2,c4:out std_logic_vector(7 downto 0);
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done : out std_logic; filter_out ); END component;
: OUT std_logic_vector(7 downto 0)
signal start,done:std_logic; signal fir_out :std_logic_vector(7 downto 0); signal c1,c2,c3,c4:std_logic_Vector(7 downto 0); signal c1r,c2r,c3r,c4r:integer;--;--std_logic_Vector(7 downto 0); signal c1outr,c2outr,c3outr,c4outr:integer;--; signal c1out,c2out,c3out,c4out:std_logic_Vector(7 downto 0); signal error : integer; begin
dut_filt:filter PORT map( clk => clk, clk_enable => '1', reset => reset, filter_in => vin, coeff1 => coeff2 => coeff3 => coeff4 => c1=>c1out, c2=>c2out, c3=>c3out, c4=>c4out, done filter_out => ); process(clk,reset) begin if reset='1' then vout<=(others=>'0'); elsif clk'event and clk='1' then c1outr<=conv_integer(c1out); c2outr<=conv_integer(c2out); c3outr<=conv_integer(c3out); c4outr<=conv_integer(c4out);
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c1, c2, c3, c4,
=> fir_out
done,
TEAM S^4
error<=conv_integer(fir_out)-conv_integer(desired); vout<=conv_std_logic_Vector( (conv_integer(fir_out)-conv_integer(desired)),8); c1<=conv_std_logic_Vector(c1r,8); c2<=conv_std_logic_Vector(c2r,8); c3<=conv_std_logic_Vector(c3r,8); c4<=conv_std_logic_Vector(c4r,8); end if; end process;
dut_aa:adaptive_algol port map (
clk reset start c1 c2 c3 c4 error done wt1 wt2 wt3 wt4
=> => => => => => => => => => =>c2r, =>c3r, =>c4r
clk, reset, '1', c1outr, c2outr, c3outr, c4outr, error, open, c1r,
);
end;
7.1.9 WIRELESS SYSTEM

entity tb_wireless_system is end;

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architecture tb of tb_wireless_system is component wireless_system port ( clk reset vge_sel source tx rx ); end component;
: : : : :
in std_logic; in std_logic; std_logic_Vector(2 downto 0);---to select the vge in std_logic; out std_logic
signal clk signal reset : signal vge_sel : signal tx signal rx
: std_logic; std_logic; std_logic_Vector(2 downto 0);---to select the vge source : std_logic; : std_logic;
signal dout:std_logic_vector(3 downto 0); signal icnt:integer;
begin
dut_ws:wireless_system port map
clk
, reset vge_sel tx rx , , ,
); process begin clk<='1';wait for 10 ns; clk<='0';wait for 10 ns; end process; process begin reset<='1';wait for 10 ns; reset<='0';wait;
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end process; process begin vge_sel<="001";wait for 25 us; vge_sel<="010";wait for 25 us; vge_sel<="011";wait for 25 us; end process; process(clk,reset) begin if reset='1' then dout<="0000"; icnt<=0; tx<='0'; elsif clk'event and clk='1' then if dout<1110 then if icnt<2 then icnt<=icnt+1; tx<=dout(icnt); else dout<=dout+"1"; icnt<=0; end if; else dout<="0000"; if icnt<2 then icnt<=icnt+1; tx<=dout(icnt); else dout<=dout+"1"; icnt<=0; end if; end if; end if; end process;
end;
7.1.10 VIBRATION SYSTEM

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entity vibration_sensor is port( clk reset voltage_out end;
: : :
);
architecture beh of vibration_sensor is component nco port (i,q :OUT real range -1.000000 to 1.000000; K_IF_FREQ_RX :real ; sclk,reset: in std_logic); end component;
component pn generic( port (
); end component; signal start:std_logic:='1'; signal noise:std_logic_vector(7 downto 0); signal sine:real range -1.0 to +1.0; begin
dut_nco:nco port map (i=>open,q=>sine,K_IF_FREQ_RX=>f,sclk=>clk,reset=>reset); dut_noise:pn generic map("11100001") port map( clk=>clk,reset=>reset,start=>start,pn_out=>noise);
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voltage_out<=sine * b2r(noise);
end;
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7.2 HARDWARE PERSPECTIVE: RTL CODE

7.2.1 ADC
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std .all; entity adc_test is port ( clk
data_out data_in ); end;
: in std_logic; adc_read : inout std_logic; adc_cs : inout std_logic; channel : out std_logic_vector(2 downto 0) := "000"; : out std_logic_vector(7 downto 0) := "00000000"; n : inout integer ; : inout std_logic_vector(7 downto 0) := "00000000"
architecture a2d of adc_test is signal count : std_logic_vector(13 downto 0):="00000000000000"; signal dcount : integer:= 0; signal adc_rx : std_logic_vector(7 downto 0); begin process (clk,adc_read,adc_cs,data_in ) begin
if clk'event and clk = '1' then count <= count+1; if count = "11111111111111" then dcount <= dcount+1;
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case dcount is when 0 => adc_cs <= '0'; channel<= "000"; when 1 => if n = 0 then channel <= "000"; elsif n= 1 then channel <= "001"; elsif n= 2 then channel <= "010"; elsif n= 3 then channel <= "011"; elsif n= 4 then channel <= "100"; elsif n= 5 then channel <= "101"; elsif n= 6 then channel <= "110"; elsif n= 7 then channel <= "111"; elsif n=8 then n<=0; end if; when 2 => adc_cs <= '1'; when 3 => adc_cs <= '0'; when 4 => adc_rx <= data_in; when 5 => data_out <= adc_rx; when 25 => if n<9 then n <= n+1; end if; dcount <= 0; when others => null; end case; end if; end if; end process;
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end ;
7.2.2 LCD DISPLAY

Library ieee; Use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use IEEE.STD_LOGIC_SIGNED.ALL; USE WORK.ASCII_PACKAGE.ALL; USE WORK.FUNCTION_SET.ALL; entity LCD_DISPLAY_MODULE is port( clk LCD_RS, LCD_RW, LCD_E LCD_DataBus
: in std_logic; : out std_logic; : out std_logic_vector(7 downto 0);
: IN std_logic_vector(7 downto 0) ); end LCD_DISPLAY_MODULE ;
architecture behav_lcd of LCD_DISPLAY_MODULE is signal state,ledcount : integer :=0; constant counter : Std_Logic_Vector(3 downto 0):="0000"; signal dis : std_logic_vector (9 downto 0); signal DATA : std_logic_vector (7 downto 0); signal dcount : std_logic_vector(10 downto 0):="00000000000";
begin process(clk,dcount,state) begin LCD_DataBus <= dis (9 downto 2); LCD_RS <= dis(1); LCD_RW <= dis(0); if clk'event and clk='1' then dcount <= dcount +1;
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if(dcount="11111111111") then state<= state+1; ledcount<=ledcount+1; CASE state IS WHEN 1=> dis <= command (FUNCTION_SET); WHEN 2=> dis <= command (DISPLAY_ON); WHEN 3=> dis <= command (SET_DD_RAM_Address_80); WHEN 6=> dis <= lcd_display(LCD1); WHEN 7=> dis <= lcd_display(LCD2); WHEN 8=> dis <= lcd_display(LCD3); WHEN 9=> dis <= lcd_display(LCD4); WHEN 10=> dis <= lcd_display(LCD5); WHEN 11=> dis <= lcd_display(LCD6); WHEN 12=> dis <= lcd_display(LCD7); WHEN 13=> dis <= lcd_display(LCD8); WHEN 14=> dis <= lcd_display(LCD9); WHEN 15=>
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TEAM S^4
dis <= lcd_display(LCD10); WHEN 16=> dis <= lcd_display(LCD11); WHEN 17=> dis <= lcd_display(LCD12); WHEN 18=> dis <= lcd_display(LCD13); WHEN 19=> dis <= lcd_display(LCD14); WHEN 20=> dis <= lcd_display(LCD15); WHEN 21=> dis <= lcd_display(LCD16); WHEN 22=> dis <= command ("11000000"); WHEN 23=> dis <= lcd_display(LCD17); WHEN 24=> dis <= lcd_display(LCD18); WHEN 25=> dis <= lcd_display(LCD19); WHEN 26=> dis <= lcd_display(LCD20); WHEN 27=> dis <= lcd_display(LCD21); WHEN 28=> dis <= lcd_display(LCD22); WHEN 29=> dis <= lcd_display(LCD23); WHEN 30=>
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dis <= lcd_display(LCD24); WHEN 31=> dis <= lcd_display(LCD25); WHEN 32=> dis <= lcd_display(LCD26); WHEN 33=> dis <= lcd_display(LCD27); WHEN 34=> dis <= lcd_display(LCD28); WHEN 35=> dis <= lcd_display(LCD29); WHEN 36=> dis <= lcd_display(LCD30); WHEN 37=> dis <= lcd_display(LCD31); WHEN 38=> dis <= lcd_display(LCD32); when 39=> state<=3; WHEN OTHERS => END CASE; end if; if dcount <= "00000000111" then lcd_E <='1'; else lcd_E<='0'; end if; if ledcount<=5000 then data<="01010101"; else if ledcount>5000 and ledcount<=10000 then data<="10101010";
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else if ledcount>10000 then ledcount<=0; end if; end if; end if;
end if; end process; end behav_lcd;
7.2.3 LCD FUNCTION

library ieee; use ieee.std_logic_1164.ALL; package FUNCTION_SET is function command(x : std_logic_vector) return std_logic_vector ; function lcd_display(x : std_logic_vector) return std_logic_vector ; end ; package body FUNCTION_SET is function command(x : std_logic_vector) return std_logic_vector is variable lcd_data : std_logic_vector (9 downto 0); -- std_ulogic? variable rs : std_logic :='0'; variable rw : std_logic :='0'; begin lcd_data(9 downto 2) := x(7 downto 0); lcd_data(1) := rs; lcd_data(0) := rw; return lcd_data; end command;
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function lcd_display(x : std_logic_vector) return std_logic_vector is variable lcd_data : std_logic_vector (9 downto 0); -- std_ulogic? variable rs : std_logic :='1'; variable rw : std_logic :='0'; begin lcd_data(9 downto 2) := x(7 downto 0); lcd_data(1) := rs; lcd_data(0) := rw; return lcd_data; end lcd_display; end package body;
7.2.4 BINARY TO BCD

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; USE WORK.ASCII_PACKAGE.ALL; entity binbcd is port ( B: in STD_LOGIC_VECTOR (7 downto 0); data1,data2,data3 : out std_logic_vector(7 downto 0) ); end binbcd; architecture binbcd_arch of binbcd is signal P: STD_LOGIC_VECTOR (9 downto 0); begin bcd1: process(B) variable z: STD_LOGIC_VECTOR (17 downto 0); begin for i in 0 to 17 loop z(i) := '0'; end loop; z(10 downto 3) := B; for i in 0 to 4 loop
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if z(11 downto 8) > 4 then z(11 downto 8) := z(11 downto 8) + 3; end if; if z(15 downto 12) > 4 then z(15 downto 12) := z(15 downto 12) + 3; end if; z(17 downto 1) := z(16 downto 0); end loop; P <= z(17 downto 8); data1 <= '0' & '0' & '1' & '1' & P(3 downto 0); data2 <= '0' & '0' & '1' & '1' & P(7 downto 4); data3 <= '0' & '0' & '1' & '1' & '0' & '0' & P(9 downto 8); end process bcd1; end binbcd_arch;
7.2.5 SOLAR PANAL

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE WORK.ASCII_PACKAGE.ALL; entity SOLAR is port( CLK:IN STD_LOGIC; ------------ADC INTERFACING PORTS-----------adc_cs : inout std_logic; adc_read : inout std_logic; channel : out std_logic_vector(2 downto 0) := "000"; data_in : inout std_logic_vector(7 downto 0) := "00000000"; RELAY : out std_logic_vector(1 downto 0):="11"; ------------LCD DISPLAY PORTS--------lcd_rw : out std_logic; lcd_select : out std_logic; lcd_enable : out std_logic; lcd_data : out std_logic_vector(7 downto 0); limit_r : inout std_logic:='1'; limit_l : inout std_logic:='1' ); end SOLAR;
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architecture Behavioral of SOLAR is signal LDR1_1,LDR1_2,LDR1_3 : std_logic_vector(7 downto 0):=(others=>'0'); signal LDR2_1,LDR2_2,LDR2_3 : std_logic_vector(7 downto 0):=(others=>'0'); signal data1 : std_logic_vector(7 downto 0):=(others=>'0'); signal data2 : std_logic_vector(7 downto 0):=(others=>'0'); signal data3 : std_logic_vector(7 downto 0):=(others=>'0'); type LCD_Array is array (0 to 31) of std_logic_vector(7 downto 0); signal READ : LCD_Array; signal n1 : integer := 0; signal adc_reg,LDR_SENSOR1,LDR_SENSOR2 : std_logic_vector(7 downto 0); signal dclk1,dclk2,dclk3:std_logic_vector(22 downto 0); component binbcd is port ( B: in STD_LOGIC_VECTOR (7 downto 0); data1,data2,data3 : out std_logic_vector(7 downto 0) ); end component; component adc_test is port ( clk : in std_logic; adc_read : inout std_logic; adc_cs : inout std_logic; channel : out std_logic_vector(2 downto 0) := "000"; data_out : out std_logic_vector(7 downto 0) := "00000000"; n : inout integer:= 0 ; data_in : inout std_logic_vector(7 downto 0) := "00000000" ); end component; COMPONENT LCD_DISPLAY_MODULE is port( clk : in std_logic; LCD_RS, LCD_RW, LCD_E : out std_logic; LCD_DataBus : out std_logic_vector(7 downto 0); ------------LCD PANEL POSTION ---------===================================================================== =========
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LCD1,LCD2,LCD3,LCD4,LCD5,LCD6,LCD7,LCD8,LCD9,LCD10,LCD11,LCD12,LCD13,L CD14,LCD15,LCD16, LCD17,LCD18,LCD19,LCD20,LCD21,LCD22,LCD23,LCD24,LCD25,LCD26,LCD27,LCD28, LCD29,LCD30,LCD31,LCD32 -===================================================================== ========= : IN std_logic_vector(7 downto 0)); END COMPONENT; begin process(clk) begin if rising_edge(clk) then dclk2<=dclk2+1; end if; end process; process(clk) begin if rising_edge(clk) then dclk1<=dclk1+1; end if; end process; PROCESS(dclk2(22)) BEGIN if dclk2(22)'EVENT AND dclk2(22)='1' then --limit_r <='0' ; --limit_l <='0' ; end if; END PROCESS; PROCESS(dclk1(22)) variable RELAY1: std_logic_vector(1 downto 0):="11"; BEGIN --&&&&&&&&&&&&&&&&& COMPARISON &&&&&&&&&&&&&&&&& --------------------------------------------------IF(limit_r='0')THEN --RELAY<="00"; --else if dclk1(22)'EVENT AND dclk1(22)='1' then
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IF(LDR_SENSOR1>LDR_SENSOR2 and limit_r /='0' and limit_l /='0')THEN RELAY1:="10"; ELSif(LDR_SENSOR1<LDR_SENSOR2 and limit_r /='0' and limit_l /='0')THEN RELAY1:="01"; else RELAY1:="11"; dclk3<=dclk3+1; if dclk3(22)='1' then IF(LDR_SENSOR1>LDR_SENSOR2 )THEN RELAY1:="10"; ELSif(LDR_SENSOR1<LDR_SENSOR2 )THEN RELAY1:="01"; end if; end if;
END IF; -end if; RELAY<=RELAY1; --&&&&&&&&&&&&&&&&& <<<<<<<<=END=>>>>>>>&&&&&&&&&&&&&&&&& READ(0 to 31)<=(L,D,R,ONE,COLON,LDR1_3,LDR1_2,LDR1_1,SPACE,L,D,R,TWO,COLON,LDR2_3, LDR2_2,LDR2_1,SPACE,SPACE,SPACE,SPACE,SPACE,T,E,S,T,I,N,G,DOT,DOT,DOT);
--################### GETTING DATA #################### if (n1=4 )THEN-LDR_SENSOR1<=adc_reg;--LDR_SENSOR1 LDR1_1 <=data1; LDR1_2<=data2; LDR1_3 <=data3; ELSif (N1=3 )THEN--LDR_SENSOR1 LDR_SENSOR2<=adc_reg; LDR2_1 <=data1; LDR2_2 <=data2; LDR2_3<=data3; ELSE end if; --################ <<<<<<<<=END=>>>>>>>############################ -- RELAY<=RELAY1; END PROCESS;
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u1 : adc_test port map(clk,adc_read,adc_cs,channel,adc_reg,n1,data_in); u2 : binbcd port MAP(adc_reg,data1,data2,data3); HD44780 : LCD_DISPLAY_MODULE port map (clk, lcd_select, lcd_rw, lcd_enable,lcd_data, ------------LCD PANEL POSTION ---------===================================================================== ========= READ(0),READ(1),READ(2),READ(3),READ(4),READ(5),READ(6),READ(7),READ(8),RE AD(9),READ(10),READ(11),READ(12),READ(13),READ(14),READ(15), READ(16),READ(17),READ(18),READ(19),READ(20),READ(21),READ(22),READ(23),RE AD(24),READ(25),READ(26),READ(27),READ(28),READ(29),READ(30),READ(31) -===================================================================== ========= ); end Behavioral;
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8. FUTURE ENHANCEMENT
Beginning with the surge in coal use which accompanied the Industrial Revolution, energy consumption has steadily transitioned from wood and biomass to fossil fuels. The early development of solar technologies starting in the 1860s was driven by an expectation that coal would soon become scarce. However development of solar technologies stagnated in the early 20th century in the face of the increasing availability, economy, and utility of coal and petroleum. The 1973 oil embargo and 1979 energy crisis caused a reorganization of energy policies around the world and brought renewed attention to developing solar technologies. Deployment strategies focused on incentive programs such as the Federal Photovoltaic Utilization Program in the US and the Sunshine Program in Japan. Other efforts included the formation of research facilities in the US (SERI, now NREL), Japan (NEDO), and Germany (Fraunhofer Institute for Solar Energy Systems ISE). Commercial solar water heaters began appearing in the United States in the 1890s. These systems saw increasing use until the 1920s but were gradually replaced by cheaper and more reliable heating fuels. As with photovoltaics, solar water heating attracted renewed attention as a result of the oil crises in the 1970s but interest subsided in the 1980s due to falling petroleum prices. Development in the solar water heating sector progressed steadily throughout the 1990s and growth rates have averaged 20% per year since 1999. Although generally underestimated, solar water heating is by far the most widely deployed solar technology with an estimated capacity of 154 GW as of 2007. Our project focuses on the use of solar energy with maximum efficiency. Apart from the obvious uses in household applications with some enhancements; the specific uses lie in the military applications and autonomous wireless sensor nodes. The model developed basically focuses on the unidirectional focusing. By adding another set of motors; we can make the solar cell rotate in the ground plane in complete 360 degrees. This would make ultra-efficient, suitable
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for military applications. This development is left to the future group planning to work on our project.
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9. RESULT
The goal of the project was satisfied. By maximizing the use of solar energy, we are on our way to create more efficient autonomous modules in the future.
SIMULATION OUTPUT
Figure 4.1
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IMPLEMENTATION
Figure 4.2
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10. REFERENCES
[1] A. Kansal and M. Srivastava, An environmental energy harvesting framework for sensor networks, in Proc. IEEE ISLPED, Aug. 2003, pp. 481486. [2] D. L. King and M. E. Buck, Experimental optimization of ananisotropic etching process for random texturization of silicon solar cells, in Proc. IEEE PV Spec. Conf., 1991, pp. 303308. [3] C. Park and P. H. Chou, AmbiMax: Efficient, autonomous energy harvesting system for multiple -supply wireless sensor nodes, in Proc. IEEE SECON, Sep. 2006, pp. 168177. [4] R. Amirtharajah and A. Chandrakasan, A micropower programmable DSP using approximate signal processing based on distributed arithmetic, IEEE J. Solid.-State Circuits, vol. 39, no. 2, pp. 337347, Feb. 2004. [5] M. Scott, B. Boser, and K. Pister, An ultralow-energy ADC for smart dust, IEEE J. Solid.-State Circuits, vol. 38, no. 7, pp. 11231129, Jul. 2003. [6] B. Otis, Y. Chee, and J. Rabey, A 400 _W-Rx, 1.6 mW-Tx superregenerative transceiver for wireless sensor networks, in Proc. IEEE ISSC, Feb. 2005, vol. 606, pp. 396397. [7] R. Amirtharajah, A. Chen, D. Thaker, and F. T. Chong, Circuit interfaces and optimization for resistive nanosensors, in Proc. SPIE, Nov. 2005, pp. 115. [8] N. Guilar, A. Chen, T. Kleeburg, and R. Amirtharajah, Integrated solar energy harvesting and storage, in Proc. IEEE ISLPED, 2006, pp. 2024. [9] I. Fujimori, C.Wang, and C. Sodini, A 256 256 CMOS differential passive pixel imager with FPN reduction techniques, IEEE J. Solid.- State Circuits, vol. 35, no. 12, pp. 20312037, Dec. 2000. [10] G. E. Bunea, K. E. Wilson, Y. Meydbray, M. P. Campbell, and D. M. De Ceuster, Low light performance of mono-crystalline silicon solar cells, in Proc. Photovoltaic Energy Conv. Conf., May 2006, pp. 13121314. [11] R. M. Swanson, Approaching the 29% limit efficiency of silicon solar cells, in Proc. IEEE Photovoltaic Specialists Conf., 2005, pp. 889894. [12] E. Maruyama, A. Terakawa, M. Taguchi, Y. Yoshimine, D. Ide, T. Baba, M. Shima, H. Sakata, and M. Tanaka, Sanyos challenges to the development of high -efficiency HIT solar cells and the expansion of HIT business, in Proc. IEEE Photovoltaic Energy Conv. Conf., 2006, pp. 14551460. [13] T. Tiedje, E. Yablonovitch, G. Cody, and B. G. Brooks, Limiting efficiency of silicon solar cells, IEEE Trans. Electron Devices, vol. ED-31, no. 5, pp. 711716, May 1984. [14] Y. Carts-Powell, Let the sun shine in [solar cell used as energy], IEE Review, vol. 52, no. 2, pp. 2831, Feb. 2006. [15] A. Barnett, C. Honsberg, D. Kirkpatrick, S. Kurtz, D. Moore, D. Salzman, R. Schwartz, J. Gray, S. Bowden, K. Goossen, M. Haney, D. Aiken, M. Wanlass, and K. Emery, 50% efficient solar cell architectures and designs, in Proc. IEEE Photovoltaic Energy Conv. Conf., 2006, pp. 25602564. [16] J. Szlufcik, S. Sivoththaman, J. F. Nlis, R. P. Mertens, and R. Van Overstraeten, Low-cost industrial technologies of crystalline silicon solar cells, Proc. IEEE, vol. 85, no. 5, pp. 711730, May 1997. ELECTRONICS AND COMMUNICATION,MVJCE
Page 80
TEAM S^4
[17] J. S. Lee, R. I. Hornsey, and D. Renshaw, Analysis of CMOS photodiodes - Part I: Quantum efficiency, IEEE Trans. Electron Devices, vol. 50, no. 5, p. 2184, May 2003, 2184. [18] J. S. Lee, R. I. Hornsey, and D. Renshaw, Analysis of CMOS photodiodes - Part II: Lateral photoresponse, IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 12391245, May 2003. [19] P. B. Catrysse, P. , and B. A. Wandell, Optical efficiency of image sensor pixels, J. Opt. Soc. Amer., vol. 19, no. 8, pp. 16101620, Aug. 2002. [20] Agilent Inc., Santa Clara, CA, Advanced design systems software package (ADS 2005A), 2005. [21] R. Aparicio and A. Hajimiri, Capacity limits and matching properties of integrated capacitors, IEEE J. SolidState Circuits, vol. 37, no. 3, pp. 384393, Mar. 2002. [22] J.-P. Colinge and C. A. Colinge, Physics of Semiconductor Devices. Norwell, MA: Kluwer, 2002. [23] P. Yeh, Optical Waves in Layered Media. New York: Wiley, 1991. [24] R. M. A. Azzam and N. M. Bashara, Ellipsometry and Polarized Light. Amsterdam, The Netherlands: NorthHolland Physics, 1977. [25] C. C. Ho, D. A. Steingart, J. P. Salminen, W. H. Sin, T. M. K. Rantala, J. W. Evans, and P. K. Wright, Dispenser printed electrochemical capacitors for power management of millimeter scale lithium ion polymer microbatteries for wireless sensors [26] J. M. Bendickson, E. N. Glytsis, T. K. Gaylord, and D. L. Brundrett, Guid ed-mode resonant subwavelength gratings: Effect of finite beams and finite size, J. Opt. Soc. Amer., vol. A 18, pp. 19121928, 2001. [27] H. Tan, A. S. P. Chang, W. Wu, Z. Yu, S. Bai, and S. Y. Chou, A tunable subwavelength resonant grating optical filter, in Proc. IEEE LEOS, 2002, pp. 825826. [28] P. B. Catrysse and B. A.Wandell, Integrated color pixels in 0.18 - m complementary metal oxide semiconductor technology, J. Opt. Soc. Amer., vol. 20, no. 12, pp. 22932305, Dec. 2003. [29] R. Amirtharajah, J.Wenck, J. Collier, J. Siebert, and B. Zhou, Circuits for energy harvesting sensor signal processing, in Proc. AMC/IEEE Des. Autom. Conf., Jul. 2006, pp. 639644. [30] A. Sinha, A. Wang, and A. Chandrakasan, Energy scalable system design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 2, pp. 135145, Apr. 2002. [31] D. Malacara, Optical Shop Testing. New York: Wiley, 1992. [32] A. E. Siegman, Lasers. Mill Valley, CA: University Square, 1986. [33] E. O. Torres, M. Chen, H. P. Forghani-zadeh, V. Gupta, N. Keskar, L. A. Milner, H.-I. Pan, and G. A. RinconMora, SiP integration of intelligent, adaptive, self-sustaining power management solutions for portable applications, in Proc. IEEE ISCAS, May 2006, pp. 2124. [34] H. Lhermet, C. Condemine, M. Plissonnier, R. Salot, P. Audebert, and M. Rosset, Energy power management circuit: Thermal energy harvesting to above-IC microbattery energy storage, in Proc. IEEE ISSCC, 2007, p. 62. [35] G. Carchon, X. Sun, G. Posada, D. Linten, and E. Beyne, Thin -film as enabling passive integration technology for RF SoC and SiP, in Proc. IEEE ISSCC, 2005, pp. 398399.
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TEAM S^4
[36] F. Simjee and P. H. Chou, Everlast: Long-life, supercapacitor-operated wireless sensor node, in Proc. IEEE ISLPED, Oct. 2006, pp. 197202. [37] X. Jiang, J. Polastre, and D. Culler, Perpetual environmentally powered sensor networks, in Proc. 4th Int. Conf. Inf. Process. Sensor Netw., Apr. 2005, pp. 463468. [38] The International Technology Roadmap for Semiconductors, Executive Summary, [Online]. Available: http://www.itrs.net/links/ 2005ITRS/ExecSum2005.pdf [39] Maxwell Technologies, PC series datasheet, 2006. [Online]. Available: www.maxwell.com [40] New Energy Systems New Electroluminescent Systems, NessCap Ultracapacitor Datasheet, 2006. [Online]. Available: www.nesscap.com [41] Cap-XX, Product BulletinGW1 Series, 2006. [Online]. Available: www.cap-xx.com [42] AVX Corp., BestCap datasheet, 2006. [Online]. Available: www.avxcorp.com [43] Cooper Power Systems, Aerogel Supercapacitor Datasheet, 2006. [Online]. Available: www.cooperpower.com [44] P. F. Ribeiro, B. K. Johnson, M. L. Crow, A. Arsoy, and Y. Liu, Energy storage systems for advanced power applications, Proc. IEEE, vol. 89, no. 12, pp. 17441756, Dec. 2001. [45] G. L. Bullard, H. B. Sierra-Alcazar, H. L. Lee, and J. L. Morris, Operating principles of the ultracapacitor, IEEE Trans. Magn., vol. 25, no. 1, pp. 102106, Jan. 1989. [46] Panasonic, Lithium Ion Battery CGA52346B: Prismatic Model Datasheet, 2006. [Online]. Available: www.panasonic.com [47] R. Degraeve, N. Pangon, B. Kaczer, T. Nigam, G. Groeseneken, and A. Naem, Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability, in Proc. IEEE Symp. VLSI Technol., Jun. 1999, pp. 5960. [48] Panasonic, Multilayer ceramic capacitors datasheet, 2006. [Online]. Available: www.panasonic.com [49] P. Wright, FIREPower. 2007, (private communication).
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INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

3.1 BLOCK DIAGRAM (SIMULATION)

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

3.2 BLOCK DIAGRAM (IMPLEMENTATION)

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

3.3 Project Module /requirement

1. Getting knowledge in vhdl 2. Tools to be used:

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series

Xilinx Spartan 3/Spartan 3E XC3S1003TQ144/XC3S250EPQ208

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

4.1 FPGA POWER SUPPLY

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

4.2 FPGA KIT CIRCUIT

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

4.3 OVERALL CIRCUIT DIAGRAM

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

5.1 DC MOTOR FORWARD REVERSE CONTROL

Circuit working Description

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

5.2 Analog-to-Digital Converter (ADC)

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

What, Exactly, Does an Analog to-Digital Converter Do?

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

Output = 2n x G x AIN / VREF

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

5.3 Field Programmable Gate Array (FPGA)

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

EVOLUTION OF PROGRAMMABLE LOGIC DEVICES

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

ELECTRONICS AND COMMUNICATION,MVJCE

INTEGRATED SOLAR ENERGY HARVESTING AND STORAGE

5.4 SPARTAN 3-E

Manufacturer: Order Code: Manufacturer Part No: