Hands-On On VHDL

By:- Saurabh Singh Sr.Asst.Prof Sr.Asst.Prof. Dept. Of CSE BIT Durg Saurabh_singh1983@rediffmail.com

VHDL
I/P O/P

SUD System Under Design

VHDL
O/P I/P

Input And Output are Interface of Digital System. IN VHDL it is known as Ports

SUD System Under Design

VHDL

SUD System Under Design

Functional Discription of SUD

VHDL
Functional Description of SUD is Known as ARCHITECTURE. There are 3 Basic Style for describing the ARCHITECTURE Behavioural Style- Most Abstract,Sequential Data Flow Style- Concurrent Stmt. Structural Style- Most detail Level of Abstraction (ONE CAN MIX ALL OF THEM)

KEY TERMS
Named Identifier:- Object in VHDL, such as entity,architecture,port,signal etc. Reserved Keyword:Keyword: A word that is part of the language and may not be used as a named identifier. Library:- Collection of VHDL design unit that have been previously compiled. Package:- A Group of Uncompiled VHDL Design Element that can be used by more than on VHDL File

Points To Remember
VHDL is Case In Sensitive Comments:--- Decimal Integers:- 1,2 ,3_455 Based Integer :- 2#1001,16#0011_0000 Signal:- An Intenal Connection with in VHDL Architecture that connects parts of design together

Structure of VHDL Programe

Package (optional) Entity (design I/0) Architecture (design function)

concurrent statements Signal declaration Component instantiation statement Conditional signal assignment statement Selected signal assignment statement Generate statement Process statement sequential statements Variable declaration Signal assignment Variable assignment Procedure call if, case, loop, next, exit, return Wait statement

Documentation Part

Library and Package Part

ENTITY and Port Part

ARCHITECTURE PART

VHDL Object Declarations

Constant Signal Variable File How to Use
Object_NameName_Identifier:Type [range_Constraint] [:= Expression]

VHDL Object Declarations

Object Name for object Type

-:Example: :Example:Signal s : Bit :=`1` Signal s1 : std_logic_vector(3 downto 0)

Range constraint

VHDL Operator
Logical Operator Operator:-works boolean,std_logic, vector length.Not on integer. integer on bit, of equal

Relational Operator Operator:-Compare two operands of the same type and produce a boolen(<,>,<=,>=) Arithmatic Operands:Operands Works on ineger ,real,std_logic Concatenation:- '&'(abb (abb &wsx=abbwsx)

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Signals and Variables

Both Both are used to represent wires and/or logic Signals Signals are used to transfer data between processes and components < = when assigning to signals Variables Variables can only be used inside processes Variable Variable assignment is immediate, while signal assignment in a process occurs after leaving the process : = when assigning to variables

Writing and Understanding VHDL Prog.

Library and Package

Name of library Package Name All Item

Use Lib_name.package_name.item_name Example Use IEEE.STD_LOGIC_1164.all

Entity and Ports

MODE of Port

entity encoder is Type of Port port (a,b: in std_logic; enable : in std_logic; y : out std_logic_vector (3 downto 0) ); end encoder;
Defines I/O ONLY
if this is the top level entity for you design, the port lists your pins for a lower level entity, ports are like ports on schematic symbol

No hint of underlying structure

Architecture Body
Architecture name_arch OF Entity_name IS
Used for declaration of signal

begin
Used for programming One can Use any Modeling style Data Flow Concurrent Structural Mixed

end name_arch

Design of Full Adder

entity fa is Port ( a,b,cin : in STD_LOGIC; sum,carry : out STD_LOGIC); end fa;

Design of Full Adder

architecture Behavioral of fa is begin sum <= (a xor b)xor cin; carry <= (a and b) or (cin and(a xor b)); end Behavioral;
WHEN CONCURRENT STMT. WILL EXCUTE ?
Concurrent Stmt.

Design of Full Adder

architecture Behavioral of fa is signal axor,a_and : std_logic; begin axor <= a xor b; a_and <= a and b; sum <= axor xor cin; carry <= a_and or (cin and axor);
Use internal signal

architecture Behavioral of fa is
begin process (a,b,cin) variable axor,a_and : std_logic; begin axor := a xor b; a_and := a and b; sum <= axor xor cin; carry <= a_and or (cin and axor); end process; end Behavioral;

Design of Full Adder

Use of Preocess Behavioral modeling

The Process Stmt.

Process ( S_LIST)
Used for declaration of Variable

begin
Sequential Stmt.

end process;

The Process Stmt.

In side process we can use following stmt. IF condition THEN sequential stmt. {ELSIF condition THEN stmt} [ ELSE sequential stmt ] end if;

The Process Stmt.

In side process we can use following stmt. CASE expression IS WHEN choices-1 1 => sequenc of stmt WHEN choices-n n => sequenc of stmt WHEN OTHERS => stmt. END CASE;

Ex. of IF Stmt.
architecture behv of D_latch is begin process(data_in, enable) begin if (enable='1') then -- no clock signal here data_out <= data_in; end if; end process; end behv;

EX.of CASE Stmt.

architecture behv of ALU is begin process(A,B,Sel) begin case Sel is when "00" => Res <= A + B; when "01" => A + (not B) + 1; when "10" => Res <= Res <= A and B; when "11" => Res <= A or B; when others => Res <= "XX"; end case;

end process; end behv;

Concurrent Stmt.
target_signal <= Val WHEN condition ELSE WITH expression SELECT

target_signal <= val1 Val1 WHEN Condition WHEN choices, ELSE val2 WHEN choices, Val2; val3 WHEN OTHERS

Conurrent Stmt.
architecture behv of D_latch is begin data_out <= data_in when (enable ='1') else 'Z';
Vlaue or Expression Key Word

end behv;

Target Signal Condition