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Microelectronic Circuits Fourth Edition Adel S. Sedra, Kenneth C. Smith, 1998 Oxford University Press
Dr. Mehmet Sira zerdem Elektrik Elektronik Mh. Blm Dicle niversitesi
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm. Microelectronic Circuits - Fifth Edition Sedra/Smith
Copyright 2004 by Oxford University Press, Inc.
Sedra/Smith
Operation with no Gate Voltage Back-to-back diodes exist in series between D and S The path between D and S has a high resistance
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Creating a Channel
The enhancement-type NMOS transistor with VGS > 0 An n channel is induced at the top of the substrate beneath the gate. When VGS > Vt (threshold voltage), channel is induced
Microelectronic Circuits - Fifth Edition
Specifically, the channel conductance is proportional to vGS Vt and thus iD is proportional to (vGS Vt) and vDS.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Microelectronic Circuits - Fifth Edition Sedra/Smith
Copyright 2004 by Oxford University Press, Inc. 7
Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS Vt the channel is pinched off at the drain end. Increasing vDS above vGS Vt has little effect (theoretically, no effect) on the channels shape.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
iD versus vDS for an enhancement-type NMOS transistor operated with vGS > V Microelectronic Circuitst- Fifth Edition Sedra/Smith
Copyright 2004 by Oxford University Press, Inc.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
For obtaining iD current for saturation region, take the voltage, VDS, as follows,
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Aspect ratio
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
(a) Circuit symbol for the NMOS. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device Circuits - Fifth Edition Sedra/Smith operation isMicroelectronic unimportant. Copyright 2004 by Oxford University Press, Inc.
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated.
Microelectronic Circuits - Fifth Edition Sedra/Smith (b) The iDvDS characteristics for a device with kn Inc. (W/L) = 1.0 mA/V2. Copyright 2004 by Oxford University Press,
Linear correlation (linear resistance) rDS can be controlled by VGS voltage Microelectronic Circuits - Fifth Edition Sedra/Smith
Copyright 2004 by Oxford University Press, Inc.
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Vt = 1 V
kn (W/L) =1.0 mA/V2
The iDvGS characteristic for an enhancement-type NMOS transistor in saturation Microelectronic Circuits - Fifth Edition Sedra/Smith
Copyright 2004 by Oxford University Press, Inc.
Ideal model
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vGS - Vt = vDS
substitute it in the either triode region equation or the saturation region equation.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in the saturation region.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by L).
The n-channel MOSFET
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.
The n-channel MOSFET
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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(a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the case the substrate (B) is connected to the source (S).
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Vt = 4 V and kn(W/L) = 2 mA/V2 (a) transistor with current and voltage polarities indicated; (b) the iDvDS characteristics
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
The depletion Type n-channel MOSFET The relative levels of terminal voltages of a depletiontype NMOS transistor for operation in the triode and the saturation regions. The case shown is for operation in the enhancement mode (vGS is positive).
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Example
For a depletion_type NMOS transistor Vt = - 2V kn(W/L)=2m A/V2 a) Find the minimum VDS required to operate in the saturation region, when VGS=1V b) iD=?
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Example
For a depletion_type NMOS transistor Vt = - 2V kn(W/L)=4m A/V2 Neglect the effect of VDS on iD in the saturation region Vs = ?
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Conceptual circuit utilized to study the operation of Microelectronic Circuits - Fifth Edition Sedra/Smith the MOSFET as a small-signal Copyright 2004 amplifier. by Oxford University Press, Inc.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Voltage Gain
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Total instantaneous voltages vGS and vD Edition Sedra/Smith for the circuit. Microelectronic Circuits - Fifth Copyright 2004 by Oxford University Press, Inc.
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(a) neglecting the dependence of iD on vDS in saturation (the channel-length modulation effect); (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Example
Amplifier circuit
Equivalent-circuit model
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
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